CN115020415A - NVM (non-volatile memory) unit - Google Patents

NVM (non-volatile memory) unit Download PDF

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Publication number
CN115020415A
CN115020415A CN202210819205.7A CN202210819205A CN115020415A CN 115020415 A CN115020415 A CN 115020415A CN 202210819205 A CN202210819205 A CN 202210819205A CN 115020415 A CN115020415 A CN 115020415A
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China
Prior art keywords
junction diodes
nvm
nmos
well
active region
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CN202210819205.7A
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Chinese (zh)
Inventor
蔡磊
陈强
杨国庆
刘祥远
傅祎晖
谈斌
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Hunan Rongchuang Microelectronic Co ltd
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Hunan Rongchuang Microelectronic Co ltd
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Priority to CN202210819205.7A priority Critical patent/CN115020415A/en
Publication of CN115020415A publication Critical patent/CN115020415A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

The invention is suitable for the technical field of storage, and provides an NVM (non-volatile memory) storage unit which comprises a P-type doped substrate, an NMOS (N-channel metal oxide semiconductor) tube, two PN junction diodes and an N-well capacitor, wherein the NMOS tube, the two PN junction diodes and the N-well capacitor are all arranged on the P-type doped substrate, an active region is formed at the positions of the two PN junction diodes and the NMOS tube, a first part of polycrystalline grid is deposited in the active region and surrounded by the active region, and P < + > type injection doping of the two PN junction diodes surrounds two sides of the first part of polycrystalline grid. The NVM storage unit of the invention solves the problem of electric leakage of the NMOS tube after radiation and the problem of electric leakage between two adjacent NMOS tubes.

Description

NVM (non-volatile memory) unit
Technical Field
The invention belongs to the technical field of storage, and particularly relates to an NVM (non-volatile memory) storage unit.
Background
NVM is a non-volatile memory in which the storage of data in a floating gate type memory cell is accomplished by changing the threshold of the memory cell by storing an amount of charge in the floating gate, and the identification of data is accomplished by comparing the conduction currents of memory cells of different thresholds. However, the floating gate memory cell is susceptible to spatial radiation and data loss, especially to the total dose effect, i.e., the memory cell leakage current increases, resulting in data identification failure.
The main factor of the total dose effect of the conventional memory cell is caused by STI field oxide leakage, which mainly includes the leakage current of the parasitic channel of the NMOS transistor after irradiation and the leakage current of the conductive channel formed by the field oxide between two adjacent NMOS transistors, as shown in fig. 4.
Disclosure of Invention
The embodiment of the invention provides an NVM (non-volatile memory) storage unit, aiming at solving the problem that the traditional storage unit is influenced by space radiation and has data loss.
The embodiment of the invention provides an NVM (non-volatile memory) storage unit, which comprises a P-type doped substrate, an NMOS (N-channel metal oxide semiconductor) tube, two PN junction diodes and an N-well capacitor, wherein the NMOS tube, the two PN junction diodes and the N-well capacitor are all arranged on the P-type doped substrate, the two PN junction diodes are respectively and electrically connected with a source end and a drain end of the NMOS tube, one sides of the two PN junction diodes, which are far away from the NMOS tube, are respectively provided with a first parasitic channel and a second parasitic channel, and the N-well capacitor is arranged on the other side of the second parasitic channel.
An active region is formed at the positions of the two PN junction diodes and the NMOS tube, a first part of polycrystalline grid is deposited in the active region and surrounded by the active region, and the two sides of the first part of polycrystalline grid are surrounded by P + type injection doping of the two PN junction diodes.
Furthermore, the first part of the polycrystalline grid is in an H-shaped structure.
Furthermore, the P + type implantation doping of the two PN junction diodes also surrounds partial positions at two ends of the first part of the polycrystalline grid.
Furthermore, a second part of polycrystalline grid connected with the first part of polycrystalline grid is deposited at the position of the second parasitic channel and the N-well capacitor.
Furthermore, the second part of the polycrystalline grid is of an L-shaped structure.
Furthermore, the NMOS transistor is electrically connected with the N-well capacitor through the first part of polycrystalline grid and the second part of polycrystalline grid in sequence.
Furthermore, two ends of the NMOS tube and the N-well capacitor are respectively connected with metal wires through contact holes arranged on the NMOS tube and the N-well capacitor so as to be electrically connected with an external device.
Furthermore, two PN junction diodes also comprise N + type implantation doping.
Furthermore, an N well is formed at the position of the N well capacitor.
The invention achieves the following beneficial effects: the first part of polycrystalline grid is surrounded by the active region, a parasitic channel constructed by field oxygen is eliminated, and the two sides of the first part of polycrystalline grid are surrounded by P + type injection doping of the two PN junction diodes, so that electrons caused by radiation are absorbed, a leakage path is prevented, and the leakage path between two adjacent NMOS tubes is isolated, thereby solving the problems of leakage of the NMOS tubes after radiation and leakage between two adjacent NMOS tubes.
Drawings
FIG. 1 is a schematic diagram of a planar structure of an NVM memory unit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a lateral cross-section of an NVM memory unit according to an embodiment of the present invention;
FIG. 3 is an electrical schematic diagram of an NVM memory unit according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating the leakage current of a conventional memory cell.
Wherein, the substrate is doped with 1 and P types; 2. an NMOS tube; 3. a PN junction diode; 4. a first parasitic channel; 5. a second parasitic channel; 6. a third parasitic channel; 7. an active region; 8. a first portion of a poly gate; 9. p + type injection doping; 10. a second portion of the poly gate; 11. a contact hole; 12. a metal wire; 13. n + type injection doping; 14. an N-well capacitor; 15. an N well; 16. the overall poly gate.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. The "connection" in the following embodiments is understood as "electrical connection", "communication connection", or the like if the connected circuits, modules, units, or the like have electrical signals or data transmission therebetween.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, the terminology used in this specification includes any and all combinations of the associated listed items.
An NVM storage unit according to an embodiment of the present invention is shown in fig. 1 to 3, and includes a P-type doped substrate 1, an NMOS transistor 2, two PN junction diodes 3, and an N-well capacitor 14, where the NMOS transistor 2, the two PN junction diodes 3, and the N-well capacitor 14 are all disposed on the P-type doped substrate 1.
The two PN junction diodes 3 are respectively and electrically connected with the source end and the drain end of the NMOS tube 2, namely the two PN junction diodes 3 are respectively positioned on the source end side and the drain end side of the NMOS tube 2; a first parasitic channel 4 and a second parasitic channel 5 are respectively arranged on one sides of the two PN junction diodes 3 far away from the NMOS tube 2; the N-well capacitance 14 is disposed on the other side of the second parasitic channel 5. In addition, a third parasitic channel 6 is disposed on the other side of the N-well capacitance 14.
The two PN junction diodes 3 are constructed by implanting in the active region 7 a P + type implant doping 9 opposite to the first parasitic channel doping and the second parasitic channel doping, and correspondingly include an implanted N + type implant doping 13.
In particular, the NVM memory cells in this embodiment are fully compatible with standard CMOS processes, with very low cost.
In this embodiment, an active region 7 is formed at the positions of the two PN junction diodes 3 and the NMOS transistor 2, a first portion of poly-crystal gate 8 is deposited in the active region 7, the first portion of poly-crystal gate 8 is surrounded by the active region 7, and P + -type implantation dopants 9 of the two PN junction diodes 3 surround two sides of the first portion of poly-crystal gate 8.
The beneficial effect that this embodiment reached: the active region 7 surrounds the first part of the polycrystalline grid 8, a parasitic channel constructed by field oxygen is eliminated, the two sides of the first part of the polycrystalline grid 8 are surrounded by the P + type injection doping 9 of the two PN junction diodes 3, electrons caused by radiation are absorbed, a leakage path is prevented, and the leakage path between the two adjacent NMOS tubes 2 is isolated, so that the problems of electric leakage of the NMOS tubes 2 and electric leakage between the two adjacent NMOS tubes 2 after radiation are solved, meanwhile, the NVM storage unit in the embodiment has extremely strong capability of resisting total dose effect, and the capability of resisting the total dose effect exceeds 100krad (Si).
In this embodiment, the first portion of the poly gate 8 has an H-shaped structure. The width of the NMOS transistor 2 can be defined by adopting an H-type structure, so as to avoid the increase of the width of the NMOS transistor 2 caused by the active region 7 surrounding the first portion of the poly-gate 8, i.e. the width of the NMOS transistor 2 is limited by adding extra poly-gate structures at the source terminal and the drain terminal of the NMOS transistor 2, therefore, the size of the active region 7 is free, and the active region 7 in the NVM memory cell structure can be enlarged to exceed the width of the NMOS transistor 2.
In this embodiment, the P + type implantation dopants 9 of the two PN junction diodes 3 further surround the two ends of the first portion poly gate 8. This can further absorb electrons caused by radiation, prevent a leakage path, and isolate the leakage path between two adjacent NMOS transistors 2.
In this embodiment, a second partial poly gate 10 connected to the first partial poly gate 8 is further deposited at the positions of the second parasitic channel 5 and the N-well capacitor 14. The second portion of the poly-gate 10 and the first portion of the poly-gate 8 together constitute a total poly-gate 16 of the NVM memory cell.
Wherein, the second part of the polycrystalline grid 10 is of an L-shaped structure; the NMOS tube 2 is electrically connected with the N-well capacitor 14 through the first part polycrystalline grid 8 and the second part polycrystalline grid 10 in sequence.
In this embodiment, an N well 15 is formed at the position of the N well capacitor 14.
The size of the N-well capacitor 14 is determined by the overlapping portions of the first and second partial poly gates 8 and 10, the N-well 15 and the active region 7.
In this embodiment, the two ends of the NMOS transistor 2 and the N-well capacitor 14 are respectively connected to a metal line 12 through a contact hole 11, so as to be electrically connected to an external device.
The two ends of the NMOS tube 2 are respectively provided with a contact hole 11, and then each contact hole 11 is connected with a metal wire 12; correspondingly, a contact hole 11 is formed in the N-well capacitor 14, and then the contact hole is connected with a metal wire 12.
In this embodiment, the first partial poly gate 8 of the NMOS transistor 2 and the second partial poly gate 10 of the N-well capacitor 14 are connected together to form a floating gate for storing charges, and the control transistor, the tunneling transistor, and the select transistor of the NVM memory cell are integrated into one NMOS transistor 2, and there is no need to use the select transistor for write crosstalk protection. The source end and the drain end of the NMOS tube 2 are respectively and electrically connected with one PN junction diode 3 to limit leakage current brought by irradiation. The difference between the NMOS tube 2 in the NVM storage unit and the traditional method is that an enlarged active region 7 surrounds a first part of polycrystalline grid 8, the first part of polycrystalline grid 8 is used for determining the width of the storage tube, and P + type injection doping 9 is added on two sides of the NMOS tube 2 to form a PN junction diode 3 to cut off a side parasitic MOS tube. The NVM unit uses hot electron injection in programming and band-to-band tunneling hot hole injection in erasing, and the writing operation by adopting the two modes can reduce the high-voltage requirement and reduce the size. In addition, since the total dose effect of the space radiation is related to the voltage bias, the higher the voltage is, the more serious the total dose effect is, so that the writing high voltage is reduced, and the capability of the memory cell for resisting the total dose effect is effectively improved.
In this embodiment, the following table i shows voltages at each port during the read/write operation of the NVM memory cell:
table one, voltage of each port
WL SL BL
0 0 HV
HV VDD HV
VREAD 0 VREAD
VREAD is the read voltage, VDD is the power voltage, and HV is the write high voltage.
All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (9)

1. An NVM (non-volatile memory) storage unit is characterized by comprising a P-type doped substrate, an NMOS (N-channel metal oxide semiconductor) tube, two PN junction diodes and an N-well capacitor, wherein the NMOS tube, the two PN junction diodes and the N-well capacitor are all arranged on the P-type doped substrate, the two PN junction diodes are respectively and electrically connected with a source end and a drain end of the NMOS tube, one sides of the two PN junction diodes, which are far away from the NMOS tube, are respectively provided with a first parasitic channel and a second parasitic channel, and the N-well capacitor is arranged on the other side of the second parasitic channel;
an active region is formed at the positions of the two PN junction diodes and the NMOS tube, a first part of polycrystalline grid is deposited in the active region and surrounded by the active region, and the two sides of the first part of polycrystalline grid are surrounded by P + type injection doping of the two PN junction diodes.
2. The NVM memory cell of claim 1, wherein said first portion of said poly gate is in an H-type configuration.
3. The NVM memory cell of claim 2 wherein the P + implant doping of both of said PN junction diodes also surrounds portions of the locations at both ends of said first portion of the poly gate.
4. The NVM memory cell of claim 1, wherein said second parasitic channel and said N-well capacitance are further deposited at a location with a second portion of poly gate connected to said first portion of poly gate.
5. The NVM memory unit of claim 4, wherein the second portion of the poly-gate is in an L-type structure.
6. The NVM memory unit of claim 4, wherein the NMOS transistor is electrically connected to the N-well capacitor sequentially through the first and second partial poly gates.
7. The NVM storage cell of claim 1 wherein both ends of said NMOS transistor and said N-well capacitor are connected to metal lines through their own contact holes for electrical connection to external devices, respectively.
8. The NVM memory cell of claim 1, wherein both of said PN junction diodes further comprise N + type implant doping.
9. The NVM memory cell of claim 1, wherein said N-well capacitance is located with an N-well.
CN202210819205.7A 2022-07-13 2022-07-13 NVM (non-volatile memory) unit Pending CN115020415A (en)

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CN202210819205.7A CN115020415A (en) 2022-07-13 2022-07-13 NVM (non-volatile memory) unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210819205.7A CN115020415A (en) 2022-07-13 2022-07-13 NVM (non-volatile memory) unit

Publications (1)

Publication Number Publication Date
CN115020415A true CN115020415A (en) 2022-09-06

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