CN115017032A - FPGA code rule detection method, device and equipment - Google Patents

FPGA code rule detection method, device and equipment Download PDF

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Publication number
CN115017032A
CN115017032A CN202210374810.8A CN202210374810A CN115017032A CN 115017032 A CN115017032 A CN 115017032A CN 202210374810 A CN202210374810 A CN 202210374810A CN 115017032 A CN115017032 A CN 115017032A
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module
file
fpga code
rule
design class
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周勋
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Chengdu Dizhen Computer Technology Co ltd
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Chengdu Dizhen Computer Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3624—Software debugging by performing operations on the source code, e.g. via a compiler
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/42—Syntactic analysis
    • G06F8/427—Parsing

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Abstract

The invention discloses a method, a device and equipment for detecting FPGA code rules, wherein the method comprises the following steps: generating a coding rule set; generating a syntax tree and loading the syntax tree into a data structure taking a module as a unit; creating a unified design class, and storing the module of each FPGA code file and the module information into the design class; setting a top-level file and a top-level module to generate a calling hierarchical graph; and carrying out rule scanning detection on the code by taking the module as a unit according to the calling logic of the calling hierarchical graph by utilizing the coding rule set. The invention can be compatible with various coding rules, realizes the check of various FGPA coding files, can realize the detection of mixed codes by establishing a unified design class, and improves the code detection efficiency.

Description

FPGA code rule detection method, device and equipment
Technical Field
The invention belongs to the technical field of code detection, and particularly relates to a method, a device and equipment for detecting FPGA code rules.
Background
With the gradually increasing scale of an FPGA (Field Programmable Gate Array), the number of resources carrying logic and the complexity of the devices are increased, so that the FPGA code for realizing the FPGA software function is more complex. In order to ensure the quality of software development, a software developer or a tester can write unit tests and integrated tests to verify the correctness of the logic processing of the codes in the development stage.
In the prior art, HDL (High-Speed Integrated Circuit Hardware Description Language) code rule detection tools that have been widely used mainly include: HDL designer, LEDA, Nlingt, Alint and the like, but the software interface of the HDL code rule detection tool does not support Chinese, the rule description is not easy to understand, and a detection method for certain standard coding rules in China is lacked. For example: in the aerospace field, in order to improve the code quality of aerospace type FPGA products, the second research institute of aerospace science and engineering in China sets up the programming standard of Q/WE1117-2014 institute type FPGA hardware description language to standardize the design of FPGA codes. However, at present, no FPGA code detection tool can be compatible with the coding rule, so that the code quality of an FPGA product in the aerospace field cannot be guaranteed.
Disclosure of Invention
The invention aims to provide a method, a device and equipment for detecting FPGA code rules, which are used for solving at least one technical problem in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a method for detecting FPGA code rules, including:
selecting a corresponding coding rule set according to a plurality of FPGA code files to be detected;
taking a file as a unit, carrying out syntax analysis on each FPGA code file to generate a syntax tree, and loading the syntax tree into a data structure taking a module as a unit;
creating a design class by taking a project as a unit, and storing a module and module information in each FPGA code file into the design class, wherein the project comprises a plurality of FPGA code files, and the module information at least comprises a modularized syntax tree;
setting a top-level file and a top-level module, automatically matching called sub-modules for the top-level module based on the design class, and generating a calling hierarchical diagram;
and carrying out rule scanning detection on the codes in the design class by using the coding rule set and taking a module as a unit according to the calling logic of the calling hierarchical diagram.
In one possible design, the method further includes:
if the violation information exists, the violation information is saved, exported in a file form and fed back to a user interface, wherein the user interface is a Chinese interface.
In one possible design, the FPGA code file includes a verilog file and/or a vhdl file.
In one possible design, the modules and module information in each FPGA code file are stored into the design classes, including:
and regarding the verilog file, taking each module node as a verilog module, and storing each verilog module and the syntax tree, the file path, the module name and/or the calling sub-module information of the module into the design class.
In one possible design, storing the modules and module information in each FPGA code file into the design class includes:
for a vhdl file, searching each entity of the vhdl file, matching a corresponding structural body for each entity, and combining each entity and the corresponding structural body to generate a vhdl module;
and storing the vhdl module, the syntax tree of the module, the file path, the module name and/or the calling sub-module information into the design class.
In one possible design, after automatically matching the called sub-modules for the top-level module based on the design class, the method further comprises:
and identifying whether the submodule called by the top module is a valid submodule, if so, carrying out white box test on the current submodule, and if not, carrying out black box test on the current submodule.
In one possible design, the encoding rules include at least the military standard 9765-.
In one possible design, a coding example and modification opinions are correspondingly arranged in each coding rule.
In a second aspect, the present invention provides an FPGA code rule detection apparatus, including:
the module selection rule set is used for selecting a corresponding coding rule set according to a plurality of FPGA code files to be detected;
the parsing module generates a syntax tree, and is used for carrying out syntax parsing on each FPGA code file by taking the file as a unit to generate the syntax tree and loading the syntax tree into a data structure by taking the module as a unit;
the system comprises a design class creating module, a syntax tree generating module and a syntax tree generating module, wherein the design class creating module is used for creating a design class by taking a project as a unit and storing a module and module information in each FPGA code file into the design class, the project comprises a plurality of FPGA code files, and the module information at least comprises a modular syntax tree;
the hierarchical diagram generating module is used for setting a top-level file and a top-level module, automatically matching and calling the top-level module with a called sub-module based on the design class and generating a calling hierarchical diagram;
and the rule detection module is used for carrying out rule scanning detection on the codes in the design class by taking the module as a unit according to the calling logic of the calling hierarchical diagram by utilizing the coding rule set.
In one possible design, the apparatus further includes:
and the violation information feedback module is used for saving the violation information and then exporting and feeding back the violation information to a user interface in a file form if the violation information exists, wherein the user interface is a Chinese interface.
In one possible design, the FPGA code file includes a verilog file and/or a vhdl file.
In one possible design, when the modules and module information in each FPGA code file are stored into the design class, the design class creation module is specifically configured to:
and regarding the verilog file, taking each module node as a verilog module, and storing each verilog module and the syntax tree, the file path, the module name and/or the calling sub-module information of the module into the design class.
In one possible design, when the modules and module information in each FPGA code file are stored into the design class, the design class creation module is specifically configured to:
for a vhdl file, searching each entity of the vhdl file, matching a corresponding structural body for each entity, and combining each entity and the corresponding structural body to generate a vhdl module;
and storing the vhdl module, the syntax tree of the module, the file path, the module name and/or the calling sub-module information into the design class.
In one possible design, after automatically matching the called sub-modules for the top-level module based on the design class, the hierarchical graph generation module is further configured to:
and identifying whether the submodule called by the top module is a valid submodule, if so, carrying out white box test on the current submodule, and if not, carrying out black box test on the current submodule.
In one possible design, the encoding rules include at least the military standard 9765-.
In one possible design, a coding example and modification opinions are correspondingly arranged in each coding rule.
In a third aspect, the present invention provides a computer device, comprising a memory, a processor and a transceiver, which are sequentially connected in communication, wherein the memory is used for storing a computer program, the transceiver is used for sending and receiving messages, and the processor is used for reading the computer program and executing the FPGA code rule detection method as described in any one of the possible designs of the first aspect.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon instructions which, when run on a computer, perform the FPGA code rule detection method as described in any one of the possible designs of the first aspect.
In a fifth aspect, the present invention provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the FPGA code rule detection method as described in any one of the possible designs of the first aspect.
Has the advantages that:
according to a plurality of FPGA code files to be detected, selecting corresponding coding rules and generating a coding rule set; then, taking the file as a unit, carrying out syntax analysis on each FPGA code file to generate a syntax tree, and loading the syntax tree into a data structure taking the module as a unit; then, with engineering as a unit, creating a design class to store all Verilog modules and vhdl modules; setting a top-level file and a top-level module, and automatically matching a called sub-module for the top-level module based on the design class to generate a calling hierarchical diagram; and carrying out rule scanning detection on the codes of the design classes by using the coding rule set and taking a module as a unit according to the calling logic of the calling hierarchical diagram. According to different FPGA code files, a plurality of preset coding rules are selected, and after the files are processed, the codes are subjected to rule scanning detection by using a coding rule set and taking a module as a unit, so that the effective detection of the FPGA codes is realized, and the method is particularly suitable for the universal detection of VHDL codes and Verilog codes in national defense and military industry FPGAs, and overcomes the defects of the prior art; the unified module class is set, and the modules of all files are stored in the design class, so that the mixed code detection can be realized, and the applicability of the method is improved.
Drawings
Fig. 1 is a flowchart of an FPGA code rule detection method in this embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments in the present description, belong to the protection scope of the present invention.
Examples
In order to solve the technical problems that the software interface of an HDL code rule detection tool in the prior art does not support Chinese, the rule description is not easy to understand, and a detection method for certain standard coding rules in China is lacked, the embodiment provides an FPGA code rule detection method, the method selects a plurality of preset coding rules according to different FPGA code files, then scans and detects the code rules by taking a module as a unit by using a coding rule set after processing the files, thereby realizing effective detection of FPGA codes, and particularly being applicable to general detection of VHDL codes and Verilog codes in the national defense and military project FPGA, and overcoming the defects of the prior art; the unified module classes are set, and the modules of all files are stored in the module classes, so that mixed code detection can be realized, and the applicability of the method is improved. The following examples are specifically described.
As shown in fig. 1, in a first aspect, this embodiment provides a method for detecting an FPGA code rule, which includes but is not limited to steps S101 to S105, and specifically includes:
s101, selecting a corresponding coding rule set according to a plurality of FPGA code files to be detected;
in step S101, the FPGA code file includes, but is not limited to, a verilog file and a vhdl (Very-High-Speed-Integrated Circuit Hardware Description Language) file, where the verilog file refers to a code file written by a Hardware Description Language verilog HDL (a Language that describes the structure and behavior of digital system Hardware in text form, and may represent a logic Circuit diagram, a logic expression, and may also represent a logic function completed by a digital logic system); the vhdl file refers to a code file written in the vhdl language.
In step S101, the encoding rules are a plurality of encoding rules preset in the system, including but not limited to chinese encoding rules and english encoding rules, such as: the army standard 9765-. Preferably, the Chinese encoding rule is 'Q/WE 1117-2014 Bid model FPGA hardware description language programming criterion'.
It should be noted that, in this embodiment, a plurality of FPGA code files are detected by taking engineering as a unit, so different FPGA code files may correspond to different encoding rules, and therefore, a corresponding encoding rule needs to be selected to form an encoding rule set, which is convenient for subsequent invocation.
In step S101, preferably, each of the encoding rules is correspondingly provided with an encoding example and a plurality of modification opinions, so that encoding personnel can be instructed to write and modify codes, and the efficiency of writing or rewriting subsequent codes is improved.
S102, taking a file as a unit, carrying out syntax analysis on each FPGA code file to generate a syntax tree, and loading the syntax tree into a data structure taking a module as a unit;
in step S102, since the FPGA code is in a module unit, after the code file generates the syntax tree, the syntax tree needs to be loaded into the data structure in a module unit to be adapted to the module. Preferably, after the syntax tree is generated, the syntax tree is optimized or simplified to generate an abstract syntax tree, and the abstract syntax tree is loaded into a data structure in units of modules.
The syntax parsing principle is to convert the tag expression into a syntax tree by using a specific syntax rule; preferably, lexical analysis can be performed on each FPGA code file, and the analysis principle is that lexical matching of character strings of input streams is completed by using a regular expression, and the matched lexical expression is returned in a tag mode, so that source codes are analyzed into tag expressions, and of course, semantic analysis and the like can be performed, which is not limited herein.
S103, creating a design class by taking a project as a unit, and storing a module and module information in each FPGA code file into the design class, wherein the project comprises a plurality of FPGA code files, and the module information at least comprises a modularized syntax tree;
it should be noted that, because there may be multiple entities or modules in each FPGA code file, in order to implement the sequential detection of all modules, as a specific implementation manner of step S103, the storing of the module and the module information in each FPGA code file into the design class includes:
for the verilog file, each module node is used as a verilog module, and syntax trees, file paths, module names and/or calling sub-module information of each verilog module and the modules are stored in the module class.
As a specific implementation manner of step S103, storing the module and the module information in each FPGA code file into the design class includes:
for a vhdl file, searching each entity of the vhdl file, matching a corresponding structural body for each entity, and combining each entity and the corresponding structural body to generate a vhdl module;
and storing the vhdl module, the syntax tree of the module, the file path, the module name and/or the calling sub-module information into the module class.
Based on the disclosure, the verilog module and the vhdl module are stored in the unified design class, so that when a mutual calling relationship exists between the verilog module and the vhdl module, mixed code detection can be realized based on the calling relationship between the verilog module and the vhdl module, each code file does not need to be detected independently, and the code detection efficiency and the applicability of the method are improved.
S104, setting a top-level file and a top-level module, automatically matching called sub-modules for the top-level module based on the design class, and generating a calling hierarchical diagram;
it should be noted that after the design classes of all modules are constructed in step S103, a top level file and a top level module need to be set to set an operation starting point for program invocation, so that by using one of the FPGA code files as the top level file and using one of the modules of the top level file as the top level module, the starting point for program operation can be established, and a calling hierarchical diagram is generated to implement subsequent sequence detection by automatically matching called sub-modules for the top level module based on the function of each code in the design classes.
In step S104, after automatically matching the called sub-module for the top-level module based on the design class, the method further includes:
and identifying whether the submodule called by the top-layer module is a valid submodule, if so, considering that the module has a source code, and performing a white box test on the current submodule, and if not, considering that the module does not have the source code, and performing a black box test on the current submodule.
And S105, scanning and detecting the code rule of the design class by taking a module as a unit according to the calling logic of the calling hierarchical diagram by utilizing the coding rule set.
In step S105, specifically, the code is scanned and detected in units of modules through a call logic between the modules, and violation information is identified, where the violation information includes, but is not limited to, a rule number, a violation description, a file path, a line number, a violation level, a comment, and the like.
In a specific embodiment, the method further comprises:
if the violation information exists, the violation information is saved, exported in a file form and fed back to a user interface, wherein the user interface is a Chinese interface.
Based on the disclosure, in the embodiment, a plurality of preset coding rules are selected according to different FPGA code files, and then after the files are processed, the codes are subjected to rule scanning detection by using a coding rule set and taking a module as a unit, so that the effective detection of the FPGA codes is realized, and the method is particularly applicable to the general detection of the VHDL codes and Verilog codes in the FPGA for national defense and military industry, and overcomes the defects of the prior art; the unified module class is set, and the modules of all files are stored in the design class, so that the mixed code detection can be realized, and the applicability of the method is improved.
In addition, the application of the embodiment finds that the embodiment has very quick response to code violation detection, can reach the rate that 1 ten thousand lines of code violation detection time is less than 5 minutes, and has very high code detection efficiency.
Based on the above disclosure, in this embodiment, according to a plurality of FPGA code files to be detected, a corresponding encoding rule is selected to generate an encoding rule set; then, taking the file as a unit, carrying out syntax analysis on each FPGA code file to generate a syntax tree, and loading the syntax tree into a data structure taking the module as a unit; then, with engineering as a unit, creating a design class to store all Verilog modules and vhdl modules; setting a top-level file and a top-level module, and automatically matching a called sub-module for the top-level module based on the design class to generate a calling hierarchical diagram; and performing rule scanning detection on the codes of the design classes by using the coding rule set and taking a module as a unit according to the calling logic of the calling hierarchical diagram. According to different FPGA code files, a plurality of preset coding rules are selected, and after the files are processed, the codes are subjected to rule scanning detection by using a coding rule set and taking a module as a unit, so that the effective detection of the FPGA codes is realized, and the method is particularly suitable for the universal detection of VHDL codes and Verilog codes in national defense and military industry FPGAs, and overcomes the defects of the prior art; the unified module class is set, and the modules of all files are stored in the design class, so that the mixed code detection can be realized, and the applicability of the method is improved.
In a second aspect, the present invention provides an FPGA code rule detection apparatus, including:
the module selection rule set is used for selecting a corresponding coding rule set according to a plurality of FPGA code files to be detected;
the parsing module is used for parsing each FPGA code file by taking the file as a unit to generate a syntax tree and loading the syntax tree into a data structure taking the module as a unit;
the design class creating module is used for creating a design class by taking engineering as a unit and storing modules and module information in each FPGA code file into the design class, wherein the engineering comprises a plurality of FPGA code files, and the module information at least comprises a modularized syntax tree;
the hierarchical diagram generating module is used for setting a top-level file and a top-level module, automatically matching called sub-modules for the top-level module based on the design class and generating a calling hierarchical diagram;
and the rule detection module is used for carrying out rule scanning detection on the codes in the design class by taking the module as a unit according to the calling logic of the calling hierarchical diagram by utilizing the coding rule set.
In one possible design, the apparatus further includes:
and the violation information feedback module is used for saving the violation information and then exporting and feeding back the violation information to a user interface in a file form if the violation information exists, wherein the user interface is a Chinese interface.
In one possible design, the FPGA code file includes a verilog file and/or a vhdl file.
In one possible design, when the modules and module information in each FPGA code file are stored into the design class, the design class creation module is specifically configured to:
and regarding the verilog file, taking each module node as a verilog module, and storing each verilog module and the syntax tree, the file path, the module name and/or the calling sub-module information of the module into the design class.
In one possible design, when the modules and module information in each FPGA code file are stored into the design class, the design class creation module is specifically configured to:
for a vhdl file, searching each entity of the vhdl file, matching a corresponding structural body for each entity, and combining each entity and the corresponding structural body to generate a vhdl module;
and storing the vhdl module, the syntax tree of the module, the file path, the module name and/or the calling sub-module information into the design class.
In one possible design, after automatically matching the called sub-modules for the top-level module based on the design class, the hierarchical graph generation module is further configured to:
and identifying whether the submodule called by the top-level module is a valid submodule.
In one possible design, the encoding rules include at least the military standard 9765-2020vhdl encoding rule, the military standard 10157-2021verilog encoding rule, the STARC encoding rule, the RMM encoding rule and/or the DO-254 encoding rule.
In a possible design, a coding case and modification opinions are set in each of the coding rules.
In a third aspect, the present invention provides a computer device, comprising a memory, a processor and a transceiver, which are sequentially connected in communication, wherein the memory is used for storing a computer program, the transceiver is used for sending and receiving messages, and the processor is used for reading the computer program and executing the FPGA code rule detection method as described in any one of the possible designs of the first aspect.
In a fourth aspect, the present invention provides a computer-readable storage medium having stored thereon instructions which, when run on a computer, perform the FPGA code rule detection method as set forth in any one of the possible designs of the first aspect.
In a fifth aspect, the present invention provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the FPGA code rule detection method as described in any one of the possible designs of the first aspect.
Finally, it should be noted that: the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. An FPGA code rule detection method is characterized by comprising the following steps:
selecting a corresponding coding rule set according to a plurality of FPGA code files to be detected;
taking a file as a unit, carrying out syntax analysis on each FPGA code file to generate a syntax tree, and loading the syntax tree into a data structure taking a module as a unit;
the method comprises the steps of establishing a design class by taking a project as a unit, and storing a module and module information in each FPGA code file into the design class, wherein the project comprises a plurality of FPGA code files, and the module information at least comprises a modularized syntax tree;
setting a top-level file and a top-level module, automatically matching called sub-modules for the top-level module based on the design class, and generating a calling hierarchical diagram;
and carrying out rule scanning detection on the codes in the design class by using the coding rule set and taking a module as a unit according to the calling logic of the calling hierarchical diagram.
2. The FPGA code rule detecting method of claim 1, further comprising:
if the violation information exists, the violation information is saved, exported in a file form and fed back to a user interface, wherein the user interface is a Chinese interface.
3. The FPGA code rule detection method of claim 1, wherein the FPGA code file comprises a verilog file and/or a vhdl file.
4. The FPGA code rule detection method of claim 3, wherein storing the modules and module information in each FPGA code file into the design class comprises:
and regarding the verilog file, taking each module node as a verilog module, and storing each verilog module and the syntax tree, the file path, the module name and/or the calling sub-module information of the module into the design class.
5. The FPGA code rule detection method of claim 3, wherein storing the modules and module information in each FPGA code file into the design class comprises:
for a vhdl file, searching each entity of the vhdl file, matching a corresponding structural body for each entity, and combining each entity and the corresponding structural body to generate a vhdl module;
and storing the vhdl module, the syntax tree of the module, the file path, the module name and/or the calling sub-module information into the design class.
6. The FPGA code rule detection method of claim 1, wherein after automatically matching called sub-modules for the top-level module based on the design class, the method further comprises:
and identifying whether the submodule called by the top module is a valid submodule, if so, carrying out white box test on the current submodule, and if not, carrying out black box test on the current submodule.
7. The FPGA code rule detection method as claimed in claim 1, wherein the encoding rules at least include the military standard 9765-2020vhdl encoding rule, the military standard 10157-2021verilog encoding rule, the STARC encoding rule, the RMM encoding rule and/or the DO-254 encoding rule.
8. The FPGA code rule detection method of claim 1, wherein each of the encoding rules is correspondingly provided with an encoding example and a plurality of modification opinions.
9. An FPGA code rule detection device, characterized by comprising:
the module selection rule set is used for selecting a corresponding coding rule set according to a plurality of FPGA code files to be detected;
the parsing module generates a syntax tree, and is used for carrying out syntax parsing on each FPGA code file by taking the file as a unit to generate the syntax tree and loading the syntax tree into a data structure by taking the module as a unit;
the system comprises a design class creating module, a syntax tree generating module and a syntax tree generating module, wherein the design class creating module is used for creating a design class by taking a project as a unit and storing a module and module information in each FPGA code file into the design class, the project comprises a plurality of FPGA code files, and the module information at least comprises a modular syntax tree;
the hierarchical diagram generating module is used for setting a top-level file and a top-level module, automatically matching called sub-modules for the top-level module based on the design class and generating a calling hierarchical diagram;
and the rule detection module is used for carrying out rule scanning detection on the codes in the design class by taking the module as a unit according to the calling logic of the calling hierarchical diagram by utilizing the coding rule set.
10. A computer device comprising a memory, a processor and a transceiver communicatively connected in sequence, wherein the memory is used for storing a computer program, the transceiver is used for transmitting and receiving messages, and the processor is used for reading the computer program and executing the FPGA code rule detection method according to any one of claims 1 to 8.
CN202210374810.8A 2022-04-11 2022-04-11 FPGA code rule detection method, device and equipment Pending CN115017032A (en)

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