CN115016948B - Resource access method and device, electronic equipment and readable storage medium - Google Patents
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Abstract
The application provides a resource access method, a resource access device, an electronic device and a readable storage medium, wherein the method comprises the following steps: responding to access requests of a plurality of threads to resources, and acquiring characterization information of the threads, wherein the characterization information is used for associating a thread synchronization strategy of a C/C + + library or a reentry structure strategy of an AOS kernel; and controlling a plurality of threads accessing the same resource to execute according to an access mechanism avoiding concurrence through the thread synchronization strategy and/or the reentry structure strategy based on the characterization information. In the method, a thread synchronization strategy is added to a C/C + + library and/or a reentry structure strategy is added to an AOS kernel to control a plurality of threads to execute an access mechanism, so that the problem of multi-thread concurrency in the access process is avoided.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a resource access method and apparatus, an electronic device, and a readable storage medium.
Background
In the product development process of the internet of things equipment, a native tool chain provided by a corresponding architecture such as ARM is generally directly used, and a C/C + + library is contained in the tool chain, but the C/C + + library is problematic for multithreading support.
This causes various concurrent multithreading problems in the resource access process based on the C/C + + library.
Disclosure of Invention
The problem to be solved by the application is that in the process of resource access of the existing C/C + + library, the problem of multi-thread concurrency is easy to occur.
In order to solve the above problem, a first aspect of the present application provides a resource access method, including:
responding to access requests of a plurality of threads to resources, and acquiring characterization information of the threads, wherein the characterization information is used for associating a thread synchronization strategy of a C/C + + library or a reentry structure strategy of an AOS kernel;
and controlling a plurality of threads accessing the same resource to execute according to an access mechanism avoiding concurrence through the thread synchronization strategy and/or the reentry structure strategy based on the characterization information.
A second aspect of the present application provides a resource access apparatus, including:
the characterization acquisition module is used for responding to access requests of a plurality of threads to resources and acquiring characterization information of the threads, wherein the characterization information is used for associating a thread synchronization strategy of a C/C + + library or a reentrant structure strategy of an AOS kernel;
and the access control module is used for controlling the execution of a plurality of threads accessing the same resource according to an access mechanism avoiding concurrence through the thread synchronization strategy and/or the reentry structure strategy based on the characterization information.
A third aspect of the present application provides an electronic device, comprising: a memory and a processor;
the memory for storing a program;
the processor, coupled to the memory, to execute the program to:
responding to access requests of a plurality of threads to resources, and acquiring characterization information of the threads, wherein the characterization information is used for associating a thread synchronization strategy of a C/C + + library or a reentry structure strategy of an AOS kernel;
and controlling a plurality of threads accessing the same resource to execute according to an access mechanism avoiding concurrence through the thread synchronization strategy and/or the reentry structure strategy based on the characterization information.
A fourth aspect of the present application provides a computer-readable storage medium having stored thereon a computer program, the program being executed by a processor to implement the resource access method described above.
In the method, a thread synchronization strategy is added to a C/C + + library and/or a reentry structure strategy is added to an AOS kernel to control a plurality of threads to execute an access mechanism, so that the problem of multi-thread concurrency in the access process is avoided.
Drawings
FIG. 1 is a flow diagram of a resource access method according to one embodiment of the present application;
FIG. 2 is a schematic diagram of an ARM/RISC-V architecture of the present application;
FIG. 3 is a flowchart of a resource access method S200 according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a reentrant structure strategy in an AOS kernel according to the present application;
FIG. 5 is a comparison table before and after memory optimization according to the present application;
FIG. 6 is a block diagram of a resource access device according to an embodiment of the present application;
fig. 7 is a block diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which this application belongs.
In some internet-of-things intelligent devices with complex application scenes, if some WIFI sound box products with dozens of tasks being concurrent exist, the concurrence problem in a C/C + + library is easily triggered. Such as multiple tasks writing into the same file, error code confusion among multiple tasks, local time acquisition confusion, etc.
This is due to the multi-threaded concurrency problem of the underlying C/C + + library. The C/C + + library is included in a tool chain, and simple Internet of things development generally directly uses a native tool chain provided by ARM, which is problematic in multi-thread support and has various multi-thread concurrency problems.
At the beginning of design, the CPU is directly operated through the C/C + + library, so that the C/C + + library is single-threaded and corresponds to the CPU of a single core. In the existing Internet of things architecture, a multi-core and multi-thread Internet of things operating system is added between a C/C + + library and a CPU, and the operating system is in butt joint with the C/C + + library; this results in the C/C + + library often causing multi-threaded concurrency problems due to underlying logic when it is multi-threaded.
In order to solve the above problems, the present application provides a new resource access scheme, which controls multithreading to execute normal resource access by adding a policy for avoiding concurrence in a C/C + + library or an AOS kernel.
For ease of understanding, the following terms that may be used are explained herein:
the operating system of the Internet of things comprises: the method is applicable to the operating system in the field Of Internet Of Things (Internet Of Things).
C, library C: a base library implementing the C language standard and the POSIX standard. There are many implementations, such as Gnu Libc, musl Libc, newlib Libc, etc., where Newlib Libc is a C library commonly used in the field of internet of things.
AliOS Things (AOS): ioT field-oriented and highly-scalable Internet of things operating system.
Tool chains: the development tool set comprises a compiler, an assembler, a linker, a debugger, a disassembler and the like.
The embodiment of the application provides a resource access method, which can be executed by a resource access device, and the resource access device can be integrated in electronic equipment such as a Pad, a computer, a server cluster, a data center and the like. FIG. 1 is a flow chart of a resource access method according to an embodiment of the present application; the resource access method comprises the following steps:
s100, responding to access requests of a plurality of threads to resources, and acquiring characterization information of the threads, wherein the characterization information is used for associating a thread synchronization strategy of a C/C + + library or a reentrant structure strategy of an AOS kernel;
in the application, the access request of the thread to the resource may be that the thread needs to access the corresponding resource when executing the thread, or that a larger-scale task encapsulating the thread is provided with corresponding logic for the thread to access the resource, or other representation modes.
In the present application, the representation information of a thread, that is, the information for determining which policy to execute the thread, is related to the setting logic of the corresponding policy. For example, if all threads accessing the first resource are set to be executed through the first policy, the first resource to be accessed or the identifier of the first resource recorded in the thread is set to be the characterization information of the thread; for example, if all threads are set to be executed by the first policy, the threads themselves are the characterizing information. In the present application, the representation form of the specific representation information of the thread is not limited. In a special case, the token information is not set on the thread, but the encapsulation logic decides to execute the thread using the first policy, and the token information of the first policy is set on the thread.
S200, based on the characterization information, controlling the multiple threads accessing the same resource through the thread synchronization strategy and/or the reentrant structure strategy to execute according to an access mechanism avoiding concurrency.
In the application, the thread synchronization strategy of the C/C + + library is realized by correspondingly adjusting the C/C + + library, and the reentry structure strategy of the AOS kernel is realized by adjusting the AOS kernel. It should be noted that, for a complete C/C + + library, there are many other architectures associated with the C/C + + library, for example, tool chains associated with the C/C + + library, so when adjusting the C/C + + library, according to actual needs, the associated tool chains may also need to be adaptively adjusted to implement/execute a policy corresponding to the C/C + + library, and similarly, the adjustment of AOS has similar relevance. In this application, the rest of the contents that need to be adaptively adjusted will not be described in detail.
In the application, a plurality of threads are controlled to execute an access mechanism by adding a thread synchronization strategy in a C/C + + library and/or adding a reentry structure strategy in an AOS kernel, so that the problem of multi-thread concurrency in an access process is avoided.
In an embodiment, when a plurality of threads have characterization information of the thread synchronization policy associated with a C/C + + library, obtaining an association relationship between the threads and the accessed resources, and controlling the plurality of threads accessing the same resources to execute according to a synchronization mechanism through the thread synchronization policy of the C/C + + library.
In one embodiment, in a case that each of the plurality of threads has characterization information of a reentrant structure policy associated with the AOS kernel, a control block defining a reentrant structure is added to the plurality of threads, and the reentrant structure policy of the AOS kernel controls the plurality of threads to execute according to an access mechanism avoiding concurrency.
In one embodiment, a first part of the threads in the plurality of threads all have characterization information of a reentrant structure policy associated with the AOS kernel, and in a case that the other threads except the first part all have characterization information of the thread synchronization policy associated with the C/C + + library, a control block defining a reentrant structure is added to the threads in the first part, and the threads in the first part are controlled to execute according to an access mechanism avoiding concurrency by the reentrant structure policy of the AOS kernel;
and acquiring the incidence relation between the other threads except the first part and the accessed resources, and controlling the threads accessing the same resources to execute according to a synchronization mechanism through the thread synchronization strategy of the C/C + + library.
In the present application, the accessed resources may be memory resources, data resources, or API resources/function resources in a C/C + + library. The specific form of the resource can be determined according to actual conditions, and the method is not limited in the application.
In the present application, the purpose of accessing resources by the thread is to execute a synchronization mechanism on the thread through a thread synchronization policy of a C/C + + library when a file is opened, read, or written.
It should be noted that, in the present application, the synchronization mechanism does not refer to multi-thread synchronization, and substantially represents that multiple threads can complete access without concurrency, which may specifically include situations of multi-thread synchronization, multi-thread mutual exclusion, and the like.
Thus, when a plurality of threads needing to access resources all need to pass through the thread synchronization policy control of the C/C + + library, a thread synchronization policy execution synchronization mechanism is set; when a plurality of threads needing to access resources all need to be controlled through the reentry structure strategy of the AOS kernel, setting a reentry structure strategy to execute an access mechanism for avoiding concurrency; when one part of the threads need to pass through the thread synchronization strategy of the C/C + + library and the other part of the threads need to pass through the reentry structure strategy control of the AOS kernel, the thread synchronization strategy and the reentry structure strategy are simultaneously set to execute corresponding threads, so that the problem of multithreading concurrency is avoided, and the problem of multithreading concurrency which can be solved is greatly expanded by combining the thread synchronization strategy and the reentry structure strategy.
FIG. 2 is a schematic diagram of the ARM/RISC-V architecture of the present application, in which Pthread, i.e., POSIX Threads, represents a portable operating system interface, so Pthread is a thread implemented under this standard; binutils is a Collection of some binary tools, GCC (GNU Compiler Collection), a programming language interpreter developed by GNU; GDB is a debugging tool under UNIX platform; the LIBC _ STUB component is used for realizing C/C + + library STUB functions (STUBs) and is used for butting the AOS and the C/C + + library; the Newlib is a C runtime base oriented to embedded systems.
In the figure, binutils, GCC, and GDB are common tools used in the development process of the application program, and the specific use process in the application development process is not described herein again. ARM and RISC-V are two common architectures, which are basic hardware, AOS3.3 is an operating system running on the ARM or RISC-V architecture, and Newlib is one of the C libraries, which is used as the basis for the development and execution of applications. When the developed application program is executed, the specific function of the application program is realized by calling the C library, wherein when the C library is called to execute the specific function, the AOS system controls corresponding hardware to realize the specific function; the LIBC _ STUB component is a calling channel of a C library for completing a drive or other functions of the AOS3.3 system, and POSIX is an interface standard by which standard semantics supported by the C library are increased, for example, POSIX can be used for converting a priority parameter in the C library and a parameter of AOS priority.
As can be seen from the figure, a thread synchronization strategy is added in the C/C + + library, so that a multithreading synchronization mechanism is completed.
In one embodiment, the thread synchronization policy is a mutual exclusion lock policy or a semaphore policy, and as shown in fig. 3, the thread synchronization policy that controls access to the same resource through a C/C + + library is executed according to a synchronization mechanism, where the thread synchronization policy includes:
s201, creating a mutex or a semaphore for the resource;
in the present application, the Mutex (Mutex) is a data structure that exhibits a mutual exclusion phenomenon, and can be used as a behavior of synchronous multitasking, and can be used as a resource for protecting a critical section code from an interrupt and sharing synchronous use. The Mutex provides exclusive access to a resource, and the value of the Mutex object has only two values, 0 and 1: the value is 0, the locking state is represented, the current object is locked, and the user thread enters queue waiting if trying to Lock critical resources; the value is 1, which represents the idle state, the current object is idle, the user process/thread can Lock critical resources, and then the Mutex value minus 1 becomes 0.
In the present application, semaphore (Semaphore) is a facility used in a multi-thread environment, which is responsible for coordinating threads to ensure that they can correctly and reasonably use common resources; the semaphore controls access to the shared resource by means of a counter, the value of which is a non-negative integer, which is decremented by one by all threads passing through it. If the counter is greater than 0, access is allowed and the counter is decremented by 1; if 0, access is prohibited and all threads attempting to pass through it will be in a wait state.
S202, based on the mutex, controlling the thread execution threads accessing the same resources to perform mutex through the mutex lock strategy of a C/C + + library;
in this application, the specific implementation manner of the mutex lock policy is not described herein again.
Or, in S203, based on the semaphore, the thread executing thread synchronization accessing the same resource is controlled by the semaphore policy of the C/C + + library.
In this application, the specific implementation of the semaphore policy is not described herein again.
In the method and the device, the thread execution synchronization mechanism accessing the same resource is controlled by setting a mutual exclusion lock strategy or a semaphore strategy, and the problem of multi-thread concurrency is avoided.
In the present application, other manners may also be adopted to control the thread execution synchronization mechanism accessing the same resource, such as a spin lock-based policy, a critical section-based policy, an event object-based policy, and the like.
In one embodiment, the thread records an identifier of a resource needing to be accessed, and a plurality of threads accessing the same resource are determined based on the identifier.
In this application, the identifier may be a pointer pointing to a storage location of the resource, may also be a global variable identifying the resource, and may also be in other presentation forms.
In one embodiment, controlling the thread to execute according to an access mechanism avoiding concurrency through a reentry structure policy of an AOS kernel includes:
a reentrant structure pointer is defined in a control block of the thread, a reentrant structure required by C/C + + library concurrency is separately allocated to each thread based on the control block, and the thread is controlled to execute according to an access mechanism based on the reentrant structure.
Thus, the pointer-element of the reentrant structure of the C/C + + library is defined for each task in the control block, the reentrant structure required by the C/C + + library concurrency is separately allocated for each task,
as shown in fig. 4, a Control Block in the graph is the Control Block of the task, and a reentrant structure pointer Struct _ element is defined in the Control Block; each re-entrant structure pointer may be allocated a re-entrant structure by way of a delayed allocation.
It should be noted that, in the present application, the number of pointers for acquiring the reentrant structure by the C/C + + library is multiple, so that multiple tasks can be really concurrently run in the multi-core architecture and a concurrency problem is avoided.
In one embodiment, the reentrant structure is clipped prior to assigning the reentrant structure separately to a thread.
In this application, the specific cutting method may be: and configuring a macro _ REENT _ SMALL to complete the clipping according to the configuration of the C/C + + library.
By clipping, the reentrant structure is made as small as possible and as sufficient to meet the requirements, thereby reducing the memory occupied by the reentrant structure.
In one embodiment, the pointer of the reentrant structure in the control block of the thread is null, and the reentrant structure is allocated after detecting a calling function for the pointer of the reentrant structure, and the pointer of the reentrant structure is pointed to the allocated reentrant structure.
In the present application, the memory with the reentrant structure is allocated in a delayed manner, so that the memory resource is optimized.
Specifically, the execution process of the reentrant structure policy of the AOS kernel is described with reference to fig. 4: when an AOS kernel creates a task, a task control block of the task is created at the same time; for example, when creating the tasks TaskA and TaskB, the task control blocks TaskA control block and TaskA control block of the tasks TaskA and TaskB are created at the same time; the characteristics of the task control block are recorded in the task control block, and the specific characteristics of the task control block are not limited in this application. A pointer struct _ present of the reentrant structure is contained in the created task control block (task control block ), and the pointer is null; tasks in the C/C + + library run, when a call function (gettree) is executed, the AOS kernel detects whether a pointer (struct _ element) in a task control block (TaskA control block or TaskA control block) is empty or not based on the call, if the pointer (struct _ element) is empty, a corresponding reentrant structure (libc struct _ element in FIG. 4) is allocated, corresponding characteristics are recorded in the reentrant structure, and the characteristics recorded by the reentrant structure are not limited by the application.
The task control blocks and the reentrant structures of the task A and the task B are mutually independent, and on the basis, the multiple tasks cannot generate concurrency problems when being specifically executed; the pointers in the task control blocks can allocate specific allocation of the reentrant structures only when the C/C + + library is called for the first time, and based on the allocation, memory overhead can be optimized remarkably.
It should be noted that, an ISR (Interrupt Service Routines) is also assigned with a reentrant structure at the time of creation, and a difference from a specific process of other tasks is that the reentrant structure assigned by the ISR is a global reentrant structure and no delay assignment is performed.
As shown in fig. 5, it is a comparison table before and after the memory optimization by the present method, and it can be clearly seen from the comparison table that the memory overhead can be significantly optimized by delaying the allocation of the memory.
In one embodiment, the same global reentrant structure _ event is used uniformly in the interrupt context (ISR), so that there is no need to allocate a reentrant structure _ event to each interrupt handling process, and the real-time performance of interrupt handling is better.
In the application, the problem of concurrence of a C/C + + library is solved by customizing an ARM tool chain and combining with thread management of an operating system of the Internet of Things, such as an AliOS Things kernel; by adopting the technical scheme of delaying memory allocation, the memory resource overhead brought by problem solving is reduced.
In the application, the native tool chain of ARM/RISC-V is combined with the AOS. When a tool chain is customized, a Pthread inter-thread synchronization API provided by a POSIX component of a C/C + + library and an AOS (AOS 3.3) is butted, and the concurrency problem caused by the fact that shared resources in the C/C + + library are accessed by a plurality of threads at the same time is solved.
In the application, LIBC, binutils, GCC and a C + + library therein may be reconfigured according to characteristics of the AliOS Things, and the C + + library is also interfaced with Pthread, and supports multithreading characteristics of C + +11 and higher standard C + +17/C + + 20.
In the application, in the field of an operating system of the Internet of things, thread management of a C/C + + library and an operating system kernel in a tool chain is butted and combined; meanwhile, a reentrant structure in a C/C + + library is realized, each thread in an operating system kernel has a separate instance, and all interrupts share one instance; therefore, the concurrence problem of the C/C + + library can be completely solved.
An embodiment of the present application provides a resource access device, which is configured to execute the resource access method described above in the present application, and the resource access device is described in detail below.
As shown in fig. 6, the resource access apparatus includes:
a representation obtaining module 101, configured to obtain, in response to access requests of multiple threads to resources, representation information of the threads, where the representation information is used to associate a thread synchronization policy of a C/C + + library or a reentrant structure policy of an AOS kernel;
an access control module 102, configured to control, based on the characterization information, multiple threads accessing the same resource to execute according to an access mechanism that avoids concurrence through the thread synchronization policy and/or the reentry structure policy.
In one embodiment, the access control module 102 is further configured to:
and under the condition that the plurality of threads have the characterization information of the thread synchronization strategy associated with the C/C + + library, acquiring the association relation between the threads and the accessed resources, and controlling the plurality of threads accessing the same resources to execute according to a synchronization mechanism through the thread synchronization strategy of the C/C + + library.
In one embodiment, the access control module 102 is further configured to:
and under the condition that the threads all have the characterization information of the reentrant structure strategy associated with the AOS kernel, adding a control block for defining a reentrant structure on the threads, and controlling the threads to execute according to an access mechanism for avoiding concurrence through the reentrant structure strategy of the AOS kernel.
In one embodiment, the access control module 102 is further configured to:
under the condition that all threads of a first part of the threads have the characterization information of the reentrant structure strategy associated with the AOS kernel, and the other threads except the first part have the characterization information of the thread synchronization strategy associated with the C/C + + library, adding a control block for defining a reentrant structure on the threads of the first part, and controlling the threads of the first part to execute according to an access mechanism for avoiding concurrency through the reentrant structure strategy of the AOS kernel; and acquiring the incidence relation between the other threads except the first part and the accessed resources, and controlling the threads accessing the same resources to execute according to a synchronization mechanism through the thread synchronization strategy of the C/C + + library.
In one embodiment, the thread synchronization policy is a mutex lock policy or a semaphore policy, and the access control module 102 is further configured to:
creating mutexes or semaphores for the resources; based on the mutex, controlling the threads accessing the same resource to execute the mutex through the mutex lock strategy of a C/C + + library; or, based on the semaphore, the thread execution thread synchronization accessing the same resource is controlled by the semaphore policy of the C/C + + library.
In one embodiment, the thread records an identifier of a resource needing to be accessed, and a plurality of threads accessing the same resource are determined based on the identifier.
In one embodiment, the access control module 102 is further configured to:
a reentrant structure pointer is defined in the control block of the thread, a reentrant structure required by C/C + + library concurrency is independently allocated to each thread based on the control block, and the thread is controlled to execute according to an access mechanism based on the reentrant structure.
In one embodiment, the access control module 102 is further configured to:
clipping the reentrant structure before individually allocating the reentrant structure for a thread.
In one embodiment, the access control module 102 is further configured to:
and the pointer of the reentrant structure in the control block of the thread is null, the reentrant structure is allocated after detecting the calling function of the pointer of the reentrant structure, and the pointer of the reentrant structure points to the allocated reentrant structure.
The resource access device provided by the above embodiment of the present application and the resource access method provided by the embodiment of the present application have the same inventive concept and have the same beneficial effects as the method adopted, operated or implemented by the application program stored in the resource access device.
Having described the internal functions and structure of the resource access device, as shown in fig. 7, in practice, the resource access device may be implemented as an electronic device, including: a memory 301 and a processor 303.
A memory 301, which may be configured to store a program.
In addition, the memory 301 may also be configured to store various other data to support operations on the electronic device. Examples of such data include instructions for any application or method operating on the electronic device, contact data, phonebook data, messages, pictures, videos, and so forth.
The memory 301 may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
A processor 303, coupled to the memory 301, for executing programs in the memory 301 for:
responding to access requests of a plurality of threads to resources, and acquiring characterization information of the threads, wherein the characterization information is used for associating a thread synchronization strategy of a C/C + + library or a reentry structure strategy of an AOS kernel;
and controlling a plurality of threads accessing the same resource to execute according to an access mechanism avoiding concurrence through the thread synchronization strategy and/or the reentry structure strategy based on the characterization information.
In one embodiment, the processor 303 is specifically configured to:
and under the condition that the multiple threads have the characterization information of the thread synchronization strategy associated with the C/C + + library, acquiring the association relation between the threads and the accessed resources, and controlling the multiple threads accessing the same resources to execute according to a synchronization mechanism through the thread synchronization strategy of the C/C + + library.
In one embodiment, the processor 303 is specifically configured to:
and under the condition that the threads all have the characterization information of the reentrant structure strategy associated with the AOS kernel, adding a control block for defining a reentrant structure on the threads, and controlling the threads to execute according to an access mechanism avoiding concurrency through the reentrant structure strategy of the AOS kernel.
In one embodiment, the processor 303 is specifically configured to:
under the condition that all threads of a first part of the threads have the characterization information of the reentrant structure strategy associated with the AOS kernel, and the other threads except the first part have the characterization information of the thread synchronization strategy associated with the C/C + + library, adding a control block for defining a reentrant structure on the threads of the first part, and controlling the threads of the first part to execute according to an access mechanism for avoiding concurrency through the reentrant structure strategy of the AOS kernel; and acquiring the incidence relation between the other threads except the first part and the accessed resources, and controlling the threads accessing the same resources to execute according to a synchronization mechanism through the thread synchronization strategy of the C/C + + library.
In one embodiment, the thread synchronization policy is a mutual exclusion lock policy or a semaphore policy, and the processor 303 is specifically configured to:
creating mutexes or semaphores for the resources; based on the mutex, controlling the threads accessing the same resource to execute the thread mutex through the mutex lock strategy of a C/C + + library; or, based on the semaphore, the thread execution thread synchronization accessing the same resource is controlled by the semaphore policy of the C/C + + library.
In one embodiment, the thread records an identifier of a resource needing to be accessed, and a plurality of threads accessing the same resource are determined based on the identifier.
In one embodiment, the processor 303 is specifically configured to:
a reentrant structure pointer is defined in a control block of the thread, a reentrant structure required by C/C + + library concurrency is separately allocated to each thread based on the control block, and the thread is controlled to execute according to an access mechanism based on the reentrant structure.
In one embodiment, the processor 303 is specifically configured to:
clipping the reentrant structure before individually allocating the reentrant structure for a thread.
In one embodiment, the processor 303 is specifically configured to:
and after detecting a calling function of the pointer of the reentrant structure, allocating the reentrant structure and pointing the pointer of the reentrant structure to the allocated reentrant structure.
In this application, only some of the components are schematically shown in fig. 7, and it is not meant that the electronic device includes only the components shown in fig. 7.
The electronic device provided by the embodiment of the present invention has the same advantages as the method for accessing a resource, which is adopted, operated or implemented by the application program stored in the electronic device, based on the same inventive concept.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or FLASH memory (FLASH RAM). Memory is an example of a computer-readable medium.
The present application further provides a computer-readable storage medium corresponding to the resource access method provided in the foregoing embodiment, and a computer program (i.e., a program product) is stored thereon, and when being executed by a processor, the computer program will execute the resource access method provided in any of the foregoing embodiments.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable Media does not include Transitory computer readable Media such as modulated data signals and carrier waves.
The computer-readable storage medium provided by the above embodiment of the present application and the resource access method provided by the embodiment of the present application have the same advantages as the method adopted, run or implemented by the application program stored in the computer-readable storage medium.
It should be noted that in the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus comprising the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (12)
1. A method for accessing resources, comprising:
responding to access requests of a plurality of threads to resources, and acquiring characterization information of the threads, wherein the characterization information is used for associating a thread synchronization strategy of a C/C + + library or a reentry structure strategy of an AOS kernel;
and controlling a plurality of threads accessing the same resource to execute according to an access mechanism avoiding concurrence through the thread synchronization strategy and/or the reentry structure strategy based on the characterization information.
2. The method according to claim 1, wherein in a case that each of the plurality of threads has the characterization information of the thread synchronization policy associated with the C/C + + library, obtaining an association relationship between the thread and the accessed resource, and controlling the plurality of threads accessing the same resource to execute according to a synchronization mechanism through the thread synchronization policy of the C/C + + library.
3. The method according to claim 1, wherein in case that a plurality of said threads each have characterization information associated with a reentrant structure policy of the AOS kernel, adding a control block defining a reentrant structure to the plurality of said threads, and controlling the plurality of said threads to execute according to an access mechanism avoiding concurrence through the reentrant structure policy of the AOS kernel.
4. The method according to claim 1, wherein a first part of said threads in a plurality of said threads all have characterization information of reentrant structure policy associated with AOS kernel, and in case that the other threads except the first part all have characterization information of said thread synchronization policy associated with C/C + + library, adding a control block defining reentrant structure on said threads in the first part, and controlling the threads in the first part to execute according to access mechanism avoiding concurrency through reentrant structure policy of AOS kernel;
and acquiring the incidence relation between the other threads except the first part and the accessed resources, and controlling the threads accessing the same resources to execute according to a synchronization mechanism through the thread synchronization strategy of the C/C + + library.
5. The method according to claim 2 or 4, wherein the thread synchronization policy is a mutual exclusion lock policy or a semaphore policy, and the thread synchronization policy through a C/C + + library controls the threads accessing the same resource to execute according to a synchronization mechanism, including:
creating a mutex or semaphore for the resource;
based on the mutex, controlling the threads accessing the same resource to execute the mutex through the mutex lock strategy of a C/C + + library;
or controlling the thread execution thread synchronization accessing the same resource through the semaphore policy of a C/C + + library based on the semaphore.
6. The method of claim 1, wherein an identification of a resource to be accessed is recorded on the thread, and wherein a plurality of threads accessing the same resource are determined based on the identification.
7. The method according to claim 3 or 4, wherein controlling the thread to execute according to the access mechanism avoiding concurrency through the reentry structure policy of the AOS kernel comprises:
a reentrant structure pointer is defined in a control block of the thread, a reentrant structure required by C/C + + library concurrency is separately allocated to each thread based on the control block, and the thread is controlled to execute according to an access mechanism based on the reentrant structure.
8. The method of claim 7, wherein the reentrant structure is clipped prior to separately allocating the reentrant structure for a thread.
9. The method of claim 7, wherein the reentrant structure pointer in the control block of the thread is null, wherein the reentrant structure is allocated after detecting a function call to the reentrant structure pointer, and wherein the reentrant structure pointer is pointed to the allocated reentrant structure.
10. A resource access apparatus, comprising:
the characterization acquisition module is used for responding to access requests of a plurality of threads to resources and acquiring characterization information of the threads, wherein the characterization information is used for associating a thread synchronization strategy of a C/C + + library or a reentrant structure strategy of an AOS kernel;
and the access control module is used for controlling the execution of a plurality of threads accessing the same resource according to an access mechanism avoiding concurrence through the thread synchronization strategy and/or the reentry structure strategy based on the characterization information.
11. An electronic device, comprising: a memory and a processor;
the memory for storing a program;
the processor, coupled to the memory, to execute the program to:
responding to access requests of a plurality of threads to resources, and acquiring characterization information of the threads, wherein the characterization information is used for associating a thread synchronization strategy of a C/C + + library or a reentry structure strategy of an AOS kernel;
and controlling a plurality of threads accessing the same resource to execute according to an access mechanism avoiding concurrence through the thread synchronization strategy and/or the reentry structure strategy based on the characterization information.
12. A computer-readable storage medium, on which a computer program is stored, characterized in that the program is executed by a processor to implement the method of any of claims 1-9.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4525780A (en) * | 1981-05-22 | 1985-06-25 | Data General Corporation | Data processing system having a memory using object-based information and a protection scheme for determining access rights to such information |
| CN106325980A (en) * | 2015-06-30 | 2017-01-11 | 中国石油化工股份有限公司 | Multi-thread concurrent system |
| CN108647087A (en) * | 2018-05-17 | 2018-10-12 | 腾讯科技（深圳）有限公司 | Realize the reentrant method, apparatus of PHP kernels, server and storage medium |
| CN109165516A (en) * | 2018-08-14 | 2019-01-08 | 中国银联股份有限公司 | A kind of access control method and device |
| CN111582562A (en) * | 2020-04-20 | 2020-08-25 | 杭州意能电力技术有限公司 | Neural network prediction control method based on optimization control platform |
| WO2021155529A1 (en) * | 2020-02-06 | 2021-08-12 | Oppo广东移动通信有限公司 | Resource deletion method, apparatus, and device, and storage medium |
| WO2021210527A1 (en) * | 2020-04-13 | 2021-10-21 | ＬｅａｐＭｉｎｄ株式会社 | Method for controlling neural network circuit |
| CN113538207A (en) * | 2021-09-17 | 2021-10-22 | 北京鲸鲮信息系统技术有限公司 | Cross-process calling graphics rendering method and device, electronic equipment and storage medium |
| CN113806031A (en) * | 2020-09-28 | 2021-12-17 | 京东科技控股股份有限公司 | Method and apparatus for securing resources through object locks |
| CN114356591A (en) * | 2020-10-14 | 2022-04-15 | 阿里巴巴集团控股有限公司 | Inter-process communication method and device, Internet of things operating system and Internet of things equipment |
| CN114756355A (en) * | 2022-06-14 | 2022-07-15 | 之江实验室 | Method and device for automatically and quickly recovering process of computer operating system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9141439B2 (en) * | 2010-10-11 | 2015-09-22 | Sap Se | System and method for reporting a synchronization event in a runtime system of a computer system |
| US9424092B2 (en) * | 2014-09-26 | 2016-08-23 | Microsoft Technology Licensing, Llc | Heterogeneous thread scheduling |
| US10901920B2 (en) * | 2018-06-03 | 2021-01-26 | Apple Inc. | Turnstile API for runtime priority boosting |
| CN109271258B (en) * | 2018-08-28 | 2020-11-17 | 百度在线网络技术（北京）有限公司 | Method, device, terminal and storage medium for realizing re-entry of read-write lock |
-
2022
- 2022-08-08 CN CN202210944519.XA patent/CN115016948B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4525780A (en) * | 1981-05-22 | 1985-06-25 | Data General Corporation | Data processing system having a memory using object-based information and a protection scheme for determining access rights to such information |
| CN106325980A (en) * | 2015-06-30 | 2017-01-11 | 中国石油化工股份有限公司 | Multi-thread concurrent system |
| CN108647087A (en) * | 2018-05-17 | 2018-10-12 | 腾讯科技（深圳）有限公司 | Realize the reentrant method, apparatus of PHP kernels, server and storage medium |
| CN109165516A (en) * | 2018-08-14 | 2019-01-08 | 中国银联股份有限公司 | A kind of access control method and device |
| WO2021155529A1 (en) * | 2020-02-06 | 2021-08-12 | Oppo广东移动通信有限公司 | Resource deletion method, apparatus, and device, and storage medium |
| WO2021210527A1 (en) * | 2020-04-13 | 2021-10-21 | ＬｅａｐＭｉｎｄ株式会社 | Method for controlling neural network circuit |
| CN111582562A (en) * | 2020-04-20 | 2020-08-25 | 杭州意能电力技术有限公司 | Neural network prediction control method based on optimization control platform |
| CN113806031A (en) * | 2020-09-28 | 2021-12-17 | 京东科技控股股份有限公司 | Method and apparatus for securing resources through object locks |
| CN114356591A (en) * | 2020-10-14 | 2022-04-15 | 阿里巴巴集团控股有限公司 | Inter-process communication method and device, Internet of things operating system and Internet of things equipment |
| CN113538207A (en) * | 2021-09-17 | 2021-10-22 | 北京鲸鲮信息系统技术有限公司 | Cross-process calling graphics rendering method and device, electronic equipment and storage medium |
| CN114756355A (en) * | 2022-06-14 | 2022-07-15 | 之江实验室 | Method and device for automatically and quickly recovering process of computer operating system |
Non-Patent Citations (4)
| Title |
|---|
| A new construction method of common embedded cross compiler tool based on newlib;Yang Yu ET AL;《2010 IEEE International Conference on Intelligent Computing and Intelligent Systems》;20101206;全文 * |
| Newlib的研究与最小实现;张宇旻等;《电子科技大学学报》;20050831(第04期);526页 * |
| 基于国产处理器的软件化雷达中间件设计;门浩;《中国知网硕士学位论文全文数据库》;20220415;第2022年卷(第4期);全文 * |
| 多线程技术;李新明等;《小型微型计算机系统》;19980208(第02期);全文 * |
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