CN115016825A

CN115016825A - Method and device for upgrading firmware of field programmable gate array and computer equipment

Info

Publication number: CN115016825A
Application number: CN202210761053.XA
Authority: CN
Inventors: 朱帅帅; 殷树根; 吴海洋
Original assignee: Suzhou HYC Technology Co Ltd
Current assignee: Suzhou HYC Technology Co Ltd
Priority date: 2022-06-30
Filing date: 2022-06-30
Publication date: 2022-09-06

Abstract

The present disclosure relates to a field programmable gate array firmware upgrade method, apparatus, computer device, storage medium and computer program product. The method comprises the following steps: acquiring mapping information of a flash memory pin of a field programmable gate array; configuring the field programmable gate array according to the flash memory pin mapping information to obtain a configured field programmable gate array; acquiring firmware information to be updated of the field programmable gate array; controlling the configured field programmable gate array to update the running program stored in the flash memory according to the firmware information to be updated to obtain an updated running program; and guiding the configured field programmable gate array to restart according to the updated running program to finish firmware upgrading. Compared with the prior art, the method has the advantages that a JTAG interface is not needed, factory return and equipment disassembly are not needed, and convenience and rapidness are achieved.

Description

Method and device for upgrading firmware of field programmable gate array and computer equipment

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a method and an apparatus for upgrading firmware of a field programmable gate array, and a computer device.

Background

With the development of computer technology, Field Programmable Gate Array technology (Field Programmable Gate Array is called "Field Programmable Gate Array" for short) appears. Due to the technical technology of the FPGA, a stored program is lost after power failure, so that a configuration Flash (Flash represents a storage chip, and the data in the storage chip can be modified by a specific program) for storing the program needs to be mounted on the FPGA, the FPGA reads the data from the Flash after being powered on to configure the Ram in the FPGA, and the program runs in the FPGA again. For configuration of Flash, JTAG (Joint Test Action Group, which is an english abbreviation of Joint Test task Group) provided by a manufacturer is usually used to write configuration data into Flash, which is very convenient for debugging and program curing before delivery, but a JTAG interface is usually not reserved after product packaging and delivery. If the firmware of the FPGA needs to be upgraded, the equipment needs to be returned to a factory or disassembled and then the firmware is programmed.

In the conventional technology, an FPGA firmware upgrading program is generally written by using an HDL (HDL is a name of a Hardware Description Language, and english is called as Hardware Description Language), and it is complicated to use the HDL writing program to operate and control serial devices such as Flash, and a large number of state machines need to be written to implement command and data transmission of functions such as erasing, reading and writing of Flash devices. In addition, during debugging, due to the large data volume, it is very difficult to search for errors by using Vivado (Vivado is a name of an integrated design environment) simulator data acquisition, and complicated error detection HDL codes need to be written, so that a large amount of development time is consumed, and the development process is limited.

Disclosure of Invention

In view of the above, it is desirable to provide a field programmable gate array firmware upgrading method, apparatus, computer device, computer readable storage medium and computer program product, which can remotely upgrade firmware without JTAG interface.

In a first aspect, the present disclosure provides a method for upgrading firmware of a field programmable gate array. The method comprises the following steps:

acquiring mapping information of a flash memory pin of a field programmable gate array;

configuring the field programmable gate array according to the flash memory pin mapping information to obtain a configured field programmable gate array;

acquiring firmware information to be updated of the field programmable gate array;

controlling the configured field programmable gate array to update the running program stored in the flash memory according to the firmware information to be updated to obtain an updated running program;

and guiding the configured field programmable gate array to restart according to the updated running program to finish firmware upgrading.

In one embodiment, the configuring the field programmable gate array according to the flash memory pin mapping information to obtain a configured field programmable gate array includes:

establishing an adjustment mapping relation between the processor and the flash memory according to the flash memory pin mapping information;

and controlling the processor to perform online configuration on the field programmable gate array according to the adjustment mapping relation between the processor and the flash memory to obtain the configured field programmable gate array.

In one embodiment, the processor includes a single chip, and the establishing of the adjusted mapping relationship between the processor and the flash memory according to the pin mapping information includes: and establishing a binary netlist containing an adjustment mapping relation between the single chip microcomputer and the flash memory, wherein the binary netlist comprises a bin file and a bit file.

In one embodiment, after the obtaining the configured field programmable gate array, the method further includes:

starting a pin of the configured field programmable gate array;

carrying out command interaction with the field programmable gate array, and determining whether the configured field programmable gate array is successfully configured;

and when the configuration of the field programmable gate array fails after the configuration, the field programmable gate array is reconfigured according to the pin mapping information.

In one embodiment, after the booting the post-configuration field programmable gate array is restarted according to the updated running program, the method further includes:

performing command interaction with the configured field programmable gate array to determine whether the firmware of the configured field programmable gate array is successfully upgraded;

and when the firmware of the configured field programmable gate array fails to be upgraded, the configured field programmable gate array is controlled again to update the running program stored in the flash memory.

In one embodiment, before directing the post-configuration field programmable gate array to restart according to the updated running program, the method further includes:

comparing and checking the updated running program in the flash memory with the firmware information to be updated, and determining a checking result;

and when the verification result is failed, the configured field programmable gate array is controlled again to update the running program stored in the flash memory.

In a second aspect, the present disclosure further provides a field programmable gate array firmware upgrading apparatus. The device comprises:

the pin information acquisition module is used for acquiring flash memory pin mapping information of the field programmable gate array;

the configuration module is used for configuring the field programmable gate array according to the flash memory pin mapping information to obtain a configured field programmable gate array;

the updating information acquisition module is used for acquiring the information of the firmware to be updated of the field programmable gate array;

the pin information updating module is used for controlling the configured field programmable gate array to update the running program stored in the flash memory according to the firmware information to be updated to obtain an updated running program;

and the firmware upgrading module is used for guiding the configured field programmable gate array to restart according to the updated running program to finish firmware upgrading.

In a third aspect, the present disclosure also provides a computer device. The computer device comprises a memory storing a computer program and a processor implementing the following steps when executing the computer program:

In a fourth aspect, the present disclosure also provides a computer-readable storage medium. The computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of:

In a fifth aspect, the present disclosure also provides a computer program product. The computer program product comprising a computer program which when executed by a processor performs the steps of:

According to the field programmable gate array firmware upgrading method, the field programmable gate array firmware upgrading device, the computer equipment, the storage medium and the computer program product, the field programmable gate array is configured, so that the external equipment can indirectly update the corresponding flash memory through the field programmable gate array, and after the running program of the field programmable gate array stored in the flash memory is modified, the field programmable gate array is guided to restart, and the firmware upgrading of the field programmable gate array can be realized. The beneficial effect of remote upgrading of the field programmable gate array firmware can be realized, compared with the prior art, the JTAG interface is not needed, factory return and equipment disassembly are not needed, and convenience and rapidness are realized.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure and are not to be construed as limiting the disclosure.

FIG. 1 is a diagram of an embodiment of an application environment of a method for upgrading firmware of a field programmable gate array;

FIG. 2 is a flowchart illustrating a method for upgrading firmware of a field programmable gate array according to an embodiment;

FIG. 3 is a flowchart illustrating a firmware upgrading method for a field programmable gate array according to another embodiment;

FIG. 4 is a flowchart illustrating a firmware upgrading method for a field programmable gate array according to another embodiment;

FIG. 5 is a block diagram of an apparatus for firmware upgrade of a field programmable gate array according to an embodiment;

FIG. 6 is a diagram illustrating an internal structure of a computer device according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the disclosure and are not intended to limit the disclosure.

It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the foregoing drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are capable of operation in sequences other than those illustrated or otherwise described herein. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The field programmable gate array firmware upgrading method provided by the embodiment of the disclosure can be applied to the application environment shown in fig. 1. It should be noted that the application environment in fig. 1 is only an example of an application environment of the present disclosure, and does not limit the application environment. The upper computer 102 (in the figure, the upper computer is a personal computer, and is represented by a PC), and the upper computer 102 may communicate with the field programmable gate array 104 in a wired or wireless manner, for example, perform command interaction. The fpga 104 may be connected to the flash memory 106 through an Interface, such as an SPI Interface (SPI is an english abbreviation of a Serial Peripheral Interface, and is entirely called a Serial Peripheral Interface), and a QSPI Interface (QSPI is an english abbreviation of a queue Serial Peripheral Interface, and is entirely called a Quad Serial Peripheral Interface). The processor 108 (in the figure, the processor is a single chip microcomputer and indicated by an MCU) and the upper computer 102 can also communicate in a wired or wireless manner. The processor 108 is also connected to an external mass storage 110, either wirelessly or by wire. The external mass storage 110 may store data to be processed, and the capacity of the external mass storage 110 may be determined according to actual use requirements, which is not limited in this disclosure. The fpga 104, the flash memory 106, the processor 108, and the external mass storage 110 may form a unified device that is connected to the host computer 102 as a whole. The external mass storage 110 may be integrated on a server or may be placed on the cloud or other network server. The external mass storage 110 may not necessarily be present according to actual use needs. When the firmware is upgraded, the upper computer 102 acquires the flash memory pin mapping information of the field programmable gate array. And the upper computer 102 directly or indirectly configures the field programmable gate array according to the flash memory pin mapping information to obtain the configured field programmable gate array. The upper computer 102 and the processor 108 can obtain the information of the firmware to be updated of the field programmable gate array. The processor 108 controls the field programmable gate array 104 to update the running program stored in the flash memory 106 according to the firmware information to be updated, so as to obtain an updated running program. The upper computer 102 can directly or indirectly guide the field programmable gate array 104 to restart according to the updated running program, and the firmware upgrade is completed. The upper computer 102 may be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, internet of things devices and portable wearable devices, and the internet of things devices may be smart speakers, smart televisions, smart air conditioners, smart vehicle-mounted devices, and the like. The portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, and the like. The external mass storage 110 may be an eMMC (eMMC is an english abbreviation of Embedded multimedia controller, and is generally called Embedded Multi Media Card), a flash memory, an SD Card, etc. (an SD memory Card is a memory device based on a semiconductor flash memory).

In one embodiment, as shown in fig. 2, a method for upgrading firmware of a field programmable gate array is provided, which is described by taking the application environment in fig. 1 as an example, and includes the following steps:

step 202, obtaining the mapping information of the flash memory pin of the field programmable gate array.

The flash memory of the field programmable gate array may refer to an external mount memory of the field programmable gate array. The flash memory pin mapping information may refer to pin information of the flash memory that may be used to establish a pin mapping relationship with an external device.

Specifically, the Field Programmable Gate Array is called Field Programmable Gate Array (FPGA) by its english name. The Flash memory is generally a Flash chip, and can also be other configuration chips. The flash memory pin mapping information may include pin setting information of the flash memory, and may also include pin mapping information between the flash memory and the field programmable gate array. The modification of the data stored in the flash memory can be realized by utilizing the mapping information of the flash memory pins.

And 204, configuring the field programmable gate array according to the flash memory pin mapping information to obtain the configured field programmable gate array.

Specifically, a bin file (a bin file is a configuration file without header information) containing the flash pin mapping information may be established according to the flash pin mapping information, and the bin file is configured into the field programmable gate array in a serial or parallel manner, so as to configure the field programmable gate array, and obtain the configured field programmable gate array. After configuration, the field programmable gate array can modify the program stored in the corresponding flash memory under the control of the external device.

And step 206, acquiring the firmware information to be updated of the field programmable gate array.

The firmware information to be updated may refer to an update requirement for firmware of the field programmable gate array.

Specifically, the firmware of the logic blocks, interconnection switches, etc. of the field programmable gate array can be re-edited. When the field programmable gate array needs to be upgraded, the information of the firmware to be updated of the field programmable gate array is obtained, so that the firmware of the field programmable gate array needs to be re-edited and the requirement of re-editing is determined.

And 208, controlling the configured field programmable gate array to update the running program stored in the flash memory according to the firmware information to be updated, so as to obtain the updated running program.

The running program may refer to a running program of the field programmable gate array.

Specifically, the operating program of the field programmable gate array is stored in the corresponding flash memory, and the firmware of the field programmable gate array needs to be updated when the firmware of the field programmable gate array is upgraded. And controlling the configured field programmable gate array to update the running program stored in the flash memory according to the firmware information to be updated, so as to obtain the updated running program. Specifically, the firmware information to be updated may be processed into a bit file (a bit file is a configuration file with header information), and then the bit file is burned to a corresponding position of the flash memory through the SPI interface or the QSPI interface. Because the flash memory is updated through the configured field programmable gate array, in the updating process, the external equipment does not need to establish physical connection with the flash memory, an analog switch is not needed, and the downloading speed is not limited by the analog switch.

And step 210, guiding the configured field programmable gate array to restart according to the updated running program, and finishing firmware upgrade.

Specifically, the processor may direct the configured field programmable gate array to restart according to the updated running program through a start pin control, for example, direct the configured field programmable gate array to restart from the flash memory. After the configured field programmable gate array is restarted from the flash memory successfully, the firmware upgrade of the field programmable gate array is completed.

In the field programmable gate array firmware upgrading method, the field programmable gate array is configured, so that the external equipment can indirectly update the corresponding flash memory through the field programmable gate array, and the field programmable gate array is guided to restart after the running program of the field programmable gate array stored in the flash memory is modified, so that the firmware upgrading of the field programmable gate array can be realized. Compared with the prior art, the remote upgrading method has the advantages that the remote upgrading of the firmware of the field programmable gate array can be realized, a JTAG interface is not needed, factory return and equipment disassembly are not needed, and the remote upgrading method is convenient and fast.

In an embodiment, the configuring the field programmable gate array according to the flash pin mapping information to obtain a configured field programmable gate array includes:

and controlling a processor to perform online configuration on the field programmable gate array according to the adjustment mapping relation between the processor and the flash memory to obtain the configured field programmable gate array.

Specifically, the processor may be a processor that controls a field programmable gate array to perform firmware upgrade, and may be, for example, a single chip microcomputer, a GPU (GPU is an english abbreviation of a graphics processor, and english is collectively called a graphics processing unit), and the like. The processor can exist as a lower computer, and the software of the computer end can exist as an upper computer of the processor. According to the mapping information of the flash memory pins, the mapping relation between the pins of the processor and the pins of the flash memory can be established, and preconditions are provided for updating the flash memory of the processor. According to the adjusted mapping relationship between the processor and the flash memory, the processor can be controlled to perform online configuration on the field programmable gate array, for example, the processor can be controlled online to burn a corresponding file into the field programmable gate array, so as to obtain the configured field programmable gate array.

In this embodiment, the corresponding relationship between the processor pin and the flash memory pin is established by establishing the adjustment mapping relationship, and since the processor is connected with the flash memory through the field programmable gate array, the field programmable gate array is configured on line according to the adjustment mapping relationship, so that the processor can indirectly modify the storage content of the flash memory through the field programmable gate array, and the beneficial effect that the processor can remotely control the flash memory of the field programmable gate array can be achieved, thereby realizing the remote online upgrade of the field programmable gate array.

In one embodiment, the processor includes a single chip, and the establishing of the adjustment mapping relationship between the processor and the flash memory according to the pin mapping information includes: and establishing a binary netlist containing an adjustment mapping relation between the single chip microcomputer and the flash memory, wherein the binary netlist comprises a bin file and a bit file.

Specifically, the single chip microcomputer is also called a micro control Unit (the micro control Unit is abbreviated as MCU, and is called Microcontroller Unit in english). And establishing a binary netlist containing an adjustment mapping relation between the single chip microcomputer and the flash memory according to the pin mapping information, so that the adjustment mapping relation is expressed in the form of the binary netlist. The binary netlist comprises a bin file and a bit file, wherein the bin file can be used for configuring a field programmable gate array, and the bit file can be used for updating a flash memory.

In this embodiment, the remote firmware upgrade of the field programmable gate array is performed by using the single chip microcomputer. The firmware upgrading code is compiled based on the single chip microcomputer, the single chip microcomputer is used for program development by using C language or C + + language, debugging is more convenient, development time is shortened, development processes are widened, a JTAG interface is not needed in the upgrading process, the upgrading process can be carried out on site, equipment does not need to be returned to a factory and disassembled, the risk of firmware upgrading failure does not exist, the upgrading success rate can reach 100%, and the method is very simple and convenient. The corresponding bin file and bit file can facilitate the configuration of the field programmable gate array and the updating of the flash memory, and can improve the speed of the remote firmware upgrading.

In one embodiment, as shown in fig. 3, after the obtaining the configured field programmable gate array, the method further includes:

and S302, starting the configured pins of the field programmable gate array.

S304, carrying out command interaction with the field programmable gate array, and determining whether the configured field programmable gate array is successfully configured.

S306, when the configuration of the field programmable gate array fails after the configuration, the field programmable gate array is reconfigured according to the pin mapping information.

Specifically, after the configured field programmable gate array is obtained, whether the configuration is successful or not may be verified. The pins of the configured field programmable gate array can be started, and then command interaction is carried out by using an upper computer and the field programmable gate array, so that whether the configured field programmable gate array is successfully configured or not is determined. And when the configured field programmable gate array fails to be configured, reconfiguring the field programmable gate array according to the pin mapping information until the successfully configured field programmable gate array is obtained.

In the embodiment, whether the configuration of the field programmable gate array is successful or not is verified after the configuration, and the field programmable gate array is reconfigured when the configuration is failed, so that the beneficial effect of ensuring the successful configuration of the field programmable gate array can be achieved.

In one embodiment, after the directing the post-configuration field programmable gate array to restart according to the updated running program, the method further comprises:

Specifically, after the configuration is booted and the field programmable gate array is restarted according to the updated running program, whether the firmware is upgraded successfully or not can be verified. After the configured field programmable gate array is started, the upper computer can perform command interaction with the configured field programmable gate array to determine whether the firmware of the configured field programmable gate array is upgraded successfully. And when the upgrading fails, the configured field programmable gate array is controlled again to update the running program stored in the flash memory until the firmware is upgraded successfully.

In the embodiment, whether the firmware of the field programmable gate array is successfully upgraded is verified through command interaction, and when the upgrading is found to be failed, the running program in the corresponding flash memory is updated again, so that the beneficial effect of ensuring that the field programmable gate array successfully upgrades the firmware can be achieved.

In one embodiment, before directing the post-configuration field programmable gate array to restart according to the updated running program, the method further comprises:

and when the verification result is that the operation program is failed, the configured field programmable gate array is controlled again to update the operation program stored in the flash memory.

Specifically, before the field programmable gate array is restarted after the configuration, it may be checked whether the running program stored in the flash memory is successfully updated. The upper computer can compare and verify the updated running program in the flash memory with the firmware information to be updated, and determine a verification result. And when the updated running program is consistent with the information of the firmware to be updated, the verification is passed, otherwise, the verification is not passed. And when the verification result is that the operation program stored in the flash memory is failed, the configured field programmable gate array is controlled again to update the operation program stored in the flash memory until the operation program stored in the flash memory is updated successfully.

In the embodiment, whether the running program stored in the flash memory is successfully updated or not is verified, and the running program is updated again when the verification fails, so that the failed update can be corrected in time, the beneficial effect of ensuring that the running program stored in the flash memory is successfully updated can be achieved, and the successful upgrade of the field programmable gate array firmware can be ensured.

In one embodiment, as shown in fig. 4, after the firmware upgrade procedure entering the fpga is started, program initialization is performed to prepare for firmware upgrade. And then judging whether a trigger firmware upgrading flow exists or not, if not, returning to the judging flow, and if so, controlling the single chip microcomputer to configure the bin file into the field programmable gate array in a serial port mode through the file system. And after the configuration is completed, the field programmable gate array is started. And then the upper computer and the field programmable gate array carry out command interaction to confirm whether the field programmable gate array is successfully configured, if not, the field programmable gate array is reconfigured, and if so, the single chip microcomputer is controlled to configure the bit file into a corresponding address of the flash memory through the SPI interface or the QSPI interface by the file system. And then configuring a starting pin of the field programmable gate array to start from the flash memory. And finally, the upper computer carries out command interaction with the field programmable gate array again to confirm whether the firmware is upgraded successfully or not, if not, the bit file is reconfigured, if yes, the updating is successful, the field programmable gate array is started, and the flow returns a command to the upper computer.

In one embodiment, the single chip includes a SERIAL _ DATA pin and a CLOCK pin, and the field programmable gate array includes a DIN pin and a CCLK pin (SERIAL _ DATA, CLOCK, DIN, and CCLK are names of the pins). The SERIAL _ DATA pin is coupled to the DIN pin and the CLOCK pin is coupled to the CCLK pin.

It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.

Based on the same inventive concept, the embodiment of the present disclosure further provides a field programmable gate array firmware upgrading device for implementing the field programmable gate array firmware upgrading method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the method, so the specific limitations in one or more embodiments of the field programmable gate array firmware upgrading device provided below can refer to the limitations on the field programmable gate array firmware upgrading method in the foregoing, and details are not described here.

Based on the description of the above field programmable gate array firmware upgrading method embodiment, the present disclosure also provides a field programmable gate array firmware upgrading device. The apparatus may include systems (including distributed systems), software (applications), modules, components, servers, clients, etc. that use the methods described in embodiments of the present specification in conjunction with any necessary apparatus to implement the hardware. Based on the same innovative concept, the embodiments of the present disclosure provide an apparatus in one or more embodiments as described in the following embodiments. Since the implementation scheme of the apparatus for solving the problem is similar to that of the method, the specific implementation of the apparatus in the embodiment of the present specification may refer to the implementation of the foregoing method, and repeated details are not repeated. As used hereinafter, the term "unit" or "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

In one embodiment, as shown in fig. 5, there is provided a field programmable gate array firmware upgrade apparatus, including: a pin information obtaining module 602, a configuration module 604, an update information obtaining module 606, a pin information updating module 608, and a firmware upgrading module 610, wherein:

a pin information obtaining module 602, configured to obtain flash memory pin mapping information of the field programmable gate array;

a configuration module 604, configured to configure the field programmable gate array according to the flash pin mapping information, so as to obtain a configured field programmable gate array;

an update information obtaining module 606, configured to obtain firmware information to be updated of the field programmable gate array;

a pin information updating module 608, configured to control the configured field programmable gate array to update the running program stored in the flash memory according to the firmware information to be updated, so as to obtain an updated running program;

and the firmware upgrading module 610 is used for guiding the configured field programmable gate array to restart according to the updated running program to finish firmware upgrading.

In one embodiment, the configuration module 604 includes:

the adjusting mapping module is used for establishing an adjusting mapping relation between the processor and the flash memory according to the flash memory pin mapping information;

and the online configuration module is used for controlling the processor to perform online configuration on the field programmable gate array according to the adjustment mapping relation between the processor and the flash memory to obtain the configured field programmable gate array.

In one embodiment, the processor includes a single chip, and the adjustment mapping module is configured to: and establishing a binary netlist containing an adjustment mapping relation between the single chip microcomputer and the flash memory, wherein the binary netlist comprises a bin file and a bit file.

In one embodiment, the apparatus further comprises:

the starting module is used for starting the pins of the configured field programmable gate array;

the first interaction module is used for carrying out command interaction with the field programmable gate array and determining whether the configured field programmable gate array is successfully configured;

and the reconfiguration module is used for reconfiguring the field programmable gate array according to the pin mapping information when the configuration of the field programmable gate array fails after the configuration.

In one embodiment, the apparatus further comprises:

the second interactive module is used for carrying out command interaction with the configured field programmable gate array and determining whether the firmware of the configured field programmable gate array is upgraded successfully;

and the re-updating module is used for controlling the field programmable gate array to update the running program stored in the flash memory after the configuration again when the firmware of the field programmable gate array fails to be upgraded.

In one embodiment, the apparatus further comprises:

the comparison and verification module is used for comparing and verifying the updated running program in the flash memory with the firmware information to be updated and determining a verification result;

and the re-updating module is also used for controlling the configured field programmable gate array to update the running program stored in the flash memory when the verification result is failed.

All or part of each module in the field programmable gate array firmware upgrading device can be realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 6. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a field programmable gate array firmware upgrade method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.

Those skilled in the art will appreciate that the configuration shown in fig. 6 is a block diagram of only a portion of the configuration associated with the disclosed aspects and does not constitute a limitation on the computing devices to which the disclosed aspects apply, as a particular computing device may include more or fewer components than shown, or combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is further provided, which includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method embodiments when executing the computer program.

In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:

In one embodiment, the processor, when executing the computer program, further performs the steps of:

and establishing a binary netlist containing an adjustment mapping relation between the single chip microcomputer and the flash memory, wherein the binary netlist comprises a bin file and a bit file.

starting a pin of the configured field programmable gate array;

carrying out command interaction with the configured field programmable gate array, and determining whether the firmware of the configured field programmable gate array is upgraded successfully;

In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:

In one embodiment, the computer program when executed by the processor further performs the steps of:

starting a pin of the configured field programmable gate array;

In an embodiment, a computer program product is provided, comprising a computer program which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, performs the steps of:

The configuring the field programmable gate array according to the flash memory pin mapping information to obtain the configured field programmable gate array comprises:

starting a pin of the configured field programmable gate array;

performing command interaction with the field programmable gate array, and determining whether the configured field programmable gate array is successfully configured;

It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) referred to in the present disclosure are information and data that are authorized by the user or sufficiently authorized by each party.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, databases, or other media used in the embodiments provided by the present disclosure may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases involved in embodiments provided by the present disclosure may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided in this disclosure may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic, quantum computing based data processing logic, etc., without limitation.

All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several implementation modes of the present disclosure, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the present disclosure. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the concept of the present disclosure, and these changes and modifications are all within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the appended claims.

Claims

1. A method for upgrading firmware of a field programmable gate array, the method comprising:

2. The method of claim 1, wherein the configuring the field programmable gate array according to the flash pin mapping information to obtain a configured field programmable gate array comprises:

3. The method of claim 2, wherein the processor comprises a single chip, and the establishing the adjusted mapping relationship between the processor and the flash memory according to the pin mapping information comprises: and establishing a binary netlist containing an adjustment mapping relation between the single chip microcomputer and the flash memory, wherein the binary netlist comprises a bin file and a bit file.

4. The method of claim 1, wherein after the obtaining the configured field programmable gate array, the method further comprises:

starting a pin of the configured field programmable gate array;

5. The method of claim 1, wherein after the booting the post-configuration field programmable gate array is restarted according to the updated running program, the method further comprises:

6. The method of claim 1, wherein prior to directing the post-configuration field programmable gate array to restart according to the updated running program, the method further comprises:

7. A field programmable gate array firmware upgrade apparatus, the apparatus comprising:

8. The apparatus of claim 7, wherein the configuration module comprises:

9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 6.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 6.