CN115001919B - Timing synchronization construction method and construction system of SEFDM system - Google Patents
Timing synchronization construction method and construction system of SEFDM system Download PDFInfo
- Publication number
- CN115001919B CN115001919B CN202210386258.4A CN202210386258A CN115001919B CN 115001919 B CN115001919 B CN 115001919B CN 202210386258 A CN202210386258 A CN 202210386258A CN 115001919 B CN115001919 B CN 115001919B
- Authority
- CN
- China
- Prior art keywords
- data
- module
- parallel
- conversion
- timing synchronization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000010276 construction Methods 0.000 title claims abstract description 17
- 238000006243 chemical reaction Methods 0.000 claims abstract description 110
- 238000005070 sampling Methods 0.000 claims abstract description 82
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000001914 filtration Methods 0.000 claims abstract description 23
- 238000009432 framing Methods 0.000 claims description 27
- 239000011159 matrix material Substances 0.000 claims description 12
- 238000009825 accumulation Methods 0.000 claims description 8
- 239000000969 carrier Substances 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- 230000005540 biological transmission Effects 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims description 6
- 230000006835 compression Effects 0.000 claims description 4
- 238000007906 compression Methods 0.000 claims description 4
- 238000004364 calculation method Methods 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 239000000284 extract Substances 0.000 claims description 3
- 238000004891 communication Methods 0.000 abstract description 5
- 230000001360 synchronised effect Effects 0.000 description 16
- 238000012935 Averaging Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000003595 spectral effect Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012549 training Methods 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2657—Carrier synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/04—Protocols for data compression, e.g. ROHC
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention belongs to the technical field of wireless communication, and particularly relates to a timing synchronization construction method and a timing synchronization construction system of a SEFDM system. Firstly, the method needs to transmit a data frame with a preamble sequence at a transmitting end, and the frame structure has generality and can adapt to the implementation structure of low carrier number in a SEFDM system. Then, a data selector structure is designed, the structure is controlled by the sampling frequency estimated value to control the switch position, the switch conversion time is controlled by the preamble sequence positioning structure, and the switch control selects the output data after serial-parallel conversion. Secondly, in order to solve the problem of high complexity of a preamble sequence positioning structure, a related structure utilizing shift and addition is designed, and the positioned data is changed into frequency domain data after FrFT. Finally, a sampling frequency synchronization structure is designed, a mean value filtering structure is added for solving the problem that sampling frequency deviation fluctuates greatly under the noisy condition, and data before filtering is fed back to a data selection module.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and particularly relates to a timing synchronization construction method and a timing synchronization construction system of a SEFDM system.
Background
With the development of communication technology, a non-orthogonal transmission system becomes a focus of attention in the field of communication. A high spectral efficiency frequency division multiplexing (Spectrally Efficient Frequency Division Multiplexing, SEFDM) system is an efficient implementation in non-orthogonal transmission. Which improves spectral efficiency by compressing the subcarrier spacing in an orthogonal frequency division multiplexing (Orthogonal Frequency Division Multiplexing, OFDM) system, but introduces inter-carrier interference (Intercarrier Interference, ICI). Because of the nature of SEFDM system spectral compression, SEFDM systems may achieve higher data transmission rates than OFDM systems with the same spectral resources, and the bandwidth of SEFDM systems is also narrower than OFDM systems with the same transmission rates.
As a complete communication system, SEFDM systems require synchronization algorithms to provide their detection algorithms with data that is sampled accurately and without carrier deviation. And the timing synchronization module is an indelible loop, which can locate the optimal sampling point and estimate the sampling timing deviation.
The conventional multi-carrier system timing synchronization algorithm is used in an OFDM system, and Schmidl and Cox (S & C) firstly propose a method for performing OFDM synchronization by using a training sequence, which specifies a data structure of the training sequence, but this results in a platform region of a timing synchronization result, which is unfavorable for positioning an optimal sampling position, and has a large disadvantage under the influence of noise. In order to make up for the disadvantages of the S & C algorithm, minn modifies the data structure of the training sequence, so that the influence of the platform area can be avoided, but the influence of multipath still can be generated, so that a larger side lobe is generated, and the synchronization effect is influenced. Park is improved again on the basis of the two algorithms, and a good synchronization effect is obtained. Many of the preamble based algorithms are then improved upon these approaches.
The conventional timing synchronization algorithm of the SEFDM system is used for a plurality of conventional timing synchronization algorithms of the multi-carrier system, because the number of carriers in the data structure of the conventional multi-carrier system is more, only one domain transformation is needed for each frame, namely only one OFDM modulation symbol is needed, so that the sensitivity to sampling deviation inherent in the system is low, but the achievable detector algorithm of the SEFDM only supports the condition that the number of carriers is less, a plurality of SEFDM modulation symbols are needed for each frame of data to be filled, so that the timing error is accumulated, the data participating in the operation of fractional Fourier transformation (Fractional Fourier Transform, frFT) deviate from the optimal sampling point, the conversion quality is influenced, and the influence is increased along with the increase of the SEFDM symbols in each frame. Conventional methods may reduce the throughput rate of transmitted data by adding pilot data tracking timing offsets to the data.
Disclosure of Invention
The technical solution of the invention is as follows: the method can be effectively matched with the existing detection method, can ensure higher throughput rate, and has accurate estimation value and low implementation complexity.
The technical scheme of the invention is as follows:
the method needs to send a data frame with a preamble sequence at a sending end, and the frame structure is general and can adapt to the realization structure of low carrier number in the SEFDM system. Then, a data selector structure is designed, the structure is controlled by the sampling frequency estimated value to control the switch position, the switch conversion time is controlled by the preamble sequence positioning structure, and the switch control selects the output data after serial-parallel conversion. Secondly, in order to solve the problem of high complexity of a preamble sequence positioning structure, a related structure utilizing shift and addition is designed, and the positioned data is changed into frequency domain data after FrFT. Finally, a sampling frequency synchronization structure is designed, a mean value filtering structure is added for solving the problem that sampling frequency deviation fluctuates greatly under the noisy condition, and data before filtering is fed back to a data selection module.
The method comprises the following steps:
the first step, using the data source module to output the bit S1 to the modulation module;
secondly, using a modulation module to perform M-order linear modulation on the received bit S1 and then outputting a modulation symbol S2 to an IFrFT module;
thirdly, firstly carrying out serial-to-parallel conversion on the received modulation symbol S2 by using an IFrFT module to obtain N paths of parallel modulation symbols, then carrying out fractional order inverse Fourier transform on the N paths of parallel modulation symbols, and then carrying out parallel-to-serial conversion on output data S3 to a framing module;
fourthly, framing the received data S3 by using a framing module, and outputting S4 to a DA conversion module;
fifthly, the DA conversion module is used for carrying out DA conversion on the received data S (t) of the S4, and the data S (t) is output to the AD conversion module through a channel r (t);
sixthly, performing AD conversion on the received data r (t) by using an AD conversion module, and outputting X to a timing synchronization module;
seventh, X outputs X2 to the FrFT module through the time domain part in the timing synchronization module;
eighth step, the FrFT module firstly carries out serial-parallel conversion on the received X2 to obtain N rho parallel modulation symbols, then carries out fractional Fourier transform on the N rho parallel modulation symbols, and then gives output data X3 to a frequency domain part of the timing synchronization module through parallel-serial conversion;
and ninth, the frequency domain part of the timing synchronization module compensates the data X3 and then completes the timing synchronization of the high-frequency spectrum efficiency frequency division multiplexing system.
The timing synchronization construction system of the SEFDM system comprises a data source module, a modulation module, an IFrFT module, a framing module, a DA conversion module, an AD conversion module, a timing synchronization module and a FrFT module. The data source module is used for outputting bits S1 and outputting the outputted bits S1 to the modulation module, the modulation module is used for receiving the bits S1 outputted by the data source module, outputting modulation symbols S2 to the IFrFT module after M-order linear modulation is carried out on the received bits S1, the IFrFT module is used for receiving modulation symbols S2 outputted by the modulation module, obtaining N paths of parallel modulation symbols after serial-to-parallel conversion is carried out on the received modulation symbols S2, carrying out fractional Fourier transform on the N paths of parallel modulation symbols, outputting data S3 to the framing module through parallel-to-serial conversion, carrying out framing processing on the received data S3, outputting S4 to the DA conversion module after framing processing, carrying out AD conversion on the received data S4 by the DA conversion module, outputting X given time synchronization module after AD conversion on the received data r (t), outputting X2 to the FrFT module after the time domain part in the time synchronization module, carrying out on the X2 after the frequency domain part in the time synchronization module carries out frequency domain part of the received data r (t) by the AD conversion, carrying out frequency domain part of the received data after the frequency domain part of the received data r (t) is subjected to frequency domain synchronous conversion by the frequency domain synchronous module, carrying out frequency domain synchronous conversion on the received data after the frequency domain part of the frequency domain serial-to the received data is subjected to the frequency domain synchronous conversion by the frequency domain part of the frequency domain synchronous module, carrying out the frequency domain synchronous conversion on the received data after the received data is carried out the frequency-division conversion by the frequency-division conversion module, and carrying out the received data after carrying out the frequency-division conversion on the received data, and carrying out the data after carrying out frequency-division conversion on the data, and carrying on the received data, carrying on the received data after carrying and carrying on the data;
said bit s1= [ S1 ] 0 ,s1 1 ,…,s1 Nb-1 ] T Nb represents the number of transmission data bits;
the modulation symbol s2= [ S2 ] 0 ,s2 1 ,…,s2 Ns-1 ] T The method comprises the steps of carrying out a first treatment on the surface of the Ns represents the number of modulated symbols after modulation;
each of the N paths of parallel modulation symbols comprises Nk=Ns/N modulation symbols, N is the number of SEFDM carriers, and Nk represents the number of modulation symbols of each path after serial-parallel conversion;
the SEFDM symbol dataIs a fractional Fourier transform matrix, n rows and k columns of dataCan be expressed as: />Alpha is the compression factor of the SEFDM system;
the framing data S4 includes preamble sequence data and valid data, each data frame is divided into two parts, the first half part is the preamble sequence, including A1 SEFDM symbols, and the second half part is the valid data, including B1 SEFDM symbols. In order to ensure the bandwidth requirement, the preamble sequence data is also obtained by IFrFT operation, and the specific implementation method is that N paths of parallel data are obtained after the fixed bit data with the length of a is converted through serial-parallel conversion, and each path contains a1=a/N data. And (3) parallel data are subjected to IFrFT and parallel-serial conversion to obtain time domain preamble sequence data.
The parallel path number of the FrFT operation is expressed as Nρ=N×ρ, and ρ is an up-sampling multiple of the FrFT input data;
the FrFT operation output data X3 is expressed asPhi is SEFDM interference matrix, omega is sampling frequency deviation matrix, sampling frequency deviation matrix can be expressed as +.>ω is the amount of phase change corresponding to the sampling frequency deviation and corresponds to the delay size of the time domain data.
The timing synchronization module comprises a data selector module, a preamble sequence positioning module and a sampling frequency synchronization module, wherein the data selector module and the preamble sequence positioning module are time domain parts, and the sampling frequency synchronization module is frequency domain parts;
the data selector module consists of a serial-parallel conversion module and a judging device. The number of data paths after serial-parallel conversion is np=nu/Nd, nu is an up-sampling multiple of sampling data of the analog-digital converter, and Nd is an up-sampling multiple of single-path data after serial-parallel conversion. The input of the judging device is the estimated error value of the sampling frequency synchronous module, and the judging device controls the switch to select the output data after serial-parallel conversion;
the working process of the judging device is that after the error value is received, when the error value is in a decreasing trend and the error value is smaller than the specified lower error limit, the output sampling point of the data selector moves forward by Nm=floor (Nu/8), namely the switch moves Nm paths in the opposite direction of the data time, and the floor is rounded downwards; when the error value is in an increasing trend and is larger than the upper limit of the specified error, the output sampling point of the data selector moves backwards by Nm, namely the switch moves Nm paths towards the positive direction of the data time, wherein the value selection of Nm is only more reasonable data, and the data can be adjusted according to the corresponding situation in actual implementation;
the preamble sequence positioning module outputs Na=A×N×Nd preamble data and Nb=B×N×Nd effective data, na is the length of the up-sampled preamble sequence, nb is the length of the up-sampled effective data, and the preamble sequence positioning module is divided into a correlation structure and a structure for judging the position exceeding the maximum point in the threshold in the correlation value;
the related structure adopts a pipeline operation structure of data inversion and data shift, input data is temporarily stored through a trigger, and the number of the trigger stages is the length of a preamble sequence after up-sampling, namely Na. The data stored in the trigger are subjected to shifting operation and accumulation, the shifting bit number is determined by the transmitted time domain preamble sequence, only part of the data needs to participate in the shifting operation and the accumulation operation, the data selection mode is determined by the locally stored preamble sequence data, and the specific judgment standard is as follows:
for i＝length(c)
else c(i)＝0；
wherein c is the locally stored preamble sequence data, the up-sampling multiple of which is determined by the extraction multiple of the data selector, d is the threshold for selecting the data involved in the correlation operation, only the data greater than the threshold is involved in the operation, c (i) is the ith data of c,to take c (i) down as the nearest power of 2, the power is the shift number;
the sampling frequency synchronization module extracts an estimated value of sampling frequency deviation through phase errors between adjacent carriers, the extraction method is to correspondingly multiply a conjugate value of a pre-stored frequency domain preamble sequence with received preamble sequence data, N paths of parallel data are obtained after serial-parallel conversion of multiplier output data, the parallel data at the same moment belong to the same SEFDM symbol, then phase is calculated by a phase calculation formula, and the phase of two adjacent paths of data is subtracted to obtain a variable quantity, wherein the variable quantity is the phase error of the frequency domain and is also the sampling deviation of the time domain. Averaging the error values obtained by calculating all the preamble sequence data in each group of data frames to obtain an error estimated value of each frame, wherein the error estimated value of each frame also needs to be compensated into input data after filtering operation;
the parallel leading sequence data participating in the operation in the subtraction process is operated in the same parallel data group only, namely, the outermost data in the parallel data is subtracted once, the other data is subtracted twice, and N-1 error values can be obtained for each N parallel data;
the filtering operation is mean filtering, the output value of the filtering operation is not only required to be subjected to an averaging process, but also required to be utilized by an output value of a judging device in a data selector, and after the number of data paths selected by the data selector is changed, the final output value of the filtering operation is required to be correspondingly adjusted. When the filter outputs final data, if the flag bit is 0, the output data is unchanged, if the flag bit is 1, the output data needs to be correspondingly adjusted, the positive and negative of the adjustment data are determined by the moving direction of the data selector, the adjustment size is determined by the up-sampling multiple Nu of the ADC output sampling point, the up-sampling multiple Nd output by the data selector, and the moving path number Nm, wherein the specific value is Nd. The average filtering length can be adjusted according to actual conditions.
Advantageous effects
1. According to the invention, according to the condition that the carrier wave number applied to the current SEFDM detection algorithm is less, a SEFDM timing synchronization realizing structure is constructed by designing a preamble sequence positioning structure and a sampling frequency synchronization structure, so that the problem that the position of the FrFT input data deviates from an optimal sampling point due to the accumulation of positioning errors of a SEFDM system is effectively solved;
2. the invention uses a leading sequence positioning module in a time domain part of a receiver, uses a sampling frequency estimation structure in a frequency domain part of the receiver, and uses a data selector in front of the leading sequence positioning structure, and the data selector is used for adjusting the position of a sampling point according to a sampling frequency synchronization structure;
3. the invention uses the related operation pipeline structure of the inverse shift in the preamble sequence positioning structure, thereby effectively reducing the complexity of the preamble sequence positioning structure;
4. the invention uses the filtering structure in the sampling frequency synchronous structure, thereby effectively reducing the estimation error.
5. The SEFDM timing synchronization realizing structure effectively solves the problem that the position of the FrFT input data deviates from the optimal sampling point due to the accumulation of positioning errors of the SEFDM system;
6. the preamble sequence positioning structure uses a related operation pipeline structure of inverse shift, so that the complexity of the system is effectively reduced;
7. the invention uses the filtering structure in the sampling frequency synchronous structure, thereby effectively ensuring the accuracy of estimating the error value.
Drawings
FIG. 1 is a schematic diagram of the system components of the present invention;
fig. 2 is a schematic diagram of a data structure of the framing data S4;
fig. 3 is a schematic diagram of the composition of the timing synchronization module.
Detailed Description
The invention is further described below with reference to the drawings and examples.
Examples
The method needs to send a data frame with a preamble sequence at a sending end, and the frame structure is general and can adapt to the realization structure of low carrier number in the SEFDM system. Then, a data selector structure is designed, the structure is controlled by the sampling frequency estimated value to control the switch position, the switch conversion time is controlled by the preamble sequence positioning structure, and the switch control selects the output data after serial-parallel conversion. Secondly, in order to solve the problem of high complexity of a preamble sequence positioning structure, a related structure utilizing shift and addition is designed, and the positioned data is changed into frequency domain data after FrFT. Finally, a sampling frequency synchronization structure is designed, a mean value filtering structure is added for solving the problem that sampling frequency deviation fluctuates greatly under the noisy condition, and data before filtering is fed back to a data selection module.
The method comprises the following steps:
the first step, using the data source module to output the bit S1 to the modulation module;
secondly, using a modulation module to perform M-order linear modulation on the received bit S1 and then outputting a modulation symbol S2 to an IFrFT module;
thirdly, firstly carrying out serial-to-parallel conversion on the received modulation symbol S2 by using an IFrFT module to obtain N paths of parallel modulation symbols, then carrying out fractional order inverse Fourier transform on the N paths of parallel modulation symbols, and then carrying out parallel-to-serial conversion on output data S3 to a framing module;
fourthly, framing the received data S3 by using a framing module, and outputting S4 to a DA conversion module;
fifthly, the DA conversion module is used for carrying out DA conversion on the received data S (t) of the S4, and the data S (t) is output to the AD conversion module through a channel r (t);
sixthly, performing AD conversion on the received data r (t) by using an AD conversion module, and outputting X to a timing synchronization module;
seventh, X outputs X2 to the FrFT module through the time domain part in the timing synchronization module;
eighth step, the FrFT module firstly carries out serial-parallel conversion on the received X2 to obtain N rho parallel modulation symbols, then carries out fractional Fourier transform on the N rho parallel modulation symbols, and then gives output data X3 to a frequency domain part of the timing synchronization module through parallel-serial conversion;
and ninth, the frequency domain part of the timing synchronization module compensates the data X3 and then completes the timing synchronization of the high-frequency spectrum efficiency frequency division multiplexing system.
As shown in FIG. 1, the timing synchronization construction system of the SEFDM system comprises a data source module, a modulation module, an IFrFT module, a framing module, a DA conversion module, an AD conversion module, a timing synchronization module and a FrFT module. The data source module is used for outputting bits S1 and outputting the outputted bits S1 to the modulation module, the modulation module is used for receiving the bits S1 outputted by the data source module, outputting modulation symbols S2 to the IFrFT module after M-order linear modulation is carried out on the received bits S1, the IFrFT module is used for receiving modulation symbols S2 outputted by the modulation module, obtaining N paths of parallel modulation symbols after serial-to-parallel conversion is carried out on the received modulation symbols S2, carrying out fractional Fourier transform on the N paths of parallel modulation symbols, outputting data S3 to the framing module through parallel-to-serial conversion, carrying out framing processing on the received data S3, outputting S4 to the DA conversion module after framing processing, carrying out AD conversion on the received data S4 by the DA conversion module, outputting X given time synchronization module after AD conversion on the received data r (t), outputting X2 to the FrFT module after the time domain part in the time synchronization module, carrying out on the X2 after the frequency domain part in the time synchronization module carries out frequency domain part of the received data r (t) by the AD conversion, carrying out frequency domain part of the received data after the frequency domain part of the received data r (t) is subjected to frequency domain synchronous conversion by the frequency domain synchronous module, carrying out frequency domain synchronous conversion on the received data after the frequency domain part of the frequency domain serial-to the received data is subjected to the frequency domain synchronous conversion by the frequency domain part of the frequency domain synchronous module, carrying out the frequency domain synchronous conversion on the received data after the received data is carried out the frequency-division conversion by the frequency-division conversion module, and carrying out the received data after carrying out the frequency-division conversion on the received data, and carrying out the data after carrying out frequency-division conversion on the data, and carrying on the received data, carrying on the received data after carrying and carrying on the data;
said bit s1= [ S1 ] 0 ,s1 1 ,…,s1 Nb-1 ] T Nb represents the number of transmission data bits;
the modulation symbol s2= [ S2 ] 0 ,s2 1 ,…,s2 Ns-1 ] T The method comprises the steps of carrying out a first treatment on the surface of the Ns represents the number of modulated symbols after modulation;
each of the N paths of parallel modulation symbols comprises Nk=Ns/N modulation symbols, N is the number of SEFDM carriers, and Nk represents the number of modulation symbols of each path after serial-parallel conversion;
the SEFDM symbol dataIs a fractional Fourier transform matrix, n rows and k columns of dataCan be expressed as: />Alpha is the compression factor of the SEFDM system;
the framing data S4 includes preamble sequence data and valid data, each data frame is divided into two parts, the first half part is the preamble sequence, including A1 SEFDM symbols, and the second half part is the valid data, including B1 SEFDM symbols. The data structure of which is shown in figure 2. In order to ensure the bandwidth requirement, the preamble sequence data is also obtained by IFrFT operation, and the specific implementation method is that N paths of parallel data are obtained after the fixed bit data with the length of a is converted through serial-parallel conversion, and each path contains a1=a/N data. And (3) parallel data are subjected to IFrFT and parallel-serial conversion to obtain time domain preamble sequence data.
The parallel path number of the FrFT operation is expressed as Nρ=N×ρ, and ρ is an up-sampling multiple of the FrFT input data;
the FrFT operation output data X3 is expressed asPhi is SEFDM interference matrix, omega is sampling frequency deviation matrix, sampling frequency deviation matrix can be expressed as +.>ω is the amount of phase change corresponding to the sampling frequency deviation and corresponds to the delay size of the time domain data.
The timing synchronization module comprises a data selector module, a preamble sequence positioning module and a sampling frequency synchronization module, wherein the data selector module and the preamble sequence positioning module are time domain parts, and the sampling frequency synchronization module is frequency domain parts, and the structure of the timing synchronization module is shown in figure 3;
the data selector module consists of a serial-parallel conversion module and a judging device. The number of data paths after serial-parallel conversion is np=nu/Nd, nu is an up-sampling multiple of sampling data of the analog-digital converter, and Nd is an up-sampling multiple of single-path data after serial-parallel conversion. The input of the judging device is the estimated error value of the sampling frequency synchronous module, and the judging device controls the switch to select the output data after serial-parallel conversion;
the working process of the judging device is that after the error value is received, when the error value is in a decreasing trend and the error value is smaller than the specified lower error limit, the output sampling point of the data selector moves forward by Nm=floor (Nu/8), namely the switch moves Nm paths in the opposite direction of the data time, and the floor is rounded downwards; when the error value is in an increasing trend and is larger than the upper limit of the specified error, the output sampling point of the data selector moves backwards by Nm, namely the switch moves Nm paths towards the positive direction of the data time, wherein the value selection of Nm is only more reasonable data, and the data can be adjusted according to the corresponding situation in actual implementation;
the preamble sequence positioning module outputs Na=A×N×Nd preamble data and Nb=B×N×Nd effective data, na is the length of the up-sampled preamble sequence, nb is the length of the up-sampled effective data, and the preamble sequence positioning module is divided into a correlation structure and a structure for judging the position exceeding the maximum point in the threshold in the correlation value;
the related structure adopts a pipeline operation structure of data inversion and data shift, input data is temporarily stored through a trigger, and the number of the trigger stages is the length of a preamble sequence after up-sampling, namely Na. The data stored in the trigger are subjected to shifting operation and accumulation, the shifting bit number is determined by the transmitted time domain preamble sequence, only part of the data needs to participate in the shifting operation and the accumulation operation, the data selection mode is determined by the locally stored preamble sequence data, and the specific judgment standard is as follows:
for i＝length(c)
else c(i)＝0；
wherein c is the locally stored preamble sequence data, the up-sampling multiple of which is determined by the extraction multiple of the data selector, d is the threshold for selecting the data involved in the correlation operation, only the data greater than the threshold is involved in the operation, c (i) is the ith data of c,to take c (i) down as the nearest power of 2, the power is the shift number;
the sampling frequency synchronization module extracts an estimated value of sampling frequency deviation through phase errors between adjacent carriers, the extraction method is to correspondingly multiply a conjugate value of a pre-stored frequency domain preamble sequence with received preamble sequence data, N paths of parallel data are obtained after serial-parallel conversion of multiplier output data, the parallel data at the same moment belong to the same SEFDM symbol, then phase is calculated by a phase calculation formula, and the phase of two adjacent paths of data is subtracted to obtain a variable quantity, wherein the variable quantity is the phase error of the frequency domain and is also the sampling deviation of the time domain. Averaging the error values obtained by calculating all the preamble sequence data in each group of data frames to obtain an error estimated value of each frame, wherein the error estimated value of each frame also needs to be compensated into input data after filtering operation;
the parallel leading sequence data participating in the operation in the subtraction process is operated in the same parallel data group only, namely, the outermost data in the parallel data is subtracted once, the other data is subtracted twice, and N-1 error values can be obtained for each N parallel data;
the filtering operation is mean filtering, the output value of the filtering operation is not only required to be subjected to an averaging process, but also required to be utilized by an output value of a judging device in a data selector, and after the number of data paths selected by the data selector is changed, the final output value of the filtering operation is required to be correspondingly adjusted. When the filter outputs final data, if the flag bit is 0, the output data is unchanged, if the flag bit is 1, the output data needs to be correspondingly adjusted, the positive and negative of the adjustment data are determined by the moving direction of the data selector, the adjustment size is determined by the up-sampling multiple Nu of the ADC output sampling point, the up-sampling multiple Nd output by the data selector, and the moving path number Nm, wherein the specific value is Nd. The average filtering length can be adjusted according to actual conditions.
In addition, the timing synchronization module provided by the invention has low complexity and good system performance.
In summary, the above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for constructing timing synchronization of a SEFDM system is characterized by comprising the following steps:
the first step, using the data source module to output the bit S1 to the modulation module;
secondly, using a modulation module to perform M-order linear modulation on the received bit S1 and then outputting a modulation symbol S2 to an IFrFT module;
thirdly, firstly carrying out serial-to-parallel conversion on the received modulation symbol S2 by using an IFrFT module to obtain N paths of parallel modulation symbols, then carrying out fractional order inverse Fourier transform on the N paths of parallel modulation symbols, and then carrying out parallel-to-serial conversion on output data S3 to a framing module;
fourthly, framing the received data S3 by using a framing module, and outputting framing data S4 to a DA conversion module;
fifthly, the DA conversion module is used for carrying out DA conversion on the received framing data S4, and the data S (t) after DA conversion is output to the AD conversion module through a channel r (t);
sixthly, performing AD conversion on the received data r (t) by using an AD conversion module, and outputting X to a timing synchronization module;
seventh, X outputs X2 to the FrFT module through the time domain part in the timing synchronization module;
eighth step, the FrFT module firstly carries out serial-parallel conversion on the received X2 to obtain N rho parallel modulation symbols, then carries out fractional Fourier transform on the N rho parallel modulation symbols, and then gives output data X3 to a frequency domain part of the timing synchronization module through parallel-serial conversion;
and ninth, compensating the data X3 by a frequency domain part of the timing synchronization module to finish timing synchronization of the SEFDM system.
2. The method for constructing the timing synchronization of the SEFDM system according to claim 1, wherein:
said bit s1= [ S1 ] 0 ,s1 1 ,…,s1 Nb-1 ] T Nb represents the number of transmission data bits;
the modulation symbol s2= [ S2 ] 0 ,s2 1 ,…,s2 Ns-1 ] T The method comprises the steps of carrying out a first treatment on the surface of the Ns represents the number of modulated symbols after modulation;
each of the N paths of parallel modulation symbols comprises Nk=Ns/N modulation symbols, N is the number of SEFDM carriers, and Nk represents the number of modulation symbols of each path after serial-parallel conversion;
said dataIs a fractional Fourier transform matrix, n rows and k columns of data +.>Expressed as:alpha is the compression factor of the SEFDM system.
3. The method for constructing the timing synchronization of the SEFDM system according to claim 2, wherein:
the framing data S4 comprises preamble sequence data and effective data, each data frame is divided into two parts, the first half part is the preamble sequence data and comprises A1 SEFDM symbols, and the second half part is the effective data and comprises B1 SEFDM symbols;
the method for acquiring the preamble sequence data comprises the following steps: and (3) carrying out serial-parallel conversion on fixed bit data with the length of A to obtain N paths of parallel data, wherein each path contains A1=A/N data, and carrying out IFrFT on the parallel data to obtain time domain preamble sequence data after the parallel data is subjected to parallel-serial conversion.
4. A method for constructing timing synchronization of SEFDM system according to claim 3, wherein:
the parallel path number of the FrFT operation is expressed as Nρ=N×ρ, and ρ is an up-sampling multiple of the FrFT input data;
the data X3 is expressed asPhi is SEFDM interference matrix, omega is sampling frequency deviation matrix, sampling frequency deviation matrix is expressed as +.>ω is the amount of phase change corresponding to the sampling frequency deviation and corresponds to the delay size of the time domain data.
5. A timing synchronization construction system of a SEFDM system, characterized in that:
the construction system comprises a data source module, a modulation module, an IFrFT module, a framing module, a DA conversion module, an AD conversion module, a timing synchronization module and a FrFT module;
the data source module is used for outputting a bit S1 and outputting the output bit S1 to the modulation module;
the modulation module is used for receiving the bit S1 output by the data source module, and outputting a modulation symbol S2 to the IFrFT module after M-order linear modulation is carried out on the received bit S1;
the IFrFT module is used for receiving the modulation symbol S2 output by the modulation module, carrying out serial-to-parallel conversion on the received modulation symbol S2 to obtain N paths of parallel modulation symbols, carrying out fractional order inverse Fourier transform on the N paths of parallel modulation symbols, and carrying out parallel-to-serial conversion on output data S3 to the framing module;
the framing module is used for receiving the data S3 output by the IFrFT module, framing the received data S3 and outputting S4 to the DA conversion module;
the DA conversion module performs DA conversion on the received S4, and outputs r (t) to the AD conversion module through a channel;
the AD conversion module performs AD conversion on the received data r (t) and then outputs X to the timing synchronization module;
the timing synchronization module is used for receiving X, and the X outputs X2 to the FrFT module through a time domain part in the timing synchronization module;
the FrFT module firstly carries out serial-parallel conversion on X2 to obtain N rho parallel modulation symbols, then carries out fractional Fourier transform on the N rho parallel modulation symbols, outputs data X3 through parallel-serial conversion to a frequency domain part of the timing synchronization module, and the frequency domain part of the timing synchronization module compensates the data X3.
6. The timing synchronization construction system of a SEFDM system according to claim 5, wherein:
the timing synchronization module comprises a data selector module, a preamble sequence positioning module and a sampling frequency synchronization module, wherein the data selector module and the preamble sequence positioning module are time domain parts, and the sampling frequency synchronization module is frequency domain parts;
the data selector module consists of a serial-parallel conversion module and a judging device, wherein the number of data paths after serial-parallel conversion is Np=Nu/Nd, nu is an up-sampling multiple of sampling data of the AD conversion module, nd is an up-sampling multiple of single-path data after serial-parallel conversion, the input of the judging device is an estimated error value of the sampling frequency synchronization module, and the judging device controls the switch to select output data after serial-parallel conversion.
7. The timing synchronization construction system of a SEFDM system of claim 6, wherein:
the working process of the judging device is that after the estimated error value is received, when the estimated error value is in a decreasing trend and the estimated error value is smaller than the specified error lower limit, the output sampling points of the data selector module move forward by Nm=floor (Nu/8), namely the switch moves Nm paths towards the opposite direction of the data time, and floor is a downward rounding; when the estimated error value is in an increasing trend and the estimated error value is greater than the prescribed upper error limit, the output sampling point of the data selector module will move backward by Nm, i.e. the switch moves forward by Nm paths in the data time direction.
8. The timing synchronization construction system of a SEFDM system of claim 7, wherein:
the preamble sequence positioning module outputs Na=A×N×Nd preamble sequence data and Nb=B×N×Nd effective data, wherein Na is the length of the up-sampled preamble sequence, nb is the length of the up-sampled effective data, and the preamble sequence positioning module is divided into a correlation structure and a structure for judging the position exceeding the maximum point in the threshold in the correlation value;
the related structure adopts a pipeline operation structure of data inversion and data shift, input data is temporarily stored through a trigger, the number of the trigger stages is the length of a preamble sequence after up sampling, namely Na, the data stored in the trigger is subjected to shift operation and accumulation, the shift bit number is determined by a transmitted time domain preamble sequence, only part of data needs to participate in the shift operation and the accumulation operation, the data selection mode is determined by the locally stored preamble sequence data, and the specific judgment standard is as follows:
for i＝lenght(c)
else c(i)＝0；
wherein c is the locally stored preamble sequence data, the up-sampling multiple of which is determined by the extraction multiple of the data selector, d is the threshold for selecting the data involved in the correlation operation, only the data greater than the threshold is involved in the operation, c (i) is the ith data of c,to take c (i) down to the nearest power of 2, the power is the shift number.
9. The timing synchronization construction system of an SEFDM system of claim 8, wherein:
the sampling frequency synchronization module extracts the estimated value of sampling frequency deviation through the phase error between adjacent carriers, the extraction method is to multiply the conjugate value of the pre-stored frequency domain preamble sequence with the received preamble sequence data correspondingly, the output data of the multiplier is subjected to serial-parallel conversion to obtain N paths of parallel data, the parallel data at the same moment belong to the same SEFDM symbol, the phase of the adjacent two paths of data is obtained through phase subtraction by using a phase angle calculation formula, the variable is the phase error of the frequency domain and is also the sampling deviation of the time domain, the phase errors obtained by calculating all the preamble sequence data in each group of data frames are averaged to obtain the estimated error value of each frame, the estimated error value of each frame is also required to be compensated into the input data after filtering operation, the parallel preamble sequence data participating in operation in the subtraction process is only calculated in the same parallel data group, namely, the outermost data in the parallel data are subtracted once, the other data are subtracted twice, and N-1 phase errors are obtained for each N parallel data.
10. The timing synchronization construction system of a SEFDM system according to claim 9, wherein:
the filtering operation is mean filtering, when the data selector module adjusts, the adjusting flag bit of the current frame is marked as 1, when the data selector module does not adjust, the adjusting flag bit of the current frame is marked as 0, when the filter outputs final data, if the adjusting flag bit is 0, the output data is unchanged, if the adjusting flag bit is 1, the output data needs to be correspondingly adjusted, the positive and negative of the adjusting data are determined by the moving direction of the data selector module, the adjusting size is determined by the up-sampling multiple Nu of the output sampling point of the AD conversion module and the up-sampling multiple Nd of the output of the data selector module, and the moving path number Nm is determined, wherein the specific numerical value is Nd/2pi.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210386258.4A CN115001919B (en) | 2022-04-13 | 2022-04-13 | Timing synchronization construction method and construction system of SEFDM system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210386258.4A CN115001919B (en) | 2022-04-13 | 2022-04-13 | Timing synchronization construction method and construction system of SEFDM system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115001919A CN115001919A (en) | 2022-09-02 |
| CN115001919B true CN115001919B (en) | 2023-12-05 |
Family
ID=83023779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210386258.4A Active CN115001919B (en) | 2022-04-13 | 2022-04-13 | Timing synchronization construction method and construction system of SEFDM system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115001919B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1588937A (en) * | 2004-08-26 | 2005-03-02 | 浙江大学 | Self adaption orthogonal frequency division multiplexing transmitting method and system variable subcarrier number |
| CN1809045A (en) * | 2005-12-12 | 2006-07-26 | 北京北方烽火科技有限公司 | Combined time synchronization method for receiving end of WiMAX system base station |
| CN107135057A (en) * | 2017-05-03 | 2017-09-05 | 哈尔滨工业大学 | A kind of efficient frequency division multiplexing Waveform generation method expanded based on zero hangover DFT |
| CN107318157A (en) * | 2017-05-24 | 2017-11-03 | 中国航空无线电电子研究所 | Timing error estimate method based on targeting sequencing |
| CN109981223A (en) * | 2019-04-02 | 2019-07-05 | 中国科学院上海高等研究院 | Multicarrier FTN transmission/method of reseptance and relevant device based on FRFT |
| CN110971307A (en) * | 2019-11-08 | 2020-04-07 | 华中科技大学 | Method for compensating interference between subcarriers inherent to SEFDM system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014153370A2 (en) * | 2013-03-16 | 2014-09-25 | Holguin-Sanchez Fausto D | Methods for creating and receiving multi-carrier signals. codification, communication and detection apparatus. tunable noise-correction method for overlapped signals. iterative estimation method for overlapped signals. |
-
2022
- 2022-04-13 CN CN202210386258.4A patent/CN115001919B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1588937A (en) * | 2004-08-26 | 2005-03-02 | 浙江大学 | Self adaption orthogonal frequency division multiplexing transmitting method and system variable subcarrier number |
| CN1809045A (en) * | 2005-12-12 | 2006-07-26 | 北京北方烽火科技有限公司 | Combined time synchronization method for receiving end of WiMAX system base station |
| CN107135057A (en) * | 2017-05-03 | 2017-09-05 | 哈尔滨工业大学 | A kind of efficient frequency division multiplexing Waveform generation method expanded based on zero hangover DFT |
| CN107318157A (en) * | 2017-05-24 | 2017-11-03 | 中国航空无线电电子研究所 | Timing error estimate method based on targeting sequencing |
| CN109981223A (en) * | 2019-04-02 | 2019-07-05 | 中国科学院上海高等研究院 | Multicarrier FTN transmission/method of reseptance and relevant device based on FRFT |
| CN110971307A (en) * | 2019-11-08 | 2020-04-07 | 华中科技大学 | Method for compensating interference between subcarriers inherent to SEFDM system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115001919A (en) | 2022-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11108612B2 (en) | Anti-interference signal detection and synchronization method for wireless broadband communication system | |
| JP4298320B2 (en) | Receiver for OFDM transmission system | |
| CN101079688B (en) | A synchronization method in orthogonal frequency division multiplexing system | |
| US8131218B2 (en) | Methods and apparatus for wirelessly communicating signals that include embedded synchronization/pilot sequences | |
| KR101246583B1 (en) | Frequency domain channel estimation in a single carrier frequency division multiple access system | |
| US20050213689A1 (en) | Demodulator circuit, radio communication system and communication semiconductor integrated circuit | |
| KR100811892B1 (en) | Channel equalization and carrier recovery method and receiver in high-speed wireless communication system | |
| CN104836769B (en) | A kind of joint timing leading based on conjugated structure and frequency synchronization method | |
| US20050201270A1 (en) | Method and apparatus for transmitting and receiving pilot signals in an orthogonal frequency division multiple access system | |
| US8300621B2 (en) | System and method for timing acquisition and carrier frequency offset estimation in wireless communication based on OFDM | |
| WO2018202038A1 (en) | Uplink synchronization timing deviation determination method and device | |
| JP2013521729A (en) | Method and apparatus for accurate time synchronization in a wireless communication system | |
| CN107086974B (en) | OFDM synchronization method and telemetering system under high dynamic environment | |
| EP2404416A1 (en) | A method of and equipment for compensating carrier frequency offset in an orthogonal frequency division multiplexing wireless radio transmission system | |
| JP4644978B2 (en) | OFDM communication system, OFDM communication method, and OFDM communication apparatus | |
| JP4043287B2 (en) | Wireless communication system, communication apparatus, and reception quality measuring method | |
| CN110971558B (en) | CAZAC sequence-based low-complexity anti-frequency offset synchronization method | |
| KR20100060456A (en) | Method and apparatus for estimating carrier frequency in a wireless communication system | |
| CN110557349A (en) | Method and device for generating and receiving synchronization signal of hierarchical structure | |
| CN104836770B (en) | It is a kind of based on related average and adding window timing estimation method | |
| CN113973031B (en) | Channel equalization method of OFDM system | |
| CN115001919B (en) | Timing synchronization construction method and construction system of SEFDM system | |
| JP2009049491A (en) | Receiving apparatus, receiving method, and program | |
| KR100321937B1 (en) | Frequency offset correcting system in orthogonal frequency division multiplex | |
| JP7458865B2 (en) | Single carrier receiving device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |