CN115001902A - Control gateway capable of encrypting and decrypting, method and data transmission method and equipment - Google Patents

Control gateway capable of encrypting and decrypting, method and data transmission method and equipment Download PDF

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Publication number
CN115001902A
CN115001902A CN202210449376.5A CN202210449376A CN115001902A CN 115001902 A CN115001902 A CN 115001902A CN 202210449376 A CN202210449376 A CN 202210449376A CN 115001902 A CN115001902 A CN 115001902A
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China
Prior art keywords
gateway
module
data
encryption
fpga module
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Pending
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CN202210449376.5A
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Chinese (zh)
Inventor
石殊
邱昕
郭瑞
赵振亚
荆有波
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN202210449376.5A priority Critical patent/CN115001902A/en
Publication of CN115001902A publication Critical patent/CN115001902A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/66—Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
    • H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Small-Scale Networks (AREA)

Abstract

The present disclosure provides an encryption and decryption control gateway, including: the FPGA module is used for receiving data and outputting the data after the data is encrypted or decrypted; the encryption and decryption module is connected with the FPGA module and is used for encrypting or decrypting the data received by the FPGA module; and the stm32 module is connected with the FPGA module and used for controlling the FPGA module to enter a low power consumption state when no data transmission exceeding a preset time is detected in the FPGA module.

Description

Control gateway capable of encrypting and decrypting, method and data transmission method and equipment
Technical Field
The present disclosure relates to the field of communications, and in particular, to an encryptable and decryptable control gateway, a method, a data transmission method, and a device.
Background
The gateway is also called an internetwork connector and a protocol converter. The default gateway realizes network interconnection above a network layer, is the most complex network interconnection equipment and is only used for interconnection of two networks with different high-level protocols. The gateway can be used for interconnection of both wide area networks and local area networks.
With the increasing security form of network data, the demand of users for encryptable gateways is also increasing. Meanwhile, with the rapid development of computers and microelectronic technologies, the application fields of gateway devices are becoming wider, which causes low power consumption to become an important consideration in the design of gateway devices.
In order to solve the above problems, a gateway capable of performing an encryption or decryption operation on data and operating with low power consumption is needed.
Disclosure of Invention
In view of the above, the present disclosure provides an encryption/decryption control gateway, including: the FPGA module is used for receiving data and outputting the data after the data is encrypted or decrypted; the encryption and decryption module is connected with the FPGA module and is used for encrypting or decrypting the data received by the FPGA module; and the stm32 module is connected with the FPGA module and used for controlling the FPGA module to enter a low power consumption state when no data transmission exceeding a preset time is detected in the FPGA module.
Optionally, the FPGA module comprises: one end of the input gigabit Ethernet is connected with the input end of the FPGA module through a first RGMII interface, and the other end of the input gigabit Ethernet is externally provided with a first standard Ethernet RJ45 interface; and one end of the output gigabit Ethernet is connected with the output end of the FPGA module through a second RGMII interface, and the other end of the output gigabit Ethernet is externally provided with a second standard Ethernet RJ45 interface.
Optionally, the FPGA module further includes: the power supply adopts an anti-surge protection design.
Optionally, the control gateway capable of encrypting and decrypting comprises: the FPGA module, the encryption and decryption module and the stm32 module all provide debugging interfaces externally.
Optionally, the debug interface includes: and the detection circuit is used for detecting whether the debugging interface has the access of external equipment.
A second aspect of the present disclosure provides an encryption and decryption control method, which is applied to the encryption and decryption control gateway, and includes: receiving data through an FPGA module; encrypting or decrypting the data through an encryption and decryption module; outputting the encrypted or decrypted data through the FPGA module; when the stm32 module detects that the preset time is exceeded in the FPGA module and the data transmission is not carried out, when the stm32 module detects that the preset time is exceeded in the FPGA module and the data transmission is not carried out, the stm32 module controls the FPGA module to enter a low power consumption state.
A third aspect of the present disclosure provides a data transmission method, applied to an encryption gateway and a decryption gateway, where the encryption gateway and the decryption gateway are the encryption-decryption control gateway, and the method includes: inputting data into the encryption gateway, and encrypting and outputting the data by the encryption gateway; transmitting the encrypted data to the decryption gateway, and decrypting and outputting the encrypted data by the decryption gateway; and when no data is transmitted for more than a preset time, the encryption gateway and the decryption gateway enter a low power consumption state.
A fourth aspect of the present disclosure proposes an apparatus, which includes the control gateway capable of encrypting and decrypting.
According to the technical scheme, the encryption and decryption control gateway enables the gateway to encrypt or decrypt data by setting the encryption and decryption module, and meanwhile, the STm32 module monitors the data flow condition in real time, so that the power consumption of the encryption and decryption control gateway is reduced when data transmission does not exist in the FPGA module for a long time.
Drawings
The foregoing and other objects, features and advantages of the disclosure will be apparent from the following description of embodiments of the disclosure, which proceeds with reference to the accompanying drawings, in which:
fig. 1 schematically illustrates an exemplary system architecture of an encryptable decryption control gateway, in accordance with an embodiment of the disclosure;
fig. 2 schematically shows a power supply diagram of an FPGA module of an encryptable and decryptable control gateway according to an embodiment of the disclosure;
fig. 3 schematically shows a debug interface diagram of an FPGA module of an encryptable and decryptable control gateway according to an embodiment of the present disclosure;
FIG. 4 schematically illustrates an encryptable and decryptable control method according to an embodiment of the disclosure;
fig. 5 schematically illustrates a data transmission method according to an embodiment of the present disclosure.
Fig. 6 schematically illustrates a data transmission system according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms, including technical and scientific terms, used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.
Where a convention analogous to "at least one of A, B and C, etc." is used, in general such a construction should be interpreted in the sense one having skill in the art would normally understand the convention, e.g., "a device having at least one of A, B and C" would include but not be limited to devices having a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.
An encryptable and decryptable control gateway, comprising: the FPGA module is used for receiving data and outputting the data after the data is encrypted or decrypted; the encryption and decryption module is connected with the FPGA module and used for encrypting or decrypting data received by the FPGA module; the stm32 module is connected with the FPGA module for when detecting that there is not data transmission in the FPGA module beyond the default time, control FPGA module entering low-power consumption state.
Fig. 1 schematically shows an architecture diagram of an encryptable and decryptable control gateway in an embodiment of the present disclosure.
As shown in fig. 1, the control gateway capable of encrypting and decrypting includes: FPGA module, encryption and decryption module, stm32 module.
The FPGA module is used for receiving data and outputting the data after the data are encrypted or decrypted. As shown in fig. 1. The FPGA module includes: the system comprises an FPGA chip, unit modules for inputting and outputting gigabit Ethernet, a power supply and the like.
The FPGA chip is a field programmable array, appears as a semi-custom circuit in the field of application-specific integrated circuits, overcomes the defects of the custom circuit and overcomes the defect of limited gate circuits of the original programmable device. In an embodiment of the present disclosure, the FPGA chip may be XC7a200TFBG484, and the FPGA chip expands 120 IO ports, which may satisfy a requirement of the encryptable gateway of the present disclosure for a large number of IO ports. In addition, the routing from the FPGA chip to the IO interface is subjected to equal length and differential processing so as to restrict the time sequence requirement on the routing and meet the requirement of high-speed transmission.
Gigabit ethernet is a technology based on the ethernet standard, providing 1000 mbps of bandwidth. The FPGA module comprises an input gigabit Ethernet and an output gigabit Ethernet, and forms a circuit framework with double network ports. One end of the input gigabit Ethernet is connected with the input end of the FPGA module through a first RGMII interface, and the other end of the input gigabit Ethernet provides a first standard Ethernet RJ45 interface to the outside; one end of the output gigabit Ethernet is connected with the output end of the FPGA module through a second RGMII interface, and the other end of the output gigabit Ethernet provides a second standard Ethernet RJ45 interface outwards. It should be noted that, when the input gigabit ethernet and the output gigabit ethernet are interconnected with the FPGA chip, all the traces adopt an equal-length design to meet the requirements of timing sequence consistency and high-speed transmission. In an embodiment of the present disclosure, an IP1001MLF chip may be used for the input gigabit ethernet and the output gigabit ethernet, and the chip integrates 10/100/1000M ethernet transceiver circuitry inside, uses 25M clock input, and provides 125M GTX clock when operating in gigabit mode.
In the data transmission process, the FPGA has a large power consumption requirement, so that a power supply needs to be designed to provide electric energy for the FPGA module. As shown in fig. 2, in an embodiment of the present disclosure, the power supply may be an LMZ2010 chip, which may provide 20V maximum input voltage and 10A current, the conversion efficiency is 92%, the output voltage ripple is low, no external heat sink is required, and the operating temperature is-40 to-125 ℃.
Preferably, the power supply of the present disclosure employs an anti-surge protection arrangement.
The encryption and decryption module is connected with the FPGA module and used for encrypting or decrypting data received by the FPGA module. An encryption and decryption chip is arranged in the encryption and decryption module. The encryption and decryption chip is interconnected with the FPGA module through the GPIO pin. In an embodiment of the present disclosure, the encryption/decryption chip may be a BHD5 chip. The chip can realize an AES encryption algorithm and an SM1 cipher algorithm, encrypt data streams in the FPGA, and provide a high data throughput speed and a high-strength encryption algorithm. The BHD5 chip supports encryption/decryption operations of the AES algorithm and the SM1 algorithm. The key length supported by the AES algorithm is 256 bits; the SM1 algorithm supports 14 rounds of operation, and the basic key EKEY and the auxiliary key AKEY are 128 bits; both of the above keys need to be properly configured via the AHB bus of the BHD5 chip. In addition, the SM1 algorithm also has a 128-bit system key SKEY, which has a default value after the BHD5 chip is reset, and the default value of SKEY can be used in actual use and can also be changed. The BHD5 chip has two sets of RAM interfaces: RAM0 (base address 0x24000) and RAM1 (base address 0x 20000). When the encryption operation is performed, data in the RAM0 is encrypted and the result is stored in the RAM1, and when the decryption operation is performed, data in the RAM1 is decrypted and the result is stored in the RAM 0.
The stm32 module is connected with the FPGA module for when detecting that there is not data transmission in the FPGA module beyond the default time, control FPGA module entering low-power consumption state. The stm32 module is connected with the FPGA module through a serial port. And stm32 module is normally open the module to whether there is the data transmission action in monitoring the FPGA module constantly, when detecting that the inside no data of FPGA module carries out the transfer transmission, give the FPGA module through sending the low-power consumption instruction, close the enable of input gigabit ethernet in the FPGA module, thereby reduce the consumption. In an embodiment of this disclosure, STM32 module can use the STM32F103 chip to use 3.3V to supply FPGA module, encryption/decryption module and STM32 module all to provide debugging interface outward. FPGA module, encryption and decryption module and stm32 module can all utilize the debugging interface of self to interact with outside equipment, and FPGA module, encryption and decryption module and stm32 module can be through respective debugging interface transmission printing information to outside equipment promptly to receive external equipment's user's configuration instruction through respective debugging interface. For example, as shown in fig. 3, a CH340G chip may be used as a debugging interface of the FPGA module, and CH340G is a switching chip of a USB bus, so as to implement USB to serial port conversion, and in a serial port mode, CH340G provides a common MODEM contact signal for extending an asynchronous serial port to the FPGA module, and upgrades a common serial device to the USB bus.
Preferably, the debug interface further comprises a detection circuit for detecting whether the external device is connected by detecting whether the external voltage is connected to the debug interface. For example, as shown in fig. 3, when the debugging interface of the FPGA module is plugged into an external device, the external device is connected to the 5V _ USB _ Mini port, and a 5V power supply is generated, and the power supply acts on the level buffer chip 74HC245PW, and a 3.3V power supply can be obtained through the voltage division of the resistor at the pin 2. Since the pin1 signal DIR of the chip 74HC245PW is high, the chip transfer direction is from a to B, so when external and devices are connected to the 5V _ USB _ Mini port, the C340_ UART _ INSERT at B0 corresponding to pin2 is high. And a detection circuit of the debugging interface is interconnected with the C340_ UART _ INSERT, the level at the C340_ UART _ INSERT is detected in real time, and when the high level is detected, the insertion of external equipment is indicated, so that the FPGA module is informed.
Fig. 4 schematically shows an encryptable and decryptable control method. The method is applied to the control gateway which can be encrypted and decrypted. As shown in fig. 4, the network control method capable of encrypting and decrypting includes steps S410 to S440.
And step S410, receiving data through the FPGA module.
In step S420, the data is encrypted or decrypted by the encryption/decryption module.
And step S430, outputting the encrypted or decrypted data through the FPGA module.
Step S440, data transmission in the FPGAFPGA module is detected through the stm32 module, and when the stm32 module detects that no data transmission exceeds the preset time in the FPGA module, the stm32 module controls the FPGA module to enter a low power consumption state.
According to this disclosed embodiment, in the control gateway use that can encrypt the decryption, data are from the input gigabit ethernet input FPGA module of the control gateway that can encrypt the decryption, keep in after the FPGA module receives data, start the encryption and decryption module simultaneously, realize encrypting or the decryption operation to data, export from exporting the gigabit ethernet at last. The stm32 module is introduced, the working condition of FPGA data transmission is detected in real time through a serial port, if no data transmission exists for a long time (5 minutes), a command is sent to close the enable of the gigabit Ethernet in the FPGA module, the FPGA module is turned off, and the power consumption of equipment is reduced.
Fig. 5 schematically shows a data transmission method applied to an encryption gateway and a decryption gateway. The encryption gateway and the decryption gateway are the control gateways capable of encrypting and decrypting. The encryption and decryption module in the encryption gateway is set to only perform encryption work, the encryption and decryption module in the decryption gateway is set to only perform decryption work, and the encryption rule and the decryption rule of the encryption gateway and the decryption gateway are corresponding. As shown in fig. 5, the encryption and decryption control method includes steps S510 to S530.
And step S510, inputting the data into the FPGA encryption gateway, and encrypting and outputting the data by the FPGA encryption gateway.
And step S520, transmitting the encrypted data to the FPGA decryption gateway, and decrypting and outputting the encrypted FPGA data by the FPGA decryption gateway.
Step S530, when no data is transmitted after the preset time, the FPGA encryption gateway and the FPGA decryption gateway enter a low power consumption state.
According to the embodiment of the present disclosure, when data exchange is performed between the internal lan and the external lan, the data transmission system is as shown in fig. 6. The FPGA module of the original data input encryption gateway of the internal local area network, the encryption and decryption module of the encryption gateway are started, the original data are encrypted to form encrypted data, and the encrypted data are output from the encryption gateway and are transmitted to the decryption gateway on signal transmission media such as electric wires. After the FPGA module of the decryption gateway receives the encrypted data, the encryption and decryption module of the decryption gateway is started, and the encrypted data is decrypted by using the decryption rule corresponding to the encryption rule of the encryption and decryption module of the encryption gateway, so that the decrypted data consistent with the original data can be obtained. The decryption gateway inputs the decrypted data into the external local area network.
The data transmission condition of monitoring constantly of stm32 module of encryption gateway and the stm32 module of deciphering gateway if do not carry out data transmission for a long time between inside LAN and the outside LAN, and the stm32 module of encryption gateway and the stm32 module of deciphering gateway make encryption gateway and deciphering gateway get into the low power consumption state.
The data transmission method enables the data to be in an encrypted state when the data is transmitted between the two local area networks, and improves the safety in the data transmission process. When no data transmission exists between the two local area networks for a long time, the encryption gateway and the decryption gateway enter a low power consumption state, so that the whole data transmission system is more energy-saving.
The disclosure also provides a device, which includes the above encryption and decryption control gateway. It should be understood that the devices referred to in this disclosure may be network switches, routers, firewalls, etc. devices with gateway functionality.
It will be appreciated by a person skilled in the art that various combinations or/and combinations of features recited in the various embodiments of the disclosure and/or in the claims may be made, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, various combinations and/or combinations of the features recited in the various embodiments of the present disclosure and/or the claims may be made without departing from the spirit and teachings of the present disclosure. All such combinations and/or associations are within the scope of the present disclosure.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the disclosure, and these alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (8)

1. An encryptable and decryptable control gateway, comprising:
the FPGA module is used for receiving data and outputting the data after the data is encrypted or decrypted;
the encryption and decryption module is connected with the FPGA module and is used for encrypting or decrypting the data received by the FPGA module;
and the stm32 module is connected with the FPGA module and used for controlling the FPGA module to enter a low power consumption state when no data transmission exceeding a preset time is detected in the FPGA module.
2. The encryptable and decryptable control gateway of claim 1, further comprising:
one end of the input gigabit Ethernet is connected with the input end of the FPGA module through a first RGMII interface, and the other end of the input gigabit Ethernet is externally provided with a first standard Ethernet RJ45 interface;
and one end of the output gigabit Ethernet is connected with the output end of the FPGA module through a second RGMII interface, and the other end of the output gigabit Ethernet is externally provided with a second standard Ethernet RJ45 interface.
3. The encryptable and decryptable control gateway of claim 1, wherein the FPGA module further comprises:
the power supply adopts an anti-surge protection design.
4. The encryptable and decryptable control gateway of claim 1, comprising:
the FPGA module, the encryption and decryption module and the stm32 module all provide debugging interfaces externally.
5. The encryptable and decryptable control gateway of claim 4, wherein the debug interface comprises:
and the detection circuit is used for detecting whether the debugging interface has the access of external equipment.
6. An encryption and decryption control method applied to the encryption and decryption control gateway according to any one of claims 1 to 5, comprising:
receiving data through an FPGA module;
encrypting or decrypting the data through an encryption and decryption module;
outputting the encrypted or decrypted data through the FPGA module;
when the stm32 module detects that the preset time is exceeded in the FPGA module and the data transmission is not carried out, when the stm32 module detects that the preset time is exceeded in the FPGA module and the data transmission is not carried out, the stm32 module controls the FPGA module to enter a low power consumption state.
7. A data transmission method is applied to an encryption gateway and a decryption gateway, wherein the encryption gateway and the decryption gateway are the control gateway capable of encrypting and decrypting according to any one of claims 1 to 5, and the method comprises the following steps:
inputting data into the encryption gateway, and encrypting and outputting the data by the encryption gateway;
transmitting the encrypted data to the decryption gateway, and decrypting and outputting the encrypted data by the decryption gateway;
and when no data is transmitted for more than a preset time, the encryption gateway and the decryption gateway enter a low power consumption state.
8. An apparatus comprising an encryptable and decryptable control gateway as claimed in any one of claims 1 to 5.
CN202210449376.5A 2022-04-26 2022-04-26 Control gateway capable of encrypting and decrypting, method and data transmission method and equipment Pending CN115001902A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107094137A (en) * 2017-04-07 2017-08-25 山东超越数控电子有限公司 A kind of VPN security gateways
CN112689253A (en) * 2019-10-18 2021-04-20 航天科工惯性技术有限公司 Low-power-consumption bidirectional-triggering multi-network-integrated ground disaster monitoring system and method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107094137A (en) * 2017-04-07 2017-08-25 山东超越数控电子有限公司 A kind of VPN security gateways
CN112689253A (en) * 2019-10-18 2021-04-20 航天科工惯性技术有限公司 Low-power-consumption bidirectional-triggering multi-network-integrated ground disaster monitoring system and method

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