CN115001461A - Comparison circuit, comparison method and semiconductor memory - Google Patents

Comparison circuit, comparison method and semiconductor memory Download PDF

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Publication number
CN115001461A
CN115001461A CN202210724969.8A CN202210724969A CN115001461A CN 115001461 A CN115001461 A CN 115001461A CN 202210724969 A CN202210724969 A CN 202210724969A CN 115001461 A CN115001461 A CN 115001461A
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circuit
switching tube
code
comparison
sub
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程伟杰
罗元钧
杨正杰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The embodiment of the application provides a comparison circuit, a comparison method and a semiconductor memory, wherein the comparison circuit comprises at least one data selector and at least one control signal generation circuit corresponding to the at least one data selector; the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding control signal generating circuit; the first input end and the second input end of the corresponding control signal generating circuit are correspondingly connected with the ith comparison code and the jth comparison code; each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code; and the corresponding control signal generating circuit is used for generating a corresponding control signal to output according to the comparison result of the ith comparison code and the jth comparison code.

Description

Comparison circuit, comparison method and semiconductor memory
Technical Field
The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a comparison circuit, a comparison method, and a semiconductor memory.
Background
In the related art, for the comparison circuit between the comparison codes of the multi-bit binary code, a considerable number of switching tubes are required to implement the comparison circuit, and the circuit is relatively complex.
Disclosure of Invention
In view of the above, embodiments of the present application provide a comparison circuit, a comparison method and a semiconductor memory.
In a first aspect, an embodiment of the present application provides a comparison circuit, including at least one data selector, and at least one control signal generation circuit corresponding to the at least one data selector;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding control signal generating circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the first input end and the second input end corresponding to the control signal generating circuit are correspondingly connected with the ith comparison code and the jth comparison code;
each data selector is used for responding to a corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
and the corresponding control signal generating circuit is used for generating and outputting the corresponding control signal according to the magnitude of the ith comparison code and the jth comparison code.
In some embodiments, the control signal generation circuit comprises an inverter and a signal generation circuit; the input end of the inverter is connected with the ith comparison code; the output end of the phase inverter is connected with the first input end corresponding to the signal generating circuit; the second input end corresponding to the signal generating circuit is connected with the jth comparison code; the output end corresponding to the signal generating circuit is connected with the control end corresponding to the data selector;
the phase inverter is used for carrying out phase inversion operation on the ith comparison code to obtain the ith comparison code after phase inversion;
and the signal generating circuit is used for generating the corresponding control signal output according to the magnitude of the ith comparison code and the jth comparison code after phase inversion.
In some embodiments, the 1 st to nth comparison codes are all m-bit binary codes; the signal generation circuit includes 1 st to mth sub-circuits; the first to third input ends of the (k + 1) th sub-circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1; the output end of the mth sub-circuit is connected with the control end corresponding to the data selector;
and the (k + 1) th sub-circuit is used for generating a corresponding control code output according to the (k + 1) th bit of the ith comparison code, the (k + 1) th bit of the jth comparison code and a comparison result of the control code output by the kth sub-circuit after phase inversion, wherein the control code of the mth sub-circuit is the corresponding control signal.
In some embodiments, the third input terminal of the 1 st sub-circuit is connected to a first level; the first level corresponds to binary code 1.
In some embodiments, the (k + 1) th sub-circuit is configured to generate a control code output at a preset level when the (k + 1) th bit of the i-th comparison code after inversion is the same as the (k + 1) th bit of the j-th comparison code and is at the preset level; and generating a control code output which is the same as the control code output by the kth sub-circuit under the condition that the (k + 1) th bit of the ith comparison code after inversion is different from the (k + 1) th bit of the jth comparison code.
In some embodiments, the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the first to third input ends of the first switching tube circuit and the first to third input ends of the second switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; a first common output end formed by connecting the output end of the first switching tube circuit and the output end of the second switching tube circuit is the output end of the (k + 1) th sub-circuit;
the preset level is a second level; the first switching tube circuit is used for generating a control code output of the second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the second level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at the second level; the second level corresponds to binary code 0;
the preset level is the first level; the second switching tube circuit is used for generating the control code output of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both the first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is the first level.
In some embodiments, the first switching tube circuit comprises a first sub-switching tube circuit and a second sub-switching tube circuit; first to third input ends of the first sub-switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in an output end of the phase inverter, a (k + 1) th bit in the jth comparison code and an output end of the kth sub-circuit; the output end of the first sub switching tube circuit is connected with the input end of the second sub switching tube circuit; the output end of the second sub switching tube circuit is the output end of the first switching tube circuit;
the first sub switching tube circuit is used for generating a control code output of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the second level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is at the second level;
the second sub switching tube circuit is used for responding to the input control code of the first level and generating the control code output of the second level.
In some embodiments, the second sub-switch tube circuit includes a first switch tube, a gate of the first switch tube is connected to the output terminal of the first sub-switch tube circuit, and a source of the first switch tube is connected to the second level; the drain electrode of the first switch tube is used as the output end of the second sub switch tube circuit;
the first switch tube is used for responding to the input control code of the first level to conduct the connection between the output end of the second sub switch tube circuit and the second level, so that the second sub switch tube circuit outputs the control code of the second level.
In some embodiments, the first sub-switching tube circuit comprises a first series switching tube circuit and a first parallel switching tube circuit; the first input end and the second input end of the first series switching tube circuit are respectively and correspondingly connected with the (k + 1) th port in the output end of the phase inverter and the (k + 1) th bit in the jth comparison code; the output end of the first series switching tube circuit is connected with a second common output end formed by the output ends of the first parallel switching tube circuits and is connected with the input end of the second sub switching tube circuit; the first to third input ends of the first parallel switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit;
the first series switching tube circuit is used for generating a control code output of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both the second level;
the first parallel switching tube circuit is used for generating and outputting the control code of the first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is the second level.
In some embodiments, the first series switching tube circuit comprises a first series branch formed by connecting a second switching tube and a third switching tube in series; the grid electrode, the source electrode and the drain electrode of the second switch tube are respectively and correspondingly connected with the (k + 1) th port in the output end of the phase inverter, the drain electrode of the third switch tube and the input end of the second sub switch tube circuit; the grid electrode of the third switching tube is connected with the (k + 1) th bit in the jth comparison code; the source electrode of the third switching tube is connected with the first level;
and the first serial branch circuit is used for conducting connection between the input end of the second sub-switching tube circuit and the first level to generate control code output of the first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both the second level.
In some embodiments, the first parallel switching tube circuit comprises a second series branch formed by connecting the first parallel branch and a sixth switching tube in series; the first parallel branch is formed by connecting a fourth switching tube and a fifth switching tube in parallel; the source electrodes of the fourth switching tube and the fifth switching tube are both connected with the first level; a first common node formed by connecting drain electrodes of the fourth switching tube and the fifth switching tube is connected with a source electrode of the sixth switching tube; the grids of the fourth to sixth switching tubes are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; the drain electrode of the sixth switching tube is connected with the input end of the second sub switching tube circuit;
and the second series branch is used for conducting connection between the input end of the second sub switching tube circuit and the first level to generate the control code output of the first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is the second level.
In some embodiments, the second switching tube circuit includes a third sub-switching tube circuit and a fourth sub-switching tube circuit, and first to third input terminals of the third sub-switching tube circuit are respectively connected to a (k + 1) th port in the output terminal of the inverter, a (k + 1) th bit in the jth comparison code, and an output terminal of the kth sub-circuit; the output end of the third sub switching tube circuit is connected with the input end of the fourth sub switching tube circuit; the output end of the fourth sub switching tube circuit is the output end of the second switching tube circuit;
the third sub switching tube circuit is used for generating a control code output of the second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is at the first level;
and the fourth sub switching tube circuit is used for responding to the input control code of the second level and generating the control code output of the first level.
In some embodiments, the fourth sub-switching tube circuit includes a seventh switching tube, a gate of the seventh switching tube is connected to the output terminal of the third sub-switching tube circuit, and a source of the seventh switching tube is connected to the first level; the drain electrode of the first switch tube is the output end of the fourth sub switch tube circuit;
the seventh switch tube is configured to switch on a connection between the output end of the fourth sub switch tube circuit and the first level in response to the input control code of the second level, so that the fourth sub switch tube circuit outputs the control code of the first level.
In some embodiments, the third sub-switch tube circuit comprises a second series switch tube circuit and a second parallel switch tube circuit; a first input end and a second input end of the second series switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter and a (k + 1) th bit in the jth comparison code; the output end of the second series switching tube circuit is connected with a third common output end formed by the output ends of the second parallel switching tube circuits and is connected with the input end of the fourth sub switching tube circuit; the first to third input ends of the second parallel switch tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit;
the second series switching tube circuit is used for generating a control code output of the second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both the first level;
and the second parallel switch tube circuit is used for generating and outputting the control code of the second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different, and the control code output by the kth sub-circuit is the first level.
In some embodiments, the second series switching tube circuit includes a third series branch formed by a series connection of an eighth switching tube and a ninth switching tube; a grid electrode, a drain electrode and a source electrode of the eighth switching tube are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, the input end of the fourth sub switching tube circuit and the drain electrode of the ninth switching tube; the source electrode of the ninth switching tube is connected with the second level; the grid electrode of the ninth switching tube is connected with the (k + 1) th bit in the jth comparison code;
and the third series branch is used for conducting connection between the input end of the fourth sub switching tube circuit and the second level to generate control code output of the second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both the first level.
In some embodiments, the second parallel switch tube circuit comprises a fourth series branch formed by connecting the second parallel branch and a twelfth switch tube in series; the second parallel branch is formed by connecting a tenth switching tube and an eleventh switching tube in parallel; the source electrodes of the tenth switching tube and the eleventh switching tube are both connected with the second level; a second common node formed by connecting the drains of the tenth switching tube and the eleventh switching tube is connected with the source of the twelfth switching tube; the grid electrodes of the tenth to twelfth switching tubes are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; the drain electrode of the twelfth switching tube is connected with the input end of the fourth sub switching tube circuit;
and the fourth serial branch is used for conducting connection between the input end of the fourth sub switching tube circuit and the second level to generate control code output of the second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is the first level.
In a second aspect, an embodiment of the present application further provides a comparison method, where the method includes:
the control signal generating circuit generates a corresponding control signal according to a comparison result of an ith comparison code and a jth comparison code in the 1 st to nth comparison codes and outputs the control signal to a corresponding data selector; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n;
the corresponding data selector responds to the corresponding control signal and selects to output the ith comparison code or the jth comparison code so as to realize comparison of the ith comparison code and the jth comparison code.
In a third aspect, an embodiment of the present application further provides a semiconductor memory, which includes the comparison circuit described in any one of the above.
In the embodiment of the application, the comparison circuit comprises at least one data selector and at least one control signal generation circuit corresponding to the at least one data selector, the control signal generation circuit generates a corresponding control signal according to a comparison result of the ith comparison code and the jth comparison code and outputs the control signal to the selection controller, and the selection controller responds to the corresponding control signal and selects and outputs the ith comparison code or the jth comparison code so as to realize comparison of the ith comparison code and the jth comparison code. Because the number of components of the comparison circuit mainly depends on the number of the switching tubes in the control signal generation circuit, the number of the switching tubes in the comparison circuit can be reduced under the condition that the switching tubes in the control signal generation circuit are small, and the circuit is simplified, so that the circuit complexity can be reduced.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
FIG. 1 is a schematic diagram illustrating a structure of a Dynamic Random Access Memory (DRAM) chip stack having a plurality of channels according to some embodiments;
FIG. 2 is a block diagram of a system architecture of a High Bandwidth Memory (HBM) Memory according to some embodiments;
FIG. 3 is a schematic diagram of a temperature sensor output temperature code of a single chip including four channels in some embodiments;
FIG. 4 is a target schematic diagram of a four temperature code comparison circuit in some embodiments;
FIG. 5a is a schematic diagram of a comparison circuit for two four-bit binary numbers according to some embodiments;
FIG. 5b is a schematic diagram of a specific circuit configuration of a two-input XNOR gate in some embodiments;
FIG. 5c is a schematic diagram of a specific circuit configuration of a two-input NOR gate in some embodiments;
FIG. 5d is a block diagram of a specific circuit configuration of a two-input NAND gate in some embodiments;
fig. 6 is a schematic structural diagram of a comparison circuit according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a comparison circuit when the number of comparison codes to be compared is odd according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a signal generating circuit in a case where the ith comparison code and the jth comparison code provided in the embodiment of the present application are both 8 bits;
fig. 9 is a schematic structural diagram of a control signal generating circuit of a first sub-comparing circuit for performing a first comparison between a first comparison code and a second comparison code in a comparing circuit for comparing 4 eight-bit binary comparison codes according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of a control signal generating circuit of a second sub-comparing circuit for performing a first comparison between a third comparison code and a fourth comparison code in a comparing circuit for comparing 4 eight-bit binary comparison codes according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of a control signal generating circuit of a third sub-comparing circuit for second comparison in a comparing circuit for comparing 4 eight-bit binary comparison codes according to an embodiment of the present application;
FIG. 12 is a schematic diagram illustrating a structure of a third sub-comparator for a second comparison in a comparator for comparing 4 eight-bit binary comparison codes according to an embodiment of the present application;
fig. 13 is a schematic structural diagram of a comparison unit circuit according to an embodiment of the present disclosure;
fig. 14 is a schematic implementation flow diagram of a comparison method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. It should be noted that, for the convenience of description, only the parts related to the related applications are shown in the drawings.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.
It should be noted that the terms "first \ second \ third" are used merely to distinguish similar objects and do not represent a specific ordering for the objects, and it should be understood that "first \ second \ third" may be interchanged under certain ordering or sequence if so permitted so that the embodiments of the present application described herein can be implemented in other orders than that shown or described herein.
HBM is a standardized stack storage technology that provides high bandwidth channels (channels) for data both within the stack and between storage and logic elements. In particular, the HBM employs stacking memory chips and stacking different memory chips through silicon vias to improve the speed and bandwidth of data transmission.
HBM DRAM is optimized for high bandwidth operation by stacking multiple DRAM chips through multiple independent interfaces called channels. It is expected that one DRAM chip can support up to 8 channels. FIG. 1 is a diagram of a DRAM chip stack with multiple channels in some embodiments, and as shown in FIG. 1, a DRAM chip stack 10 includes 4 DRAM chips, each of which supports 2 channels.
In fig. 1, a DRAM chip stack 10 includes first to fourth DRAM chips 101 to 104, a logic chip or base chip 105; therein, the first DRAM chip 101 includes channel 0 and channel 1.
Fig. 2 is a schematic diagram illustrating a system architecture of the HBM memory in some embodiments, as shown in fig. 2, the DRAM chips 201 to 204 and the logic chip 205 are independently connected to the microbumps 207 of the Silicon middle level (interface) 208 and the microbumps of the physical layer interface PHY 2051 in the logic chip 205 Through Silicon Vias (TSVs) 206 and microbumps (Micro-bumps) 207, so as to ensure that data in the DRAM stack is independently transmitted to the Silicon middle level 208 or the PHY 2051; in the silicon intermediate layer 208, individual data is transmitted to a Package board (Package Substrate)209 or PHY 2101 of the main chip 210 through a conductive wire (copper foil). Here, the main chip 210 is also packaged on a package board 209 through a silicon middle layer 208.
It is understood that the HBM needs to transmit data on the DRAM channel through the substrate channel, and therefore, in case that the HBM needs to detect a temperature value of each channel and output a maximum value of temperatures of all channels, in order to reduce the amount of transmitted data of the TSV, the maximum value of the temperature of each chip may be compared and then transmitted to the substrate channel.
In some possible embodiments, in order to compare the temperatures of the channels to obtain the maximum value of the temperatures, a relatively complex comparison circuit is required to implement. Here, since the temperature of the channel is an analog physical quantity that changes in real time, in order to compare the temperatures and determine the maximum value of the temperatures, analog-to-digital conversion needs to be performed on temperature data to obtain a binary temperature code.
FIG. 3 is a schematic diagram of the temperature code output by the temperature sensor of a single chip including four channels in some embodiments, as shown in FIG. 3, one temperature sensor is disposed for each of the four channels of the chip; wherein, the temperature sensor TS 0301 in the channel 0 outputs eight-bit binary temperature code temp _ code0<7:0 >; the temperature sensor TS 1302 in channel 1 outputs an eight-bit binary temperature code temp _ code1<7:0 >; the temperature sensor TS 2303 in channel 2 outputs an eight-bit binary temperature code temp _ code2<7:0 >; the temperature sensor TS 3304 in channel 3 outputs an eight-bit binary temperature code temp _ code3<7:0 >.
FIG. 4 is a target schematic diagram of a comparison circuit for four temperature codes according to some embodiments, and as shown in FIG. 4, four input terminals of the comparison circuit 40 for four binary temperature codes are temp _ code0<7:0>, temp _ code1<7:0>, temp _ code2<7:0> and temp _ code3<7:0>, respectively; the output terminals of the four binary temperature code comparison circuits 40 are MAXCODEdie 1<7:0>, that is, the maximum values among temp _ code0<7:0>, temp _ code1<7:0>, temp _ code2<7:0>, and temp _ code3<7:0 >.
FIG. 5a is a schematic diagram of a comparison circuit for two four-bit binary numbers according to some embodiments, such asShown in FIG. 5a, the binary number a 0 a 1 a 2 a 3 And b 0 b 1 b 2 b 3 The comparison circuit at least comprises four two-input same-or gates 501, a two-input or gate 502, a two-input nor gate 503 and five and gates 506 consisting of a two-input nand gate 504 and a not gate 505. Here, due to the binary number a 0 a 1 a 2 a 3 And b 0 b 1 b 2 b 3 The comparison circuit of (2) is a basic comparison circuit, and the composition of the comparison circuit of two four-bit binary numbers is not described in detail herein.
Fig. 5b is a schematic diagram of a specific circuit structure of a two-input exclusive nor gate in some embodiments, and as shown in fig. 5b, a two-input exclusive nor gate 501 includes 10 switching transistors. Here, the 10 switch tubes are all NMOS tubes; meanwhile, since the two-input exclusive nor circuit 501 is a basic circuit, a detailed description of a specific connection of the two-input exclusive nor circuit will not be given herein.
Fig. 5c is a schematic diagram of a specific circuit structure of a two-input nor gate in some embodiments, and as shown in fig. 5c, a two-input nor gate 503 includes 4 switching transistors. Here, two of the 4 switching tubes are PMOS tubes, and two are NMOS tubes; meanwhile, since the two-input nor gate circuit 503 is a basic circuit, a detailed description of the specific connection of the two-input nor gate circuit 503 will not be given here.
Fig. 5d is a schematic diagram of a specific circuit structure of a two-input nand gate in some embodiments, and as shown in fig. 5d, one two-input nand gate 504 includes 4 switching tubes. Here, the 4 switching tubes are all NMOS tubes; meanwhile, since the two-input nand circuit 504 is a basic circuit, the specific connection of the two-input nand circuit 504 will not be described in detail.
As can be seen from fig. 5a to 5d, in the above embodiment, the two four-bit binary comparison circuits at least include four two-input and or gates 501, one two-input or gate 502, one two-input nor gate 503, and five and gates 506 including one two-input nand gate 504 and a not gate 505, each two-input and or gate 501 includes 10 switching transistors, one two-input nor gate 503 includes 4 switching transistors, and each two-input nand gate 504 includes 4 switching transistors, so that the two four-bit binary comparison circuits require a large number of switching transistors, are relatively complex, and have relatively high cost.
In view of the above technical problem, the embodiment of the present application provides a comparison circuit, as shown in fig. 6, the comparison circuit 60 includes at least one data selector 601, at least one control signal generation circuit 602 corresponding to the at least one data selector 601;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding control signal generating circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the first input end and the second input end of the corresponding control signal generating circuit are correspondingly connected with the ith comparison code and the jth comparison code;
each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
and the corresponding control signal generating circuit is used for generating a corresponding control signal to output according to the comparison result of the ith comparison code and the jth comparison code.
In some possible embodiments, the data selector may be an alternative data selector.
It is understood that the 1 st to nth comparison codes may be n binary codes representing temperature values to be compared or other types of binary codes corresponding to information to be compared and output.
In some possible embodiments, the 1 st to nth comparison codes may be 1 st to nth temperature codes. In the case where n comparison codes are required to be compared and the data selectors are either one-out-of-two data selectors, the at least one data selector 601 includes n-1 data selectors. That is, in the case where the one-out-of-two data selector is selected to compare n comparison codes, n-1 one-out-of-two data selectors are required and n-1 comparisons are required.
For the implementation manner of performing the comparison n-1 times, exemplarily, the parity of n may be determined first, and when n is an even number, n binary codes are grouped pairwise for the first time and divided into n/2 groups; then, carrying out first comparison on two binary codes of each group in the n/2 groups grouped for the first time, outputting the maximum binary code of the binary codes of each group in the n/2 groups to obtain n/2 binary codes needing second comparison, then judging the parity of the n/2, and carrying out second pairwise grouping on the n/2 binary codes needing second comparison under the condition that the n/2 is an even number to divide the binary codes into n/4 groups; the two binary codes of each of the n/4 groups grouped a second time are then compared a second time … … until the largest binary code of the 1 st through nth comparison codes is obtained.
Of course, in the case that n is an odd number, the first n-1 binary codes may be divided into (n-1)/2 groups; and comparing the two binary codes of each group in the (n-1)/2 groups, outputting the maximum binary code of the binary codes in each group until the maximum code in the n-1 binary codes is compared, and comparing the maximum code in the n-1 binary codes with the nth comparison code to obtain the maximum comparison code in the n comparison codes.
Fig. 7 is a target schematic diagram of a comparison circuit in a case that the number of comparison codes to be compared is odd, as shown in fig. 7, the number of comparison codes to be compared is 5, and the number of bits of the comparison codes is 8; wherein 701 denotes a comparison circuit to which 4 comparison codes (Temp _ code0<7:0> to Temp _ code3<7:0>) are input; 702 denotes a comparator circuit which inputs 2 comparison codes; 701 (the maximum temperature code of Temp _ code0<7:0> to Temp _ code3<7:0>) as a first input to 702, and Temp _ code4<7:0> as a second input to 702, so that 702 can output the maximum temperature code MAXCoredie2<7:0> of Temp _ code0<7:0> to Temp _ code4<7:0 >. 703 denotes a comparison circuit to which 5 comparison codes (Temp _ code0<7:0> to Temp _ code4<7:0>) are input.
It can be seen that, the comparison circuit with the number of comparison codes to be compared being 5 can simply mix and superimpose the comparator circuit with the input of 2 comparison codes and the comparison circuit with the input of 4 comparison codes for use, and can realize the numerical comparison with any number.
In some possible embodiments, the ith comparison code and the jth comparison code may be any two comparison codes to be compared; the ith and jth comparison codes may be two comparison codes of the same group in the first or nth grouping.
In some possible embodiments, the control signal may be high level 1 or low level 0, and needs to be determined according to the comparison result of the ith comparison code and the jth comparison code.
In one embodiment, the corresponding control signal output is generated according to the comparison result of the ith comparison code and the jth comparison code, and a low level 0 output can be generated when the ith comparison code is larger than the jth comparison code; if the ith comparison code is less than the jth comparison code, a high level 1 output is generated.
In some possible embodiments, the data selector selects to output the ith comparison code or the jth comparison code in response to the corresponding control signal to implement the comparison between the ith comparison code and the jth comparison code, and may be configured to select to output the ith comparison code in response to a low level of 0 of the control signal and select to output the jth comparison code in response to a high level of 1 of the control signal.
In the embodiment of the application, the comparison circuit comprises at least one data selector and at least one control signal generation circuit corresponding to the at least one data selector, the control signal generation circuit generates a corresponding control signal according to a comparison result of an ith comparison code and a jth comparison code and outputs the control signal to the alternative selection controller, and the ith comparison code or the jth comparison code is selected and output in response to the corresponding control signal so as to realize comparison of the ith comparison code and the jth comparison code. Because the number of components of the comparison circuit mainly depends on the number of the switching tubes in the control signal generation circuit, the number of the switching tubes in the comparison circuit can be reduced under the condition that the switching tubes in the control signal generation circuit are small, the circuit is relatively simple, and the circuit complexity is reduced.
An embodiment of the present application further provides a comparison circuit, where the comparison circuit includes: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding signal generating circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the output end of the phase inverter is connected with the first input end of the corresponding signal generating circuit; the second input end of the corresponding signal generating circuit is connected with the jth comparison code;
each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the phase inverter is used for carrying out phase inversion operation on the ith comparison code to obtain the ith comparison code after phase inversion;
and the signal generating circuit is used for generating a corresponding control signal to output according to the comparison result of the ith comparison code and the jth comparison code after inversion.
In the embodiment of the application, the ith comparison code is subjected to phase inversion operation through an inverter in the control signal generation circuit to obtain the ith comparison code after phase inversion; the ith comparison code and the jth comparison code after the phase inversion are compared through a signal generation circuit to obtain a comparison result, and a control signal can be generated according to the comparison result to be output; the output control signal can enable the data selection selector to select the comparison code with the largest value in the codes to be compared and input by the output.
An embodiment of the present application further provides a comparison circuit, where the comparison circuit includes: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the first to third input ends of the (k + 1) th sub-circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1;
each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the phase inverter is used for carrying out phase inversion operation on the ith comparison code to obtain the ith comparison code after phase inversion;
and the (k + 1) th sub-circuit is used for generating a corresponding control code output according to the comparison result of the (k + 1) th bit of the ith comparison code, the (k + 1) th bit of the jth comparison code and the output code of the kth sub-circuit after inversion, wherein the control code of the mth sub-circuit is a corresponding control signal.
It is understood that m can be any positive integer greater than or equal to 2, and of course, needs to be determined or set according to the practical complexity of calculation. For example, m may be 4 or 8.
In the embodiment of the application, under the condition that the 1 st to nth comparison codes are m-bit binary codes, the signal generating circuit comprises 1 st to mth sub-circuits; and generating corresponding control code output through the (k + 1) th sub-circuit according to the (k + 1) th bit of the ith comparison code, the (k + 1) th bit of the jth comparison code and the comparison result of the control code output by the kth sub-circuit after inversion so as to realize the control of the data selector.
In some possible embodiments, the third input terminal of the 1 st sub-circuit is connected to the first level; the first level represents a binary code 1.
Here, the first level may be a high level, denoted by VDD, whose level size may be 15V.
Fig. 8 is a schematic diagram of a composition structure of a signal generating circuit in a case where the ith comparison code and the jth comparison code provided in the embodiment of the present application are both 8 bits, and as shown in fig. 8, the signal generating circuit 80 includes a 1 st sub-circuit 801 to an 8 th sub-circuit 808; the first to third ports of the 1 st sub-circuit 801 are respectively connected with the 1 st bit of the ith comparison code, the 1 st bit of the jth comparison code and the first level after inversion; the first to third ports of the 2 nd sub-circuit 802 are respectively and correspondingly connected with the 2 nd bit of the ith comparison code, the 2 nd bit of the jth comparison code and the output end of the 1 st sub-circuit 801; the circuit connections of the 3 rd sub-circuit 803 to the 8 th sub-circuit 808 are similar to the 2 nd sub-circuit 802. The control code generated by the 8 th sub-circuit 808 is the corresponding control signal.
In some possible embodiments, the (k + 1) th sub-circuit is configured to generate a control code output at a preset level when the (k + 1) th bit of the i-th comparison code after inversion is the same as the (k + 1) th bit of the j-th comparison code and is at the preset level; and generating a control code output which is the same as the control code output by the kth sub-circuit under the condition that the (k + 1) th bit of the ith comparison code after inversion is not the same as the (k + 1) th bit of the jth comparison code.
An embodiment of the present application further provides a comparison circuit, where the comparison circuit includes: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the first to third input ends of the first switching tube circuit and the first to third input ends of the second switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1; the output end of the first switching tube circuit is connected with the output end of the second switching tube circuit to form a first common output end which is the output end of the (k + 1) th sub-circuit;
each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first switching tube circuit is used for generating control code output of a second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at a second level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at a second level; the second level corresponds to binary code 0;
and the second switching tube circuit is used for generating control code output of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at the first level.
It is understood that the second level may be a low level, denoted by VSS, which may have a level of 0V.
In the embodiment of the application, a first switching tube circuit generates a control code of a second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the second level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at the second level; generating a control code of a first level by a second switching tube circuit under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at the first level; in this way, the corresponding control code may be generated according to the comparison result of the ith comparison code and the jth comparison code, so that the data selector may be controlled to select and output the corresponding comparison code by the generated control code.
An embodiment of the present application further provides a comparison circuit, including: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the first switching tube circuit comprises a first sub switching tube circuit and a second sub switching tube circuit;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the first to third input ends of the first sub-switching tube circuit and the first to third input ends of the second switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1; the output end of the first sub switching tube circuit is connected with the input end of the second sub switching tube circuit; the output end of the second sub switching tube circuit is the output end of the first switching tube circuit; (ii) a
Each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first sub switching tube circuit is used for generating a control code output of a first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at a second level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is at the second level;
the second sub switching tube circuit is used for responding to the input control code of the first level and generating a control code output of a second level;
and the second switching tube circuit is used for generating a control code output of a first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after inversion are the same and both are at the first level or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after inversion are different and the control code output by the kth sub-circuit is at the first level.
In the embodiment of the application, the first sub-switching tube circuit generates the control code of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the second level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-switching tube circuit is at the second level, and then converts the input first level into the second level to output through the second sub-switching tube circuit.
The embodiment of the present application provides another comparison circuit, where the comparison circuit includes: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the first switching tube circuit comprises a first sub switching tube circuit and a second sub switching tube circuit; the second sub-switching tube circuit comprises a first switching tube;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the first to third input ends of the first sub-switching tube circuit and the first to third input ends of the second switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1; the output end of the first sub switching tube circuit is connected with the grid electrode of the first switching tube; the source electrode of the first switching tube is connected with a second level; the drain electrode of the first switching tube is used as the output end of the second sub switching tube circuit;
each data selector is used for responding to the corresponding control signal and selectively outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first sub switching tube circuit is used for generating a control code output of a first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at a second level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is at the second level;
the first switching tube is used for responding to the input control code of the first level to conduct the connection between the output end of the second sub switching tube circuit and the second level, so that the second sub switching tube circuit outputs the control code of the second level;
and the second switching tube circuit is used for generating control code output of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at the first level.
Here, the first switch Transistor may be an N-type metal-Oxide-Semiconductor Field Effect Transistor (NMOSFET) NNOS Transistor.
It can be understood that, since the source of the first switch tube is connected to the second level, when the first switch tube is turned on, the source and the drain of the first switch tube are turned on, and therefore, the drain of the first switch tube is also connected to the second level, and when the drain of the first switch tube is the output end of the second sub-switch tube, the second sub-switch tube outputs the control code of the second level.
In the embodiment of the application, the connection between the output end of the second sub-switch tube circuit and the second level is conducted through the first switch tube in response to the control code of the first level, so that the first level of the input end can be converted into the second level to be output.
An embodiment of the present application additionally provides a comparison circuit, including: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the first switching tube circuit comprises a first sub switching tube circuit and a second sub switching tube circuit; the first sub-switch tube circuit comprises a first series switch tube circuit and a first parallel switch tube circuit;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the first to third input ends of the first parallel switching tube circuit and the first to third input ends of the second switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; the first input end and the second input end of the first series switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter and a (k + 1) th bit in the jth comparison code; k is any positive integer between 1 and m-1; the output end of the first series switching tube circuit is connected with a second common output end formed by the output ends of the first parallel switching tube circuits and is connected with the input end of the second sub switching tube circuit; the output end of the second sub switching tube circuit is the output end of the first switching tube circuit;
each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first series switching tube circuit is used for generating a control code output of a first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both at a second level;
the first parallel switching tube circuit is used for generating a control code output of a first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is of a second level;
the second sub switching tube circuit is used for responding to the input control code of the first level and generating a control code output of a second level;
and the second switching tube circuit is used for generating control code output of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at the first level.
It is understood that the first series switching tube circuit and the first parallel switching tube circuit are connected in parallel.
In the embodiment of the application, the control code of the first level is generated under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both the second level through the first series switching tube circuit; the method comprises the steps that a first parallel switch tube circuit is used for generating a control code output of a first level under the condition that the (k + 1) th bit of an ith comparison code and the (k + 1) th bit of a jth comparison code after phase inversion are different and the control code output by a kth sub-circuit is of a second level; thus, the control code of the first level can be generated under the condition of the (k + 1) th bit of the ith comparison code, the (k + 1) th bit of the jth comparison code and the output code of the kth sub-circuit after different inversions.
An embodiment of the present application provides another comparison circuit, including: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the first switching tube circuit comprises a first sub switching tube circuit and a second sub switching tube circuit; the first sub-switch tube circuit comprises a first series switch tube circuit and a first parallel switch tube circuit; the first series switching tube circuit comprises a first series branch formed by connecting a second switching tube and a third switching tube in series;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the phase inverter is connected with the ith comparison code; the first to third input ends of the first parallel switching tube circuit and the first to third input ends of the second switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; the grid electrode, the source electrode and the drain electrode of the second switch tube are respectively and correspondingly connected with the (k + 1) th port in the output end of the phase inverter, the drain electrode of the third switch tube and the input end of the second sub switch tube circuit; the grid electrode of the third switching tube is connected with the (k + 1) th bit in the jth comparison code; the source electrode of the third switching tube is connected with a first level; k is any positive integer between 1 and m-1; the output end of the first parallel switching tube circuit is connected with the input end of the second sub-switching tube circuit; the output end of the second sub switching tube circuit is the output end of the first switching tube circuit;
each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first serial branch circuit is used for conducting connection between the input end of the second sub-switching tube circuit and a first level to generate control code output of the first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both at a second level;
the first parallel switching tube circuit is used for generating a control code output of a first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is of a second level;
the second sub switching tube circuit is used for responding to the input control code of the first level and generating a control code output of a second level;
and the second switching tube circuit is used for generating a control code output of a first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after inversion are the same and both are at the first level or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after inversion are different and the control code output by the kth sub-circuit is at the first level.
In some possible embodiments, the second switching tube and the third switching tube may be both P-type metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) PNOS tubes.
In the embodiment of the application, the second switching tube and the third switching tube included in the first serial branch are enabled to correspondingly respond to the input of the gate, and under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both at the second level, the connection between the input end of the second sub switching tube circuit and the first level is conducted, and the control code output of the first level is generated.
The embodiment of the present application provides a further comparison circuit, and the comparison circuit includes: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the first switching tube circuit comprises a first sub switching tube circuit and a second sub switching tube circuit; the first sub-switch tube circuit comprises a first series switch tube circuit and a first parallel switch tube circuit; the first parallel switching tube circuit comprises a second series branch formed by connecting a first parallel branch and a sixth switching tube in series; the first parallel branch is formed by connecting the fourth switching tube and the fifth switching tube in parallel;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the first to third input ends of the second switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; the source electrodes of the fourth switching tube and the fifth switching tube are both connected with a first level; a first common node formed by connecting drain electrodes of the fourth switching tube and the fifth switching tube is connected with a source electrode of the sixth switching tube; the grids of the fourth to sixth switching tubes are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; the drain electrode of the sixth switching tube is connected with the input end of the second sub switching tube circuit;
the first input end and the second input end of the first series switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter and a (k + 1) th bit in the jth comparison code; k is any positive integer between 1 and m-1; the output end of the second sub-switching tube circuit is used as the output end of the first switching tube circuit, and a first public output end formed by connecting the output end of the first switching tube circuit with the output end of the second switching tube circuit is used as the output end of the (k + 1) th sub-circuit;
each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first series switching tube circuit is used for generating a control code output of a first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both at a second level;
the second series branch is used for conducting connection between the input end of the second sub switching tube circuit and the first level to generate control code output of the first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the output code of the kth sub circuit is the second level;
the second sub switching tube circuit is used for responding to the input control code of the first level and generating a control code output of a second level;
and the second switching tube circuit is used for generating control code output of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at the first level.
In the embodiment of the application, the second serial branch is used for conducting the connection between the input end of the second sub switching tube circuit and the first level to generate the control code output of the first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after inversion are different and the control code output by the kth sub circuit is of the second level.
An embodiment of the present application provides another comparison circuit, including: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the second switching tube circuit comprises a third sub switching tube circuit and a fourth sub switching tube circuit;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the first to third input ends of the third sub-switching tube circuit and the first to third input ends of the first switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1; the output end of the third sub switching tube circuit is connected with the input end of the fourth sub switching tube circuit; the output end of the fourth sub switching tube circuit is the output end of the second switching tube circuit;
each data selector is used for responding to the corresponding control signal and selectively outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first switching tube circuit is used for generating control code output of a second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at a second level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at a second level; the second level corresponds to binary code 0;
the third sub switching tube circuit is used for generating control code output of a second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at a first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is at the first level;
and the fourth sub switching tube circuit is used for responding to the input control code of the second level and generating the control code output of the first level.
In the embodiment of the application, the third sub-switching tube circuit generates the control code of the second level under the condition that the k +1 th bit of the i-th comparison code and the k +1 th bit of the j-th comparison code after phase inversion are the same and are both at the first level, or under the condition that the k +1 th bit of the i-th comparison code and the k +1 th bit of the j-th comparison code after phase inversion are different and the control code output by the k sub-circuit is at the first level, and then converts the input control code of the second level into the control code output at the first level through the fourth sub-switching tube circuit, so that the corresponding control code can be generated according to the comparison result of the i-th comparison code and the j-th comparison code, so that the data selector can be controlled to select and output the corresponding comparison code through the generated control code.
An embodiment of the present application provides another comparison circuit, including: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the second switching tube circuit comprises a third sub switching tube circuit and a fourth sub switching tube circuit; the fourth sub-switching tube circuit comprises a seventh switching tube;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the first to third input ends of the third sub-switching tube circuit and the first to third input ends of the first switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1; the output end of the third sub-switching tube circuit is connected with the grid electrode of the seventh switching tube; the source electrode of the seventh switching tube is connected with the first level; the drain electrode of the seventh switching tube is the output end of the fourth sub-switching circuit;
each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first switching tube circuit is used for generating and outputting a control code of a second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and both are at the second level or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at the second level; the second level corresponds to binary code 0;
the third sub switching tube circuit is used for generating control code output of a second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at a first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is at the first level;
and the seventh switch tube is used for responding to the input control code of the second level to switch on the connection between the output end of the fourth sub switch tube circuit and the first level, so that the fourth sub switch tube circuit outputs the control code of the first level.
Here, the seventh switching transistor may be a PMOS transistor.
In this embodiment, the seventh switching tube is used for responding to the connection between the output end of the fourth sub-switching tube circuit and the first level, so that the control code of the second level at the input end can be converted into the control code of the first level for output.
The embodiment of the present application further provides a comparison circuit, which includes: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the second switching tube circuit comprises a third sub switching tube circuit and a fourth sub switching tube circuit; the third sub-switch tube circuit comprises a second series switch tube circuit and a second parallel switch tube circuit;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the phase inverter is connected with the ith comparison code; the first to third input ends of the second parallel switch tube circuit and the first to third input ends of the first switch tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1; a first input end and a second input end of the second series switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter and a (k + 1) th bit in the jth comparison code; the output end of the second series switching tube circuit is connected with a third common output end formed by the output ends of the second parallel switching tube circuits and connected with the input end of the fourth sub switching tube circuit; the output end of the fourth sub switching tube circuit is the output end of the second switching tube circuit; each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first switching tube circuit is used for generating control code output of a second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at a second level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at a second level; the second level corresponds to binary code 0;
the second series switching tube circuit is used for generating control code output of a second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both at a first level;
the second parallel switch tube circuit is used for generating and outputting a control code of a second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is of a first level;
and the fourth sub switching tube circuit is used for responding to the input control code of the second level and generating the control code output of the first level.
It is understood that the second series switching tube circuit and the second parallel switching tube circuit are connected in parallel.
In the embodiment of the application, the control code of the second level is generated by the second series switching tube circuit under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both the first level; the control code output of a second level is generated under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is of a first level through a second parallel switch tube circuit; thus, the control code of the second level can be generated under the condition of the (k + 1) th bit of the ith comparison code, the (k + 1) th bit of the jth comparison code and the control code output by the kth sub-circuit after different inversions.
An embodiment of the present application further provides a comparison circuit, where the comparison circuit includes: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the second switching tube circuit comprises a third sub switching tube circuit and a fourth sub switching tube circuit; the third sub-switch tube circuit comprises a second series switch tube circuit and a second parallel switch tube circuit; the second series switching tube circuit comprises a third series branch formed by connecting an eighth switching tube and a ninth switching tube in series;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the first to third input ends of the second parallel switch tube circuit and the first to third input ends of the first switch tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1; the grid electrode, the drain electrode and the source electrode of the eighth switching tube are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, the input end of the fourth sub switching tube circuit and the drain electrode of the ninth switching tube; the source electrode of the ninth switching tube is connected with the second level; the grid electrode of the ninth switching tube is connected with the (k + 1) th bit in the jth comparison code;
the output end of the second parallel switch tube circuit is connected with the input end of the fourth sub switch tube circuit; the output end of the fourth sub switching tube circuit is the output end of the second switching tube circuit;
each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first switching tube circuit is used for generating and outputting a control code of a second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and both are at the second level or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at the second level; the second level corresponds to binary code 0;
the third series branch is used for conducting connection between the input end of the fourth sub switching tube circuit and the second level to generate control code output of the second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both the first level;
the second parallel switch tube circuit is used for generating control code output of a second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is of a first level;
and the fourth sub switching tube circuit is used for responding to the input control code of the second level and generating the control code output of the first level.
It is understood that the eighth switching tube and the ninth switching tube may be both NMOS tubes.
In this embodiment of the application, through the eighth switching tube and the ninth switching tube included in the second serial branch, the eighth switching tube and the ninth switching tube are enabled to respond to the input of the gate correspondingly, and under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and both are the first level, the connection between the input end of the fourth sub-switching tube circuit and the second level is conducted, and the second level control code output is generated.
An embodiment of the present application further provides a comparison circuit, where the comparison circuit includes: at least one data selector, at least one control signal generating circuit corresponding to the at least one data selector; the control signal generating circuit comprises an inverter and a signal generating circuit; the signal generating circuit includes 1 st to mth sub-circuits; the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the second switching tube circuit comprises a third sub switching tube circuit and a fourth sub switching tube circuit; the third sub-switch tube circuit comprises a second series switch tube circuit and a second parallel switch tube circuit; the second parallel switch tube circuit comprises a fourth series branch formed by connecting a second parallel branch and a twelfth switch tube in series; the second parallel branch is formed by connecting a tenth switching tube and an eleventh switching tube in parallel;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding mth sub-circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the input end of the inverter is connected with the ith comparison code; the first to third input ends of the first switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1;
the source electrodes of the tenth switching tube and the eleventh switching tube are both connected with a second level; a second common node formed by connecting the drains of the tenth switching tube and the eleventh switching tube is connected with the source of the twelfth switching tube; the grid electrodes of the tenth to twelfth switching tubes are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; the drain electrode of the twelfth switching tube is connected with the input end of the fourth sub switching tube circuit;
a first input end and a second input end of the second series switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter and a (k + 1) th bit in the jth comparison code; the output end of the second series switching tube circuit is connected with the input end of the fourth sub switching tube circuit; the output end of the fourth sub-switching tube circuit is used as the output end of the second switching tube circuit, and a first public output end formed by connecting the output end of the second switching tube circuit with the output end of the first switching tube circuit is the output end of the (k + 1) th sub-circuit;
each data selector is used for responding to the corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
the inverter is used for carrying out inversion operation on the ith comparison code to obtain an inverted ith comparison code;
the first switching tube circuit is used for generating control code output of a second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at a second level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at a second level; the second level corresponds to binary code 0;
the second series switching tube circuit is used for generating control code output of a second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both at a first level;
the fourth series branch is used for conducting connection between the input end of the fourth sub switching tube circuit and the second level to generate output code output of the second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is the first level;
and the fourth sub switching tube circuit is used for responding to the input control code of the second level and generating the control code output of the first level.
In the embodiment of the application, the fourth serial branch is connected between the input end of the fourth switching tube circuit and the second level to generate the control code output of the second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the output code of the kth sub-circuit is the first level.
Fig. 9 is a schematic structural diagram of a control signal generating circuit of a first sub-comparing circuit for performing a first comparison between a first comparison code and a second comparison code in a comparing circuit for comparing 4 eight-bit binary comparison codes according to an embodiment of the present application; as shown in fig. 9, the control signal generating circuit of the first sub-comparison circuit includes TS 901, TS 902, RS 903, RS 904, an inverter INV <7:0>905 and a first comparison unit circuit CMP0<7:0> 906;
wherein, TS 901 and TS 902 are the temperature sensor circuit in 0 th channel and 1 st channel in DRAM chip respectively; the temperature sensor circuit comprises a temperature sensor, and temperature information on a channel is sensed through the temperature sensor; the temperature sensor circuit also comprises an analog-to-digital conversion circuit, and the temperature information is subjected to analog-to-digital conversion through the analog-to-digital conversion circuit to obtain a temperature code;
RS 903 and RS 904 are eight-bit registers, and are respectively used for correspondingly storing a first temperature code temp _ code0 and a second temperature code temp _ code1 output by TS 901 and TS 902;
temp _ code0 and temp _ code1 which are correspondingly output by TS 901 and TS 902 are correspondingly stored by RS 903 and RS 904 respectively; the temp _ code0 stored and output by the RS 903 is subjected to inversion processing by an inverter 905 to obtain an inverted temp _ code0, and the inverted temp _ code0 is input to a first input end of a CMP0<7:0> 906; meanwhile, Temp _ code1 stored and output by RS 904 is input to a second input terminal of CMP0<7:0> 906; CMP0<7:0>906 outputs an eight-bit control signal T0<7:0 >; wherein, T0<6:0> is connected to the third input terminal of CMP0<7:0>906, T0<0> is fixedly connected to high level VDD; t0<7> is a control signal for the data selector that compares TS 901 and TS 902.
Fig. 10 is a schematic structural diagram of a control signal generating circuit of a second sub-comparing circuit for performing a first comparison between a third comparison code and a fourth comparison code in a comparing circuit for comparing 4 eight-bit binary comparison codes according to an embodiment of the present application; as shown in fig. 10, the control signal generating circuit of the second sub-comparing circuit includes TS 1001, TS 1002, RS 1003, RS 1004, inverter INV1<7:0>1005, and CMP1<7:0> 1006; since the control signal generating circuits of the second sub-comparison circuits in fig. 10 are identical in composition to the control signal generating circuits of the first sub-comparison circuits in fig. 9, the only difference is that fig. 10 is used to generate control signals for comparison of Temp _ code2 and Temp _ code 3; where T1<7> is a control signal of the data selector comparing TS 1001 and TS 1002.
Fig. 11 is a schematic structural diagram of a control signal generating circuit of a third sub-comparing circuit for second comparison in a comparing circuit for comparing 4 eight-bit binary comparison codes according to an embodiment of the present application; as shown in fig. 11, the control signal generating circuit of the third sub-comparison circuit includes a first one-out data selector MUX0<7:0>1101, a first inverter INV2<7:0>1102, a second one-out data selector MUX1<7:0>1103, and a third comparison unit circuit CMP <7:0> 1104;
wherein, a first input end and a second input end of MUX0<7:0>1101 are respectively connected with Temp _ code0 and Temp _ code1, a control end of MUX0<7:0>1101 is connected with an output T0<7> control signal in FIG. 9, MUX0<7:0>1101 outputs a maximum temperature signal MAX [ Temp _ code0, 1] in Temp _ code0 and Temp _ code1 to INV2<7:0>1102 in response to the T0<7> control signal; INV2<7:0>1102 inverts MAX [ Temp _ code0, 1] and inputs the inverted MAX [ Temp _ code0, 1] to a first input terminal of CMP <7:0> 1104;
a first input terminal and a second input terminal of MUX1<7:0>1103 are connected with Temp _ code2 and Temp _ code3, respectively, a control terminal of MUX1<7:0>1103 is connected with output T1<7> control signal in FIG. 10, MUX1<7:0>1103 outputs a maximum temperature signal MAX [ Temp _ code2, 3] in Temp _ code2 and Temp _ code3 to a second input terminal of CMP <7:0>1104 in response to T1<7> control signal; CMP <7:0>1104 outputs TM0<7:0 >; wherein, TM0<6:0> is connected with the third input terminal of CMP <7:0>1104, TM0<0> is fixedly connected with high level VDD; TM0<7> is a control signal for the data selector that compares MAX Temp _ code0, 1 with MAX Temp _ code2, 3.
FIG. 12 is a schematic diagram illustrating a structure of a third sub-comparator circuit for a second comparison in a comparator circuit for comparing 4 eight-bit binary comparison codes according to an embodiment of the present application, where the third sub-comparator circuit includes a third one-out-of-two data selector MUX2<7:0>1201 and an eight-bit register circuit RSM 1202, as shown in FIG. 12; wherein, the first input terminal, the second input terminal and the control terminal of MUX2<7:0>1201 are respectively connected to MAX [ Temp _ codeTemp _ code0, 1], MAX [ Temp _ code2, 3] and TM0<7> in FIG. 11; the MUX2<7:0>1201 outputs the maximum value among MAX [ Temp _ code0, 1] and MAX [ Temp _ code2, 3] in response to input MAX [ Temp _ code0, 1], MAX [ Temp _ code2, 3] and TM0<7>, and stores the maximum value through the RSM 1202 to obtain Maxcodedie3<7:0>, which is the maximum temperature value among the four temperature codes Temp _ code0 to Temp _ code 3.
Fig. 13 is a schematic diagram illustrating a structure of a comparison unit circuit according to an embodiment of the present disclosure, and as shown in fig. 13, a plurality of comparison unit circuits may be included in CMP0<7:0>906, CMP1<7:0>1006, or CMP <7:0>1104 in fig. 9 to 11; the number of the comparison unit circuits is determined according to the binary number of the comparison codes to be compared, for example, eight comparison unit circuits are required for eight-bit comparison codes (temperature codes), for example, CMP0<7:0>1106 includes first to eighth comparison unit circuits; the j comparison unit circuit is used for comparing j bits in Temp _ code0 and Temp _ code 1; j is a positive integer greater than 1 and equal to or less than 8.
The jth comparison unit circuit comprises a first PMOS transistor P0 to a sixth PMOS transistor P5, a first NMOS transistor N0 to a sixth NMOS transistor N5, a high level VDD and a low level VSS; the inputs of the jth compare unit circuit include A, B and VIN;
wherein A, B is the j-th bit in Temp _ code0 and Temp _ code1 respectively; VIN is connected to VDD in the 1 st bit (least significant bit), i.e., high level 1; and the control code output by the j-1 circuit is the VIN from the 2 nd bit to the 7 th bit.
The P0 and the P1 are connected in parallel to form a parallel branch L1; l1 is connected with P3 in series to form a series branch L2; a series branch L3 and L2 formed by connecting P2 and P4 in series are connected between VDD and the gate of P5 in parallel; the source of P5 is connected to VDD; the drain of the P5 is used as the output terminal VOUT of the jth comparison unit circuit; gate connections a for P0 and P4; gate connections B of P1 and P2; the gate of P3 is connected to VIN; the source of P3 is connected to the common node of the P0 and P1 drains; the sources of P0 and P1 are connected with VDD; the drain electrode of the P3 is connected with the drain electrode of the P4; the source of the P4 is connected with the drain of the P2;
n3 and N4 are connected in parallel to form a parallel branch L4; l4 is connected with N0 in series to form a series branch L5; a series branch L6 and L5 formed by connecting N1 and N5 in series are connected between VSS and the gate of N2 in parallel; the source of N2 is connected with VSS; the drain electrode of the N2 is connected with the drain electrode of the P5; gate connections a of N1 and N3; gate connections B of N4 and N5; the gate of N0 is connected to VIN; the source of N0 is connected with the common node of the N3 and the N4 drain; the sources of N3 and N4 are connected with VSS; the drain electrode of the N0 is connected with the drain electrode of the N1; the source of N1 is connected to the drain of N5.
In the comparison unit circuit, under the condition that A and B are the same, the output VOUT is the same as A or B (follows A or B); that is, A and B are 1 (or 0); vout is 1 (or 0);
in the case where a and B are not the same, VOUT follows VIN.
Meanwhile, as can be seen from fig. 9, due to the presence of the inverters INV <7:0>905, in the case that the j-th bits of the Temp _ code0 and Temp _ code1 are the same, and are both 0 or 1, the corresponding inputs a and B in the j-th comparison unit circuit are different, that is, the j-th comparison unit circuit output T0< j > follows VIN of the j-th comparison unit circuit; since VIN of the j-th comparison unit circuit is the output T0< j-1> of the j-th circuit, that is, T0< j > is T0< j-1 >.
In the case where the j-th bits of Temp _ code0 and Temp _ code1 are different, the corresponding inputs A and B in the j-th compare unit circuit are the same due to the presence of INV <7:0>905, i.e., the output T0< j > follows A or B.
On the basis of the above embodiments, the present application further provides a comparison method, as shown in fig. 14, the comparison method includes:
step S1401: the control signal generating circuit generates a corresponding control signal according to the magnitude of the ith comparison code and the jth comparison code in the 1 st to nth comparison codes and outputs the control signal to a corresponding data selector; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n;
step S1402: and the corresponding data selector responds to the corresponding control signal and selects and outputs the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code.
The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure may be combined arbitrarily without conflict to arrive at new method embodiments. Features disclosed in several of the product embodiments provided in this disclosure may be combined in any combination to yield new product embodiments without conflict. The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (18)

1. A comparison circuit is characterized by comprising at least one data selector and at least one control signal generation circuit corresponding to the at least one data selector;
the first input end and the second input end of each data selector are respectively and correspondingly connected with the ith comparison code and the jth comparison code in the 1 st to nth comparison codes; the control end of each data selector is connected with the output end of the corresponding control signal generating circuit; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n; the first input end and the second input end corresponding to the control signal generating circuit are correspondingly connected with the ith comparison code and the jth comparison code;
each data selector is used for responding to a corresponding control signal and selecting and outputting the ith comparison code or the jth comparison code so as to realize the comparison of the ith comparison code and the jth comparison code;
and the corresponding control signal generating circuit is used for generating corresponding control signal output according to the comparison result of the ith comparison code and the jth comparison code.
2. The comparison circuit according to claim 1, wherein the control signal generation circuit comprises an inverter and a signal generation circuit; the input end of the inverter is connected with the ith comparison code; the output end of the phase inverter is connected with the first input end corresponding to the signal generating circuit; the second input end corresponding to the signal generating circuit is connected with the jth comparison code; the output end corresponding to the signal generating circuit is connected with the control end corresponding to the data selector;
the phase inverter is used for carrying out phase inversion operation on the ith comparison code to obtain the ith comparison code after phase inversion;
and the signal generating circuit is used for generating corresponding control signal output according to the comparison result of the ith comparison code and the jth comparison code after phase inversion.
3. The comparison circuit according to claim 2, wherein the 1 st to nth comparison codes are each an m-bit binary code; the signal generation circuit includes 1 st to mth sub-circuits; the first to third input ends of the (k + 1) th sub-circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; k is any positive integer between 1 and m-1; the output end of the mth sub-circuit is connected with the control end corresponding to the data selector;
and the (k + 1) th sub-circuit is used for generating a corresponding control code output according to the (k + 1) th bit of the ith comparison code, the (k + 1) th bit of the jth comparison code and a comparison result of the control code output by the kth sub-circuit after phase inversion, wherein the control code of the mth sub-circuit is the corresponding control signal.
4. The comparison circuit of claim 3 wherein the third input of the 1 st sub-circuit is connected to a first level; the first level corresponds to binary code 1.
5. The comparison circuit according to claim 4, wherein the (k + 1) th sub-circuit is configured to generate a control code output of a preset level when the (k + 1) th bit of the i-th comparison code after inversion is the same as the (k + 1) th bit of the j-th comparison code and is a preset level; and generating a control code output which is the same as the control code output by the kth sub-circuit under the condition that the (k + 1) th bit of the ith comparison code after inversion is different from the (k + 1) th bit of the jth comparison code.
6. The comparison circuit of claim 5, wherein the (k + 1) th sub-circuit comprises a first switching tube circuit and a second switching tube circuit; the first to third input ends of the first switching tube circuit and the first to third input ends of the second switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; a first common output end formed by connecting the output end of the first switching tube circuit and the output end of the second switching tube circuit is the output end of the (k + 1) th sub-circuit;
the preset level is a second level; the first switching tube circuit is used for generating a control code output of the second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and both are at the second level or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is at the second level; the second level corresponds to binary code 0;
the preset level is the first level; the second switching tube circuit is used for generating the control code output of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both the first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is the first level.
7. The comparator circuit of claim 6, wherein the first switching tube circuit comprises a first sub switching tube circuit and a second sub switching tube circuit; first to third input ends of the first sub-switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in an output end of the phase inverter, a (k + 1) th bit in the jth comparison code and an output end of the kth sub-circuit; the output end of the first sub switching tube circuit is connected with the input end of the second sub switching tube circuit; the output end of the second sub switching tube circuit is the output end of the first switching tube circuit;
the first sub switching tube circuit is used for generating a control code output of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and both are at the second level or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and a control code output by the kth sub circuit is at the second level;
the second sub-switching tube circuit is used for responding to the input control code of the first level and generating the control code output of the second level.
8. The comparison circuit as claimed in claim 7, wherein the second sub-switch tube circuit comprises a first switch tube, a gate of the first switch tube is connected to the output terminal of the first sub-switch tube circuit, and a source of the first switch tube is connected to the second level; the drain electrode of the first switch tube is used as the output end of the second sub switch tube circuit;
the first switch tube is used for responding to the input control code of the first level to conduct the connection between the output end of the second sub switch tube circuit and the second level, so that the second sub switch tube circuit outputs the control code of the second level.
9. The comparator circuit of claim 7, wherein the first sub-switch tube circuit comprises a first series switch tube circuit and a first parallel switch tube circuit; the first input end and the second input end of the first series switching tube circuit are respectively and correspondingly connected with the (k + 1) th port in the output end of the phase inverter and the (k + 1) th bit in the jth comparison code; the output end of the first series switching tube circuit is connected with a second common output end formed by the output ends of the first parallel switching tube circuits and is connected with the input end of the second sub switching tube circuit; the first to third input ends of the first parallel switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit;
the first series switching tube circuit is used for generating a control code output of the first level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both the second level;
the first parallel switching tube circuit is used for generating and outputting the control code of the first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub-circuit is the second level.
10. The comparison circuit as claimed in claim 9, wherein the first series switching tube circuit comprises a first series branch formed by a second switching tube and a third switching tube connected in series; the grid electrode, the source electrode and the drain electrode of the second switch tube are respectively and correspondingly connected with the (k + 1) th port in the output end of the phase inverter, the drain electrode of the third switch tube and the input end of the second sub switch tube circuit; the grid electrode of the third switching tube is connected with the (k + 1) th bit in the jth comparison code; the source electrode of the third switching tube is connected with the first level;
and the first serial branch circuit is used for conducting connection between the input end of the second sub-switching tube circuit and the first level to generate control code output of the first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both the second level.
11. The comparison circuit as claimed in claim 9, wherein the first parallel switching tube circuit comprises a second series branch formed by a first parallel branch connected in series with a sixth switching tube; the first parallel branch is formed by connecting a fourth switching tube and a fifth switching tube in parallel; the source electrodes of the fourth switching tube and the fifth switching tube are both connected with the first level; a first common node formed by connecting drain electrodes of the fourth switching tube and the fifth switching tube is connected with a source electrode of the sixth switching tube; the grids of the fourth to sixth switching tubes are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; the drain electrode of the sixth switching tube is connected with the input end of the second sub switching tube circuit;
and the second series branch is used for conducting connection between the input end of the second sub switching tube circuit and the first level to generate the control code output of the first level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is the second level.
12. The comparison circuit according to claim 6, wherein the second switching tube circuit comprises a third sub-switching tube circuit and a fourth sub-switching tube circuit, and first to third input terminals of the third sub-switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output terminal of the inverter, a (k + 1) th bit in the jth comparison code and an output terminal of the kth sub-circuit; the output end of the third sub switching tube circuit is connected with the input end of the fourth sub switching tube circuit; the output end of the fourth sub switching tube circuit is the output end of the second switching tube circuit;
the third sub switching tube circuit is used for generating a control code output of the second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both at the first level, or under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is at the first level;
the fourth sub switching tube circuit is used for responding to the input control code of the second level and generating the control code output of the first level.
13. The comparison circuit as claimed in claim 12, wherein the fourth sub-switching tube circuit comprises a seventh switching tube, a gate of the seventh switching tube is connected to the output terminal of the third sub-switching tube circuit, and a source of the seventh switching tube is connected to the first level; the drain electrode of the first switch tube is the output end of the fourth sub switch tube circuit;
the seventh switch tube is configured to switch on a connection between the output end of the fourth sub switch tube circuit and the first level in response to the input control code of the second level, so that the fourth sub switch tube circuit outputs the control code of the first level.
14. The comparison circuit as claimed in claim 12, wherein the third sub-switch tube circuit comprises a second series switch tube circuit and a second parallel switch tube circuit; a first input end and a second input end of the second series switching tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter and a (k + 1) th bit in the jth comparison code; the output end of the second series switching tube circuit is connected with a third common output end formed by the output ends of the second parallel switching tube circuits and is connected with the input end of the fourth sub switching tube circuit; the first to third input ends of the second parallel switch tube circuit are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit;
the second series switching tube circuit is used for generating a control code output of the second level under the condition that the k +1 th bit of the ith comparison code and the k +1 th bit of the jth comparison code after phase inversion are the same and are both the first level;
and the second parallel switch tube circuit is used for generating and outputting the control code of the second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different, and the control code output by the kth sub-circuit is the first level.
15. The comparison circuit as claimed in claim 14, wherein the second series switching tube circuit comprises a third series branch formed by a eighth switching tube and a ninth switching tube connected in series; a grid electrode, a drain electrode and a source electrode of the eighth switching tube are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, the input end of the fourth sub switching tube circuit and the drain electrode of the ninth switching tube; the source electrode of the ninth switching tube is connected with the second level; the grid electrode of the ninth switching tube is connected with the (k + 1) th bit in the jth comparison code;
and the third series branch is used for conducting connection between the input end of the fourth sub switching tube circuit and the second level to generate control code output of the second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are the same and are both the first level.
16. The comparison circuit as claimed in claim 14, wherein the second parallel switch tube circuit comprises a fourth series branch formed by the second parallel branch and a twelfth switch tube in series; the second parallel branch is formed by connecting a tenth switching tube and an eleventh switching tube in parallel; the source electrodes of the tenth switching tube and the eleventh switching tube are both connected with the second level; a second common node formed by connecting the drains of the tenth switching tube and the eleventh switching tube is connected with the source of the twelfth switching tube; the grid electrodes of the tenth to twelfth switching tubes are respectively and correspondingly connected with a (k + 1) th port in the output end of the phase inverter, a (k + 1) th bit in the jth comparison code and the output end of the kth sub-circuit; the drain electrode of the twelfth switching tube is connected with the input end of the fourth sub switching tube circuit;
and the fourth serial branch is used for conducting connection between the input end of the fourth sub switching tube circuit and the second level to generate control code output of the second level under the condition that the (k + 1) th bit of the ith comparison code and the (k + 1) th bit of the jth comparison code after phase inversion are different and the control code output by the kth sub circuit is the first level.
17. A method of comparison, the method comprising:
the control signal generating circuit generates a corresponding control signal according to a comparison result of an ith comparison code and a jth comparison code in the 1 st to nth comparison codes and outputs the control signal to a corresponding data selector; n is a positive integer greater than or equal to 2; i and j are different and are positive integers less than or equal to n;
the corresponding data selector responds to the corresponding control signal and selects to output the ith comparison code or the jth comparison code so as to realize comparison of the ith comparison code and the jth comparison code.
18. A semiconductor memory characterized by comprising the comparison circuit according to any one of claims 1 to 16.
CN202210724969.8A 2022-06-23 2022-06-23 Comparison circuit, comparison method and semiconductor memory Pending CN115001461A (en)

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CN202210724969.8A CN115001461A (en) 2022-06-23 2022-06-23 Comparison circuit, comparison method and semiconductor memory

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CN202210724969.8A CN115001461A (en) 2022-06-23 2022-06-23 Comparison circuit, comparison method and semiconductor memory

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CN115001461A true CN115001461A (en) 2022-09-02

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