CN115001454A

CN115001454A - Duty ratio regulator

Info

Publication number: CN115001454A
Application number: CN202210849633.4A
Authority: CN
Inventors: 赖荣钦
Original assignee: Dongxin Semiconductor Co ltd
Current assignee: Dongxin Semiconductor Co ltd
Priority date: 2022-07-19
Filing date: 2022-07-19
Publication date: 2022-09-02
Also published as: WO2024016951A1

Abstract

The invention relates to a duty cycle adjuster, comprising: a first duty cycle adjusting DCA module comprising M parallel adjusting units, each adjusting unit comprising a NOR gate and a PMOS transistor, each adjusting unit configured to: the timing delay of the input to the nor gate from the low level to the high level causes the PMOS to be opened at a rising edge of a signal, so that the PMOS delays the rising edge of the signal to reduce the duty cycle of the signal; and the timing delay of the transition from the high level to the low level input to the nor gate causes the PMOS not to be turned on at the falling edge of the signal, so that the PMOS does not change the falling edge of the signal.

Description

Duty ratio regulator

Technical Field

The present invention relates to the field of semiconductor devices, and more particularly, to a duty cycle adjuster.

Background

For some semiconductor devices, there may be a need to adjust the duty cycle. In some cases it may be desirable to adjust only the rising edge, while the falling edge remains unchanged.

For example, for DDR5, the bidirectional data control pin (DQS) internal clock duty cycle may be adjusted according to section 4.41 of JEDEC (solid state electronics Association) JESD79-5A specification standard, as an example. However, duty cycle adjustment may affect tDQSCK timing, which is undesirable.

Disclosure of Invention

The invention relates to a duty cycle adjuster, comprising: a first duty cycle adjusting DCA module comprising M parallel adjusting units, each adjusting unit comprising a NOR gate and a PMOS transistor, each adjusting unit configured to: the timing delay of the transition from low to high input to the nor gate causes the PMOS to be opened on the rising edge of the signal, whereby the PMOS delays the rising edge of the signal to reduce the duty cycle of the signal; and the timing delay of the transition from high to low input to the nor gate causes the PMOS to not be turned on the falling edge of the signal so that the PMOS does not change the falling edge of the signal, and/or a second duty cycle adjustment DCA module comprising N parallel adjustment units, each adjustment unit comprising a nor gate and an NMOS transistor, each adjustment unit configured to: the timing delay of the transition from the low level to the high level input to the nor gate causes the NMOS to be turned on at a rising edge of a signal, so that the NMOS advances the rising edge of the signal to increase the duty ratio of the signal; and the timing delay of the transition from the high level to the low level input to the nor gate causes the NMOS not to be turned on at the falling edge of the signal, so that the NMOS does not change the falling edge of the signal.

The duty cycle adjuster as described above, the gate of the PMOS coupled to the output of the nor gate, the drain of the PMOS coupled to the input signal whose duty cycle is to be adjusted, the source of the PMOS coupled to the power supply, and/or the gate of the NMOS coupled to the output of the nor gate, the drain of the NMOS coupled to the input signal whose duty cycle is to be adjusted, the source of the NMOS coupled to ground.

The duty cycle adjuster as described above, in the first DCA module, an inverter is included between the nor gate and the PMOS.

As described above, the input signal passes through an inverter before being input to the drain of the NMOS or PMOS, and the final output signal of the duty cycle adjuster includes an inverter before.

The duty cycle regulator as described above, the nor gate of each regulating unit includes an inverter on the first input line; the first input of the NOR gate of each adjusting unit is high level or low level, when the first input is high level, the high level controls the adjusting unit to be in an active state, and when the first input is low level, the low level controls the adjusting unit to be in an inactive state; the second input line of the nor gate of each regulating unit comprises a delay device such that the second input of the nor gate of each regulating unit is a delayed input signal and wherein the state of each regulating unit is independently controllable.

The duty cycle adjuster as described above, wherein the delay amount generated by the delay device on the input signal is set as: at least the entire rising edge of the signal whose duty cycle is to be adjusted is made to fall in the low level region of the delayed input signal and, correspondingly, the entire falling edge of the signal whose duty cycle is to be adjusted is made to fall in the high level region of the delayed input signal.

The duty cycle adjuster as described above, which is provided in a Delay Locked Loop (DLL) circuit, the change of the rising edge is made during DLL locking.

The duty cycle adjuster as described above, which is disposed after the MIMIC circuit in the DLL circuit.

The duty cycle adjuster as described above, when the duty cycle adjuster includes both the first DCA module and the second DCA module, the first DCA module and the second DCA module are connected in parallel.

For duty cycle regulators as described above, M is equal to N.

The duty cycle adjuster as described above includes a duty cycle adjuster for the internal clock of the DDR5 four-phase bidirectional data control pin DQS.

The duty cycle adjuster as described above, the number of the duty cycle adjusters comprising four, each phase of the four-phase signal being independently adjusted by the respective duty cycle adjuster, each duty cycle adjuster comprising the first DCA module and the second DCA module in parallel; a duty cycle adjuster for a first phase of the four-phase signal does not vary a duty cycle of the first phase; respective duty cycle adjusters for second, third and fourth phases of the four-phase signal independently adjust duty cycles of the second, third and fourth phases.

The duty cycle adjusters as described above, in each of which the first DCA module includes 7 adjusting units and the second DCA module includes 7 adjusting units; and the duty cycle adjuster is configured to: using a mode register MR43OP [2:0] to specify steps of the second phase duty cycle adjustment, and MR43OP [3] to specify the positive or negative sign of the steps, and the steps include 14 steps-7 to + 7; using mode register MR43OP [6:4] to specify steps of the third phase duty cycle adjustment, and MR43OP [7] to specify the positive or negative sign of the steps, and the steps include 14 steps-7 to + 7; the pattern register MR44 OP [2:0] is used to specify the steps of the fourth phase duty cycle adjustment, and MR44 OP [3] is used to specify the positive or negative sign of the steps, and the steps include 14 steps from-7 to + 7.

As with the duty cycle regulators described above, 14 steps are achieved by using different state combinations of 14 regulating units in parallel.

The duty cycle adjusters as described above, the first DCA module of each duty cycle adjuster is adapted to perform steps +1 to +7, the second DCA module is configured to perform steps-1 to-7, and wherein steps +1 to +7 are respectively valid for 1 to 7 of the 7 adjustment units in the first DCA module, and steps-1 to-7 are respectively valid for 1 to 7 of the 7 adjustment units in the second DCA module.

The duty ratio regulator as described above has a regulation range of 2ps to 4ps per step, and a total regulation range of 28ps to 56ps for 14 steps.

The duty cycle adjuster as described above is provided in a Delay Locked Loop (DLL) circuit comprising a frequency divider configured to divide a four-phase input signal into first, second, third and fourth phases differing by pi/2 between adjacent phases.

The invention also relates to a Delay Locked Loop (DLL) circuit comprising a duty cycle adjuster as claimed in any one of the preceding claims.

Drawings

To further clarify embodiments of the present invention, a more particular description of embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope as claimed.

Further, it should be understood that the primary connections of the various components are illustrated in the drawings, and not all connections are illustrated. Also, for the purpose of explaining the technical aspects of the present invention, the accompanying drawings show exemplary components. More or fewer components may be included in a practical application.

FIG. 1 is a schematic diagram of duty cycle regulation of a four-phase signal;

FIG. 2 is a schematic diagram showing the range and steps of duty cycle adjustment;

3a-3b are schematic diagrams of an adjustment unit of a first Duty Cycle Adjustment (DCA) module for increasing a duty cycle of a signal and timing diagrams thereof;

FIGS. 4a-4b are schematic diagrams of a second DCA module's regulation unit for reducing the duty cycle of a signal and timing diagrams thereof;

FIG. 5 is a circuit schematic of a duty cycle adjuster capable of increasing and decreasing the duty cycle of a signal;

6a-6b are schematic diagrams of a Delay Locked Loop (DLL) circuit including a duty cycle adjuster and timing diagrams of output signals of the duty cycle adjuster circuit; and is

Fig. 7 is a schematic diagram of the correspondence between mode register control bits and steps for duty cycle adjustment and control signals received by each adjustment unit in the DDR5 application scenario of the present invention.

Detailed Description

The following detailed description refers to the accompanying drawings. The drawings show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. It is to be understood that the following detailed description is intended for purposes of illustration, and is not to be construed as limiting the invention; those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope and spirit of the claimed subject matter.

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of various described embodiments. It will be apparent, however, to one skilled in the art that the various embodiments described may be practiced without these specific details. Unless defined otherwise, technical and scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

The terms "first," "second," and the like in the description and in the claims of the present application do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. An embodiment is an example implementation or example. Reference in the specification to "an embodiment," "one embodiment," "some embodiments," "various embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the technology. The various appearances "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. Elements or aspects from one embodiment may be combined with elements or aspects of another embodiment.

One embodiment of the invention is directed to a duty cycle adjuster including a first DCA module. The first DCA module may include M parallel regulating units. Each of the adjusting units may include a nor gate and a PMOS transistor. Each adjustment unit may be configured for: the timing delay of the transition from low to high input to the nor gate causes the PMOS to be turned on at the rising edge of the signal, so that the PMOS delays the rising edge of the signal to reduce the duty cycle of the signal; and the timing delay of the transition from high to low input to the nor gate causes the PMOS not to be turned on at the falling edge of the signal so that the PMOS does not change the falling edge of the signal.

Another embodiment of the invention is directed to a duty cycle adjuster that includes a second DCA module. The second DCA module may include N parallel regulating units. Each of the adjusting units may include a nor gate and an NMOS transistor. Each adjustment unit may be configured for: the timing delay of the transition from the low level to the high level input to the nor gate causes the NMOS to be turned on at the rising edge of the signal, so that the NMOS advances the rising edge of the signal to increase the duty ratio of the signal; and the timing delay of the transition from the high level to the low level input to the nor gate causes the NMOS not to be turned on at the falling edge of the signal so that the NMOS does not change the falling edge of the signal.

Yet another embodiment of the present invention may relate to a duty cycle adjuster including the first DCA module and the second DCA module described above. The first DCA module and the second DCA module may be connected in parallel to enable both an increase in duty cycle and a decrease in duty cycle, as described in more detail below.

In the scheme of the invention, only the rising edge of the signal is changed, and the falling edge of the signal is not changed. This is consistent with the relevant provisions for DDR5 four-phase DQS internal clock duty cycle adjustment. In a more preferred embodiment, the duty cycle adjuster of the present invention may be provided in a Delay Locked Loop (DLL) circuit, and the duty cycle may be adjusted after DLL locking. Therefore, the scheme of the present invention does not change tDQSCK timing.

In the following description, a detailed description of the technical solution of the present invention is mainly made with respect to DDR 5. However, it should be understood that the present technique for duty cycle adjustment is not limited to use with only DDR 5. The technical scheme of the invention can be used in any use situation requiring duty ratio adjustment. In particular, the techniques of the present application are more beneficial in situations where it is desirable to adjust the rising edge while the falling edge remains unchanged.

For DDR5, a DDR5 duty cycle regulator may be applied in a bidirectional data control pin (DQS) clock tree according to section 4.41 of the JEDEC (solid State electronics Association) JESD79-5A specification standard. Different mode register definitions may be used for single and multi-phase DQS internal clocks. For example, mode register MR43OP [3:0] may be used for single phase DQS internal clocking, while MR43OP [7:0] or MR44 OP [3:0] may be used for multi-phase DQS internal clocking. When applied to DDR5, the present invention is primarily directed to duty cycle adjustment of a four-phase DQS internal clock, which may include: ICLK (0 °), QCLK (90 °), IBCLK (180 °), and QBCLK (270 °), as described in the DDR5 specification. The duty cycle adjustments for QCLK, IBCLK and QBCLK may be as shown in fig. 1. Wherein an increase of the DCA code corresponds to a delay of the rising edge (respectively, a decrease of the duty cycle) and a decrease of the DCA code corresponds to an advance of the rising edge (respectively, an increase of the duty cycle) since the rising edge is adjusted. Further, for some applications, the duty cycle adjustment techniques of the present invention may be used to adjust the three clock signals QCLK (90), IBCLK (180), and QBCLK (270), while ICLK (0) may remain unchanged. As described above, for the four-phase DQS of DDR5, the duty cycle adjustment circuit only changes the rising edge of the signal, and does not change the falling edge of the signal.

As shown in connection with fig. 2, duty cycle step adjustments from-7 to +7 may be specified by mode registers MR43 and MR44, respectively. For example, for duty cycle adjustment of QCLK, MR43OP [2:0] may be used to specify the steps of the duty cycle adjustment and OP [3] may be used to specify the positive or negative sign of the steps. For duty cycle adjustment of IBCLK, MR43OP [6:4] can be used to specify the steps of the duty cycle adjustment, and MR43OP [7] can specify the positive or negative sign of the steps. For duty cycle adjustment of QBCLK, MR44 OP [2:0] may be used to specify the steps of the duty cycle adjustment and MR44 OP [3] may be used to specify the positive or negative sign of the steps. In general, circuit design is subject to JEDEC specification requirements.

The DQS duty cycle adjustment may be ahead of the DQS clock tree or equivalent location. Duty cycle adjustment requires a locked DLL state and will affect the DQS and DQ duty cycles in the following operations:

a) reading;

b) read Preamble (Preamble) training;

c) reading a training mode;

d) the mode register is read.

In a scheme where the DQS clock tree uses four-phase clocks, the odd and even duty cycles of all DQS for each device may be adjusted accordingly, since the internal four-phase clock may be independently controlled by the DCA code.

Referring again to FIG. 2, the rising edge of the pulse signal is adjusted for the four-phase DQS of DDR 5. In the duty cycle adjustment of QCLK, IBCLK and QBCLK, there may be 7 steps for positive and negative adjustments, respectively. Thus, a total of 14 steps may be included. In the present invention, the regulation range for each step may be about 2ps-4ps, and thus, the total duty cycle regulation range for 14 steps may be about 28ps-56 ps.

Fig. 3a-3b are schematic diagrams of a regulating unit of the first DCA module for reducing the duty cycle of a signal and a timing diagram thereof. Each of the adjustment units may include a nor gate 302 and a PMOS transistor 306. As with the timing diagram of fig. 3b, the main design idea of this embodiment is that each adjustment unit may be configured to: the timing delay of the transition from low to high input to nor gate 302 causes PMOS306 to be turned on the rising edge of the signal (i.e., the drive current of PMOS306 is active) so that PMOS306 delays the rising edge of the signal to reduce the duty cycle of the signal; and the timing delay of the transition from high to low input to nor gate 302 causes PMOS306 not to be turned on at the falling edge of the signal (i.e., the drive current of PMOS306 is disabled) so that PMOS306 does not change the falling edge of the signal.

The first input of the nor gate 302 of each adjustment unit may be high or low. When the first input is high (e.g., C _ U <0> ═ H as shown in fig. 3 a), the high level may control the regulating unit to be in an active state, i.e., enable the regulating unit. When the first input is low (e.g., C _ U <0> ═ L), the low level may control the regulation unit to be in an inactive state, i.e., not to enable the regulation unit. It should be noted that due to the operational characteristics of the nor gate, an inverter 314 may be added to the first line in order to achieve the above control effect. A delay device 308 may be included on the second input line of the nor gate 302 of each of the conditioning cells such that the second input of the nor gate 302 of each of the conditioning cells is a delayed input signal. For example, IN connection with fig. 3b, the second input of the nor gate 302 may be the delayed input signal IN _ D.

IN an embodiment of the present invention, as shown IN conjunction with the timing diagram of FIG. 3b, the amount of delay generated by delay device 308 on input signal IN may be set as: at least the entire rising edge of the signal whose duty cycle is to be adjusted (which may be, for example, the input signal IN or, if an inverter 310 is used, the input signal IN after passing the inverter 310) is caused to fall IN the low-level region of the timing delayed signal IN _ D (as indicated by the shape "|" on the left side of fig. 3 b), and correspondingly, the entire falling edge of the signal whose duty cycle is to be adjusted at least falls IN the high-level region of the timing delayed signal IN _ D (as indicated by the shape "|" on the right side of fig. 3 b). Two delay devices 208, which may be buffers, are shown in fig. 3 b. This is, however, exemplary only and not limiting. Other numbers and/or types of delay devices may be provided based on the above delay amount setting requirements.

The gate (G) of PMOS306 may be coupled to the output of nor gate 302. The drain (D) of PMOS306 may be coupled to the input signal whose duty cycle is to be adjusted. The input signal whose duty ratio is to be adjusted may be, for example, the signal IN, or an IN signal (similar to OUT) having a certain phase delay after passing through the inverter 310, and the inverter 310 may be added due to the operating characteristics of PMOS. The source (S) of PMOS306 may be coupled to a power supply. As described above, the input signal IN may pass through the inverter 310 before being input to the drain of the PMOS306 based on the operating characteristics of the PMOS. IN addition, IN the case of adding the inverter 310, an inverter 312 may be added before the final output of the output signal OUT, so that the input signal IN and the output signal OUT are IN phase. It should be understood that "coupled," as used herein, may include direct connection, and may also include indirect connection.

In a further embodiment, based on the PMOS operating characteristics, to achieve the above control effect, the adjusting unit of fig. 3a may include an inverter 304 between the nor gate 302 and the PMOS transistor 306. The signal output from inverter 304 may be as shown in CUb <0> of fig. 3 b. As shown by the shape "|" on the left of fig. 3b, during the rising edge of the input signal IN and the output signal OUT (the phase of OUT may be delayed compared to IN due to the action of the inverter, as described above), PMOS306 is driven because signal CUb <0> input to PMOS306 is at a low level, PMOS306 may have an effect on signal OUT. As indicated by the shape "|" on the right side of fig. 3b, during the falling edge of the input signal IN and the output signal OUT, since the signal CUb <0> input to PMOS306 is at a high level, PMOS306 is not driven and PMOS306 does not affect signal OUT. PMOS306 will slow the rising edge due to the PMOS operating characteristics, thereby postponing the rising edge and reducing the duty cycle.

The invention may be used with a plurality of conditioning units in parallel as shown in figure 3 a. The number of the adjusting units can be set according to actual needs. The state of each regulating unit is independently controllable. In use, some, all, or none of the regulation units may be enabled as required for actual duty cycle regulation, thereby achieving the desired duty cycle reduction.

Fig. 4a-4b are schematic diagrams of a regulating unit of the second DCA module for increasing the duty cycle of a signal and timing diagrams thereof. Each of the adjustment units may include a nor gate 402 and an NMOS transistor 406. As in connection with the timing diagram of fig. 4b, the main design idea of this embodiment is that each adjusting unit may be configured to: the timing delay of the transition from low to high input to nor gate 402 causes NMOS 406 to be turned on at the rising edge of the signal (i.e., the drive current for NMOS 406 is active), such that NMOS 406 advances the rising edge of the signal to increase the duty cycle of the signal; and the timing delay of the transition from high to low input to nor gate 402 causes NMOS 406 to not be turned on at the falling edge of the signal (i.e., the drive current of NMOS 406 is disabled) so that NMOS 406 does not change the falling edge of the signal.

The first input of the nor gate 402 of each adjustment unit may be high or low. When the first input is high (e.g., C _ D <0> -H as shown in fig. 4 a), the high level may control the regulating unit to be in an active state, i.e., to enable the regulating unit. When the first input is low (e.g., C _ D <0> ═ L), the low level may control the regulating unit to be in an inactive state, i.e., not enable the regulating unit. It should be noted that an inverter 414 may be added to the first line to achieve the above control effect due to the operational characteristics of the nor gate. A delay device 408 may be included on the second input line of the nor gate 402 of each of the conditioning cells such that the second input of the nor gate 402 of each of the conditioning cells is a delayed input signal. For example, IN connection with fig. 4b, the second input of the nor gate 402 may be the delayed input signal IN _ D.

IN an embodiment of the present invention, as shown IN conjunction with the timing diagram of FIG. 4b, the amount of delay generated by delay device 408 on input signal IN may be set as: at least the entire rising edge of the signal whose duty ratio is to be adjusted (which may be, for example, the input signal IN or, if an inverter 410 is used, the input signal IN after passing through the inverter 410) is made to fall IN the low level region of the timing delayed pulse signal IN _ D (as indicated by the block of the shape "|" on the left side of fig. 4 b), and correspondingly, the entire falling edge of the signal whose duty ratio is to be adjusted falls at least IN the high level region of the timing delayed pulse signal IN _ D (as indicated by the block of the shape "| |" on the right side of fig. 4 b). Since the output of nor gate 402 is directly coupled to NMOS 406, accordingly, the entire rising edge of input signal IN or phase-delayed input signal IN (similar to the phase of OUT) falls IN the high region of output CD <0> of nor gate 402; the entire falling edge of the input signal IN or the phase-delayed input signal IN (similar to the phase of OUT) falls IN the low level region of the output (CD <0>) of the nor gate 402. Two delay devices 308, which may be buffers, are shown in fig. 4 b. This is, however, exemplary only and not limiting. Other numbers and/or types of delay devices may be provided based on the above delay amount setting requirements.

The gate (G) of NMOS 406 may be coupled to the output of nor gate 402. The drain (D) of NMOS 406 may be coupled to the input signal whose duty cycle is to be adjusted. The input signal whose duty ratio is to be adjusted may be, for example, the signal IN, or an IN signal (similar to OUT) with a phase delay after passing through the inverter 410, and the inverter 410 may be added due to the operating characteristics of NMOS. The source (S) of NMOS 406 may be coupled to ground. As described above, the input signal IN may pass through the inverter 410 before being input to the drain of the PMOS 406 based on the operating characteristics of the NMOS. IN addition, IN the case of adding the inverter 410, the inverter 412 may be further added before the final output of the output signal OUT, so that the input signal IN and the output signal OUT are IN phase. It will be appreciated that "coupled," as used herein, may include direct connection, and may also include indirect connection.

As shown by the shape "|" on the left of fig. 4b, during the rising edge of the input signal IN and the output signal OUT (as described above, the phase of OUT may be delayed compared to IN due to the action of the inverter), NMOS 406 is driven because the signal CD <0> input to NMOS 406 is at a high level, and NMOS 406 has an effect on the signal OUT. As indicated by the box of shape "|" on the right side of fig. 4b, during the falling edge of the input signal IN and the output signal OUT, the NMOS 406 is not driven because the signal CD <0> input to the NMOS 406 is at a low level, and the NMOS 406 has no effect on the signal OUT. Due to the operating characteristics of the NMOS, NMOS 406 will accelerate the rising edge, thereby advancing the rising edge to increase the duty cycle.

The invention may be used with a plurality of conditioning units in parallel as shown in figure 4 a. The number of the adjusting units can be set according to actual needs. The state of each regulating unit is independently controllable. In use, some, all, or none of the regulation units may be enabled as required for actual duty cycle regulation to achieve the desired increase in duty cycle.

Fig. 5 is a circuit schematic of a duty cycle adjuster capable of increasing and decreasing the duty cycle of a signal. For a multi-phase signal, each phase of the multi-phase signal may be independently adjusted by a respective duty cycle adjuster. For example, in DDR5 applications with four-phase DQS, the four phases may be independently adjusted by four duty cycle adjusters, respectively. In a preferred embodiment of the present invention, the duty cycle adjuster for a first phase of a multi-phase signal (e.g., ICLK in a four-phase signal) may not vary the duty cycle of the first phase (as shown in fig. 6 b). The duty cycles of the second, third and fourth phases may be independently adjusted by, for example, respective duty cycle adjusters for the second, third and fourth phases of the four-phase signal.

The duty cycle adjuster of fig. 5 may include the first DCA module and the second DCA module described above. The first DCA module and the second DCA module may be connected in parallel. Furthermore, in a preferred embodiment, the number of the adjusting units of the first DCA module may be the same as the number of the adjusting units of the second DCA module. A mixer comprising PMOS and NMOS may enable the duty cycle adjuster to move the rising edge of the signal forward or backward for duty cycle increase or decrease.

In DDR5 four-phase DQS applications, the first DCA block may include 7 regulation units and the second DCA block may include 7 regulation units. As described above, the mode register MR43OP [2:0] may be used to specify the steps of the second phase duty cycle adjustment of the four-phase signal, and MR43OP [3] may be used to specify the positive or negative sign of the steps, and may include 14 steps of-7 to + 7; the steps of duty cycle adjustment for the third phase may be specified using mode registers MR43OP [6:4] and the positive or negative sign of the steps may be specified using MR43OP [7], and may include 14 steps of-7 to + 7; the steps of the fourth phase duty cycle adjustment may be specified using mode register MR44 OP [2:0] and the positive or negative sign of the steps using MR44 OP [3], and may include 14 steps of-7 to + 7.

The 14 steps can be realized by using different state combinations of 14 regulating units connected in parallel. The first DCA module may be adapted to perform steps +1 to + 7. The second DCA module may be configured to perform steps-1 through-7. As shown in connection with fig. 5, steps +1 to +7 correspond to 1 to 7 of the 7 regulating units in the first DCA module being active, respectively, and steps-1 to-7 correspond to 1 to 7 of the 7 regulating units in the second DCA module being active, respectively. The states of the 14 regulating units are independently controllable. Thus, a corresponding number of regulating units may be enabled according to the actual need, thereby achieving the desired amount of increasing/decreasing duty cycle.

Fig. 6a-6b are schematic diagrams of a DLL circuit including a duty cycle adjuster according to the present invention and timing diagrams of output signals of the duty cycle adjuster circuit. As shown in FIG. 6a, in addition to the duty cycle adjusters 612-1, 612-2, 612-3, 612-4 described above, the DLL circuit may include some other circuitry, such as one or more of: a phase detector 602 operable to detect whether a phase of the clock signal CLK coincides with a phase of a DLL output signal (e.g., DCA _ OUT); a DLL control 604 operable to output a control signal to control the regulation of the voltage (e.g., U voltage up, D voltage down) based on the comparison of the phase detector; a charge pump 606 operable to output a voltage control signal (VCTRL) in accordance with the control signal output by the DLL control; a Voltage Controlled Delay Line (VCDL)608 operable to perform voltage control in accordance with a voltage control signal; MIMIC circuit 610, which may be used to model circuit components from CLK to DCA output to model the effect of various factors on the input CLK clock signal in the DLL circuit, especially the duty cycle; a frequency divider 614 for dividing the four-phase signal from the MIMIC into four phases, e.g., ICLK (0 °), QCLK (90 °), IBCLK (180 °), and QBCLK (270 °). The frequency divider 614 may be coupled to respective duty cycle adjusters 612-1, 612-2, 612-3, 612-4. The duty cycle adjusters 612-1, 612-2, 612-3, 612-4 operate according to the same principles as described above and will not be described in detail herein.

With the circuit diagram of the present invention as shown in fig. 6a, not only the output ICLK signal and CLK can be made to be in the same phase, but also the duty cycles of the output QCLK, BCLK and QBCLK signals can be independently adjusted according to the situation or need. Since the present invention places the duty cycle adjuster IN the loop of the DLL circuit, as shown IN fig. 3a and 4a, after the phase of the input signal IN is affected through, for example, an inverter (e.g., one or more of 310, 312, 410, or 412), the rising edge of ICLK can be realigned to the rising edge of the clock signal CLK after DLL locking IN the DLL circuit (so that the phases of QCLK, BCLK, and QBCLK can return to the respective correct positions due to the fixed phase relationship between ICLK and QCLK, BCLK, and QBCLK), and only the rising edges of QCLK, BCLK, and QBCLK are adjusted, as shown IN the timing diagram of fig. 6b, thereby avoiding the effect on tDQSCK timing.

Fig. 7 is a corresponding diagram of the mode register control bits and steps due to duty cycle adjustment and control signals received by each adjustment unit in the DDR5 application scenario of the present invention. One of the inputs C _ D < m > or C _ U < n > (m and n may both be 7 in the example of fig. 7) of the nor gate of each adjustment unit may be "1" or "0". Where "1" may indicate a high potential and "0" may indicate a low potential.

Step 0(+0 or-0 as shown by the dashed box) may be that none of the 14 adjustment units is enabled, so that no delay is applied to the signal. Steps +1 to +7 may correspond to 1 to 7 regulating units comprising PMOS being enabled, thereby enabling a corresponding amount of duty cycle reduction. Steps-1 to-7 may correspond to 1 to 7 regulating units comprising NMOS being enabled, thereby enabling a corresponding amount of duty cycle increase.

As described herein, for ease of understanding, the present description will be described primarily with respect to DDR5 as an example. However, the invention is not limited to application in DDR5, but may be used in any use scenario where duty cycle adjustment is required. In particular, the techniques of the present application are more beneficial in situations where the rising edge needs to be adjusted while the falling edge remains unchanged. In other application scenarios, the corresponding parameters may change, for example, the step adjustment may be a number of steps other than-7 to +7 for 14 adjustment steps, and the number of phases may not be limited to four phases. Other parameters may also vary and are not limited to the specific forms described herein, but are to be construed as limitations on the scope of the invention.

The basic concept of the present invention has been described above. It will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the embodiments of the present application.

Claims

1. A duty cycle adjuster, comprising:

a first duty cycle adjusting DCA module comprising M parallel adjusting units, each adjusting unit comprising a NOR gate and a PMOS transistor, each adjusting unit configured to: the timing delay of the transition from low to high input to the nor gate causes the PMOS to be opened on the rising edge of the signal, whereby the PMOS delays the rising edge of the signal to reduce the duty cycle of the signal; and the timing delay of the transition from high to low input to the NOR gate causes the PMOS not to be turned on the falling edge of the signal so that the PMOS does not change the falling edge of the signal, and/or

A second duty cycle adjustment DCA module comprising N parallel adjustment units, each adjustment unit comprising a NOR gate and an NMOS transistor, each adjustment unit configured to: the timing delay of the transition from the low level to the high level input to the nor gate causes the NMOS to be turned on at a rising edge of a signal, so that the NMOS advances the rising edge of the signal to increase the duty ratio of the signal; and the timing delay of the transition from high level to low level input to the nor gate causes the NMOS not to be turned on at the falling edge of the signal so that the NMOS does not change the falling edge of the signal.

2. The duty cycle adjuster according to claim 1,

a gate of the PMOS is coupled to an output of the NOR gate, a drain of the PMOS is coupled to an input signal whose duty cycle is to be adjusted, a source of the PMOS is coupled to a power supply, and/or

The gate of the NMOS is coupled to the output of the NOR gate, the drain of the NMOS is coupled to the input signal whose duty cycle is to be adjusted, and the source of the NMOS is coupled to ground.

3. The duty cycle adjuster of claim 2, wherein an inverter is included between the NOR gate and the PMOS in the first DCA module.

4. The duty cycle adjuster of claim 2, wherein the input signal passes through an inverter before being input to the drain of the NMOS or PMOS, and a final output signal of the duty cycle adjuster includes an inverter before.

5. The duty cycle adjuster according to claim 2,

the first input line of the NOR gate of each adjusting unit comprises an inverter;

the first input of the NOR gate of each adjusting unit is high level or low level, when the first input is high level, the high level controls the adjusting unit to be in an active state, and when the first input is low level, the low level controls the adjusting unit to be in an inactive state;

a delay device is included on the second input line of the nor gate of each of the regulating units such that the second input of the nor gate of each of the regulating units is a delayed input signal, and wherein

The state of each regulating unit is independently controllable.

6. The duty cycle adjuster according to claim 5, wherein the amount of delay the delay device generates for the input signal is set to: at least the entire rising edge of the signal whose duty cycle is to be adjusted is made to fall in the low level region of the delayed input signal and, correspondingly, the entire falling edge of the signal whose duty cycle is to be adjusted is made to fall in the high level region of the delayed input signal.

7. The duty cycle adjuster of claim 1, disposed in a Delay Locked Loop (DLL) circuit, wherein the change in the rising edge is made during DLL lock.

8. The duty cycle adjuster of claim 7, wherein the duty cycle adjuster is disposed after a MIMIC circuit in the DLL circuit.

9. The duty cycle adjuster of claim 1, wherein when the duty cycle adjuster includes both the first DCA module and the second DCA module, the first DCA module and the second DCA module are in parallel.

10. The duty cycle adjuster according to claim 9, wherein M is equal to N.

11. The duty cycle regulator of any one of claims 1-10, wherein the duty cycle regulator comprises a duty cycle regulator for a DDR5 four-phase bidirectional data control pin DQS internal clock.

12. The duty cycle adjuster according to claim 11,

the number of duty cycle adjusters comprising four, each phase of a four-phase signal being independently adjusted by a respective duty cycle adjuster, each duty cycle adjuster comprising the first DCA module and the second DCA module in parallel;

a duty cycle adjuster for a first phase of the four-phase signal does not vary a duty cycle of the first phase;

respective duty cycle adjusters for second, third and fourth phases of the four-phase signal independently adjust duty cycles of the second, third and fourth phases.

13. The duty cycle adjuster according to claim 12,

in each duty cycle adjuster, the first DCA module includes 7 adjusting units, and the second DCA module includes 7 adjusting units; and is

The duty cycle adjuster is configured to:

using a mode register MR43OP [2:0] to specify steps of the second phase duty cycle adjustment, and MR43OP [3] to specify the positive or negative sign of the steps, and the steps include 14 steps-7 to + 7;

using mode register MR43OP [6:4] to specify steps of the third phase duty cycle adjustment, and MR43OP [7] to specify the positive or negative sign of the steps, and the steps include 14 steps-7 to + 7;

the pattern register MR44 OP [2:0] is used to specify the steps of the fourth phase duty cycle adjustment, and MR44 OP [3] is used to specify the positive or negative sign of the steps, and the steps include 14 steps from-7 to + 7.

14. The duty cycle regulator of claim 13, wherein 14 steps are achieved by using different state combinations of 14 regulating cells in parallel.

15. The duty cycle adjuster of claim 14, wherein the first DCA module of each duty cycle adjuster is configured to perform steps +1 through +7, the second DCA module is configured to perform steps-1 through-7, and wherein

Steps +1 to +7 correspond to 1 to 7 of the 7 conditioning units in the first DCA module being active, respectively, and steps-1 to-7 correspond to 1 to 7 of the 7 conditioning units in the second DCA module being active, respectively.

16. The duty cycle adjuster according to claim 13, wherein the adjustment range for each step is 2ps-4ps, and the total adjustment range for 14 steps is 28ps-56 ps.

17. The duty cycle adjuster of claim 12, disposed in a Delay Locked Loop (DLL) circuit comprising a divider configured to divide a four-phase input signal into first, second, third and fourth phases that differ by pi/2 between adjacent phases.

18. A delay locked loop, DLL, circuit comprising a duty cycle adjuster as claimed in any of claims 1 to 17.