CN115001415A - Strong-driving reference buffer circuit applied to multi-channel analog-to-digital converter - Google Patents

Strong-driving reference buffer circuit applied to multi-channel analog-to-digital converter Download PDF

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Publication number
CN115001415A
CN115001415A CN202210611370.3A CN202210611370A CN115001415A CN 115001415 A CN115001415 A CN 115001415A CN 202210611370 A CN202210611370 A CN 202210611370A CN 115001415 A CN115001415 A CN 115001415A
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China
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operational amplifier
resistor
capacitor
voltage
digital converter
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Inventor
孙权
罗红瑞
焦子豪
陈阳
袁婷
蔡滨宇
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XI'AN AEROSPACE MINXIN TECHNOLOGY CO LTD
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XI'AN AEROSPACE MINXIN TECHNOLOGY CO LTD
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Priority to CN202210611370.3A priority Critical patent/CN115001415A/en
Publication of CN115001415A publication Critical patent/CN115001415A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a strong drive reference buffer circuit applied to a multi-channel analog-to-digital converter, which improves output voltage through a voltage division unit and reduces input voltage of an operational amplifier, so that the output voltage of the operational amplifier is higher than the input voltage, the input voltage of the operational amplifier becomes reasonable, and no device enters a linear area. According to the invention, the level transfer unit is added at the output end of the operational amplifier, so that the output voltage of the operational amplifier is reduced, and the operational amplifier cannot enter a linear region during working; according to the invention, a capacitor is added to the grid electrode of the PMOS transistor M4, and then the high-frequency noise is filtered by the filtering unit, so that the noise of the output end of the operational amplifier is reduced, and the precision of the analog-to-digital converter is improved.

Description

Strong-driving reference buffer circuit applied to multi-channel analog-to-digital converter
Technical Field
The application belongs to the field of buffer circuits, and particularly relates to a strong-driving reference buffer circuit applied to a multi-channel analog-to-digital converter.
Background
The invention discloses a high-precision strong-driving reference buffer circuit applied to an analog-to-digital converter, which can generate a driving voltage of 4.0V as a reference voltage of the analog-to-digital converter, and is provided with a circuit structure which is formed by combining a reference circuit, a reference driver and a reference buffer circuit.
The conventional circuit structure is shown in fig. 1, in which a reference generates a voltage VREFP after being output, the VREFP is connected to the positive input terminal of the operational amplifier, then the voltage VREFP is generated at net1 through a loop formed by M1 and the operational amplifier, and then the current is copied in proportion through branch 2 (driving stage) to generate VREFP at net 2. Although this circuit can implement the function of the reference driver, it has two limitations for this application:
1. the input voltage of 4.0V is too high for the sleeve type operational amplifier, and part of MOS tube works in a linear region, so that the input voltage of the operational amplifier needs to be reduced.
2. A voltage of 4.0V is generated at net1, and the threshold voltage of M1 is typically above 0.5V. Therefore, the output of the operational amplifier is above 4.5V, the operational amplifier designed at this time is of a single-stage sleeve type structure, and when the power supply voltage is 4.75V, the operational amplifier works in a linear region when the output voltage of the operational amplifier is above 4.5V, so that the operational amplifier works abnormally.
3. C of the drive tube M2 GS The capacitance is large, and when voltage fluctuation exists in the output, a fluctuation signal is coupled to the output end of the operational amplifier, so that the loop is unstable.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned disadvantages, and to provide a strong driving reference buffer circuit applied to a multi-channel analog-to-digital converter, which can improve the precision and stability.
In order to achieve the purpose, the power amplifier comprises an operational amplifier, wherein the forward input end of the operational amplifier is connected with a voltage VREFP, the reverse input end of the operational amplifier is connected with a voltage dividing unit, the output end of the operational amplifier is connected with a level shifting unit, the level shifting unit is connected with the grid electrode of a PMOS (P-channel metal oxide semiconductor) transistor M3, the source electrode of a PMOS (P-channel metal oxide semiconductor) transistor M3 is connected with the voltage dividing unit, a PMOS transistor M3 is connected with a filtering unit, and the filtering unit is connected with one end of a voltage dividing capacitor C2 and a capacitor C2 GS One end of the transistor is connected with the source electrode of the PMOS transistor M4, and the source electrode of the PMOS transistor M4 is connected with the capacitor C GS The other end of the resistor R5 is connected with a resistor R5, a resistor R6 is connected with the resistor R6, and the resistor R6 is grounded.
The output end of the operational amplifier is connected with one end of the capacitor C3 and the level shifting unit, and the other end of the capacitor C3 is grounded.
The level shift unit comprises a level shifter M1 and an NMOS transistor M2, the grid electrode of the level shifter M1 is connected with the output end of the operational amplifier, the drain electrode of the level shifter M1 is grounded, and the source electrode of the level shifter M1 is connected with the grid electrode of the PMOS transistor M3 and the drain electrode of the NMOS transistor M2.
The voltage division unit comprises a resistor R2 and a resistor R3, the reverse input end of the voltage division unit is connected with one end of the resistor R2 and one end of the resistor R3, the other end of the resistor R2 is connected with the source electrode of the PMOS transistor M3, and the other end of the resistor R3 is grounded.
The filter unit comprises a resistor R1 and a capacitor C1, a PMOS transistor M3 is connected with one end of the resistor R1 and one end of the capacitor C1, and the other end of the resistor R1 is connected with one end of a voltage-dividing capacitor C2 and the capacitor C GS And the source of the PMOS transistor M4, and the other end of the capacitor C1 is grounded.
The voltage VREFP at the positive input of the operational amplifier is 2.5V.
The output voltage of the operational amplifier is 4.0V.
Coupling voltage V generated by operational amplifier output end out The calculation method of (2) is as follows:
Figure BDA0003673202070000021
wherein, C GS Is a capacitor C GS Capacitor of C p For parasitic capacitance, Δ V is the output voltage filter.
Compared with the prior art, the invention improves the output voltage through the voltage division unit and reduces the input voltage of the operational amplifier, so that the output voltage of the operational amplifier is higher than the input voltage, the input voltage of the operational amplifier becomes reasonable, and no device enters a linear region. According to the invention, the level transfer unit is added at the output end of the operational amplifier, so that the output voltage of the operational amplifier is reduced, and the operational amplifier cannot enter a linear region during working; according to the invention, a capacitor is added to the grid electrode of the PMOS transistor M4, and then the high-frequency noise is filtered by the filtering unit, so that the noise of the output end of the operational amplifier is reduced, and the precision of the analog-to-digital converter is improved.
Drawings
FIG. 1 is a circuit diagram of a conventional digital-to-analog converter;
fig. 2 is a circuit diagram of a digital-to-analog converter of embodiment 1;
fig. 3 is a circuit diagram of a digital-to-analog converter of embodiment 2.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Example 1:
referring to fig. 2, the invention comprises an operational amplifier, wherein a forward input end of the operational amplifier is connected with a voltage VREFP, a reverse input end of the operational amplifier is connected with a voltage dividing unit, an output end of the operational amplifier is connected with a level shifting unit, the level shifting unit is connected with a grid electrode of a PMOS transistor M3, a source electrode of a PMOS transistor M3 is connected with the voltage dividing unit, a PMOS transistor M3 is connected with a filtering unit, the filtering unit is connected with one end of a voltage dividing capacitor C2 and a capacitor C2 GS One end of the PMOS transistor M4 is connected with the source electrode of the PMOS transistor M4, and the source electrode of the PMOS transistor M4 is connected with the capacitor C GS The other end of the resistor R5 is connected with a resistor R5, the resistor R5 is connected with a resistor R6, and the resistor R6 is grounded.
The level shift unit comprises a level shifter M1 and an NMOS transistor M2, the grid electrode of the level shifter M1 is connected with the output end of the operational amplifier, the drain electrode of the level shifter M1 is grounded, and the source electrode of the level shifter M1 is connected with the grid electrode of the PMOS transistor M3 and the drain electrode of the NMOS transistor M2.
The voltage division unit comprises a resistor R2 and a resistor R3, the reverse input end of the voltage division unit is connected with one end of the resistor R2 and one end of the resistor R3, the other end of the resistor R2 is connected with the source electrode of the PMOS transistor M3, and the other end of the resistor R3 is grounded.
The filter unit comprises a resistor R1 and a capacitor C1, a PMOS transistor M3 is connected with one end of the resistor R1 and one end of the capacitor C1, and the other end of the resistor R1 is connected with one end of a voltage-dividing capacitor C2 and the capacitor C GS One terminal of the capacitor C1 is grounded with the source of the PMOS transistor M4.
Preferably, the voltage VREFP at the positive input of the operational amplifier is 2.5V.
Preferably, the output voltage of the operational amplifier is 4.0V.
Example 2:
referring to fig. 3, the output end of the operational amplifier in the loop of the present invention is a large resistor and a small capacitor, and the gate end of the PMOS transistor M3 is a small resistor (1/gm1) and a large capacitor (capacitor C1 and capacitor C2), so that the two poles are close to each other, the loop is unstable, and the two poles need to be separated by compensation, so as to stabilize the system.
The invention comprises an operational amplifier, wherein the positive input end of the operational amplifier is connected with a voltage VREFP, the reverse input end of the operational amplifier is connected with a voltage dividing unit, the output end of the operational amplifier is connected with a level shift unit, the level shift unit is connected with the grid electrode of a PMOS (P-channel metal oxide semiconductor) transistor M3, the source electrode of the PMOS transistor M3 is connected with the voltage dividing unit, the PMOS transistor M3 is connected with a filtering unit, the filtering unit is connected with one end of a voltage dividing capacitor C2 and a capacitor C2 GS One end of the transistor is connected with the source electrode of the PMOS transistor M4, and the source electrode of the PMOS transistor M4 is connected with the capacitor C GS The other end of the operational amplifier is connected with a resistor R5, a resistor R5 is connected with a resistor R6, a resistor R6 is grounded, the output end of the operational amplifier is connected with one end of a capacitor C3 and the level shifting unit, and the other end of the capacitor C3 is grounded.
The level shift unit comprises a level shifter M1 and an NMOS transistor M2, the grid electrode of the level shifter M1 is connected with the output end of the operational amplifier, the drain electrode of the level shifter M1 is grounded, and the source electrode of the level shifter M1 is connected with the grid electrode of the PMOS transistor M3 and the drain electrode of the NMOS transistor M2.
The voltage division unit comprises a resistor R2 and a resistor R3, the reverse input end of the voltage division unit is connected with one end of the resistor R2 and one end of the resistor R3, the other end of the resistor R2 is connected with the source electrode of the PMOS transistor M3, and the other end of the resistor R3 is grounded.
The filter unit comprises a resistor R1 and a capacitor C1, wherein a PMOS tube M3 is connected with one end of a resistor R1 and one end of a capacitor C1, and the other end of the resistor R1 is connected with one end of a voltage division capacitor C2 and the capacitor C GS One terminal of the capacitor C1 is grounded with the source of the PMOS transistor M4.
Preferably, the voltage VREFP at the positive input of the operational amplifier is 2.5V.
Preferably, the output voltage of the operational amplifier is 4.0V.
In this embodiment, an appropriate capacitor C3 is added to the output terminal of the operational amplifier, so that the output terminal of the operational amplifier generates a small pole and is separated from another pole, and as long as the sub-pole is pushed to 2GBW to 3GBW, the system can reach a phase margin of about 60 degrees, thereby stabilizing the loop.
Referring to fig. 2 and 3, the output voltage of the operational amplifier is 4V or less by adding a level shifter M1 and changing an NMOS transistor M2. Since the source terminal voltage of the PMOS transistor M3 is 4.0V, assuming that the threshold voltage of the PMOS transistor M3 is 0.5V, the gate terminal voltage of the PMOS transistor M3 is 4.5V, so the source terminal of the level shifter M1 is 4.5V, assuming that the threshold voltage of the level shifter M1 is 0.5V, the operational amplifier output is 4.0V. Thus, the problem that the operational amplifier works in a linear region is solved.
Due to the capacitance C of the driving tube GS The parasitic capacitance at the output end of the operational amplifier is very small, and if the parasitic capacitance is Cp and the output voltage fluctuation is delta V, the coupling voltage V generated at the output end of the operational amplifier out Coupling voltage V generated at output end of operational amplifier out The calculation method of (2) is as follows:
Figure BDA0003673202070000051
wherein, C GS Is a capacitor C GS Capacitor of C p And is parasitic capacitance, and Δ V is output voltage filtering.
Therefore, voltage fluctuation at the output end of the driver is almost applied to the output end of the operational amplifier, and the output end of the operational amplifier is in a loop, so that loop oscillation is caused, and the system is unstable.
The crosstalk problem is solved by adding the cross-talk signal at the grid of the PMOS tube M4A capacitor C2 passing through the capacitor C GS And the voltage division of the C2 can reduce the voltage noise at the grid end of the PMOS tube M4 of the driving tube, and then the high-frequency noise is filtered by an RC filter consisting of a resistor R1 and a capacitor C1, so that the noise signal at the source end of the level shifter M1 is greatly reduced. Therefore, the noise at the output end of the operational amplifier is greatly reduced, and the influence of the voltage fluctuation output by the driver on the loop can be ignored.
The invention improves the reference driving circuit, thereby improving the precision and the stability, the power supply voltage of the reference driving circuit is 4.75V-5.25V, the output voltage of the reference and the driver is 4.0V, and the process is a high-tower semiconductor of 0.18 um.

Claims (8)

1. The strong-drive reference buffer circuit applied to the multichannel analog-to-digital converter is characterized by comprising an operational amplifier, wherein the forward input end of the operational amplifier is connected with a voltage VREFP, the reverse input end of the operational amplifier is connected with a voltage division unit, the output end of the operational amplifier is connected with a level transfer unit, the level transfer unit is connected with the grid electrode of a PMOS (P-channel metal oxide semiconductor) tube M3, the source electrode of the PMOS tube M3 is connected with the voltage division unit, the PMOS tube M3 is connected with a filtering unit, and the filtering unit is connected with one end of a voltage division capacitor C2 and a capacitor C GS One end of the PMOS transistor M4 is connected with the source electrode of the PMOS transistor M4, and the source electrode of the PMOS transistor M4 is connected with the capacitor C GS The other end of the resistor R5 is connected with a resistor R5, the resistor R5 is connected with a resistor R6, and the resistor R6 is grounded.
2. The strong driving reference buffer circuit applied to the multi-channel analog-to-digital converter as claimed in claim 1, wherein the output terminal of the operational amplifier is connected to one terminal of the capacitor C3 and the level shifting unit, and the other terminal of the capacitor C3 is grounded.
3. The strong driving reference buffer circuit applied to the multi-channel analog-to-digital converter of claim 1, wherein the level shifter unit comprises a level shifter M1 and an NMOS transistor M2, a gate of the level shifter M1 is connected to the output terminal of the operational amplifier, a drain of the level shifter M1 is grounded, and a source of the level shifter M1 is connected to a gate of the PMOS transistor M3 and a drain of the NMOS transistor M2.
4. The strong driving reference buffer circuit applied to the multi-channel analog-to-digital converter as claimed in claim 1, wherein the voltage dividing unit comprises a resistor R2 and a resistor R3, the inverting input terminal of the voltage dividing unit is connected to one end of the resistor R2 and one end of the resistor R3, the other end of the resistor R2 is connected to the source of the PMOS transistor M3, and the other end of the resistor R3 is grounded.
5. The strong driving reference buffer circuit applied to the multi-channel analog-to-digital converter of claim 1, wherein the filtering unit comprises a resistor R1 and a capacitor C1, the PMOS transistor M3 is connected to one end of the resistor R1 and one end of the capacitor C1, and the other end of the resistor R1 is connected to one end of a voltage dividing capacitor C2 and one end of a capacitor C2 GS One terminal of the capacitor C1 is grounded with the source of the PMOS transistor M4.
6. The strong-drive reference buffer circuit applied to the multi-channel analog-to-digital converter as claimed in claim 1, wherein the voltage VREFP at the positive input end of the operational amplifier is 2.5V.
7. The strong driving reference buffer circuit applied to the multi-channel analog-to-digital converter as claimed in claim 1, wherein the output voltage of the operational amplifier is 4.0V.
8. The strong drive reference buffer circuit applied to the multi-channel analog-to-digital converter as claimed in claim 1, wherein the coupling voltage V generated at the output end of the operational amplifier out The calculation method of (2) is as follows:
Figure FDA0003673202060000021
wherein, C GS Is a capacitor C GS Capacitor of C p For parasitic capacitance, Δ V is the output voltage filter.
CN202210611370.3A 2022-05-31 2022-05-31 Strong-driving reference buffer circuit applied to multi-channel analog-to-digital converter Pending CN115001415A (en)

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