CN115001297A - Improved carrier phase-shifting capacitance voltage balancing method suitable for direct-current fault ride-through - Google Patents

Improved carrier phase-shifting capacitance voltage balancing method suitable for direct-current fault ride-through Download PDF

Info

Publication number
CN115001297A
CN115001297A CN202210649039.0A CN202210649039A CN115001297A CN 115001297 A CN115001297 A CN 115001297A CN 202210649039 A CN202210649039 A CN 202210649039A CN 115001297 A CN115001297 A CN 115001297A
Authority
CN
China
Prior art keywords
voltage
sub
bridge
positive
half cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210649039.0A
Other languages
Chinese (zh)
Inventor
梅军
张森
雷刘鹏
张丙天
陈萧宇
郭家炜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southeast University
Original Assignee
Southeast University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southeast University filed Critical Southeast University
Priority to CN202210649039.0A priority Critical patent/CN115001297A/en
Publication of CN115001297A publication Critical patent/CN115001297A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483Converters with outputs that each can have more than two voltages levels
    • H02M7/4833Capacitor voltage balancing
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00Circuit arrangements for ac mains or ac distribution networks
    • H02J3/36Arrangements for transfer of electric power between ac networks via a high-tension dc link
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0048Circuits or arrangements for reducing losses
    • H02M1/0054Transistor switching losses
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/14Arrangements for reducing ripples from dc input or output
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/60Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]

Abstract

The invention discloses an improved carrier phase-shifting capacitance voltage balancing method suitable for direct current fault ride-through, which is based on the traditional carrier phase-shifting modulation, adjusts the distribution of signals between a half bridge and a full bridge submodule based on a virtual half bridge visual angle, and smoothly applies carrier phase-shifting to realize the direct current fault ride-through of a few-submodule mixed MMC. On the basis, based on the idea of reconstructing the mapping relation between the sub-modules and the pulse signals, the positive half cycle and the negative half cycle of the modulation wave are distinguished according to the voltage output requirement of the system, and the established distribution relation between the pulses and the sub-modules is adjusted according to a sequencing method, so that the balance of the capacitance and the voltage of the sub-modules during the DC fault ride-through period is realized. According to the invention, under the condition of not introducing extra balance compensation signals, the stability of the controller and the system is not changed, and the capacitance voltage balance of the minority carrier module hybrid MMC during the direct current fault ride-through period is smoothly realized only by changing the mapping relation on the basis of sequencing.

Description

Improved carrier phase-shifting capacitor voltage balancing method suitable for direct-current fault ride-through
Technical Field
The invention belongs to the field of modular multilevel converters, and particularly relates to an improved carrier phase-shifting capacitor voltage balancing method suitable for direct-current fault ride-through.
Background
Modular Multilevel Converters (MMC) are increasingly and widely applied to the fields of flexible direct-current transmission, medium and low voltage direct-current power distribution networks, new energy collection and grid connection and the like in recent years due to the advantages of modular structure, low switching frequency, strong fault handling capacity and the like. In some scenes such as new energy grid connection and the like, the number of MMC sub-modules is relatively small, and the situations are different from the situations of hundreds of sub-modules of each bridge arm of a high-voltage large-capacity MMC, so that typical recent Level approximation modulation (NLM) is no longer applicable, and carrier Phase-Shifted-Carrier PWM (PSC-PWM) can realize higher equivalent switching frequency under lower switching frequency, and the performance of the converter is better exerted.
The sub-module capacitance voltage balance control is one of the key technologies for the MMC to maintain stable operation. The traditional carrier phase shift modulation can maintain stable voltage of the capacitor of the sub-module during steady-state operation due to the self-balancing characteristic. However, during the dc fault, since the system experiences a complex and rapid transient process, and the switching state of the full-bridge sub-module is changed by the active current-limiting control adopted to implement the dc fault ride-through, the capacitor voltage of the sub-module is affected, and the system may be out of normal operation due to unbalanced or even deteriorated capacitor voltage fluctuation. Therefore, the conventional carrier phase shift modulation cannot meet the requirements of direct current fault ride through and capacitor voltage balance control during the fault ride through.
Aiming at the problems, the self-balancing characteristic of the traditional carrier phase shifting is deeply excavated based on the traditional carrier phase shifting, and an improved carrier phase shifting capacitor voltage balancing method suitable for direct current fault ride-through is researched and provided.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide an improved carrier phase-shifting capacitance voltage balancing method suitable for direct current fault ride-through, which not only enables a hybrid MMC to smoothly realize the direct current fault ride-through function, but also does not introduce additional balancing signals and complex control algorithms, realizes the sub-module capacitance voltage balancing during the direct current fault period by reconstructing a pulse mapping relation, and maintains the stable operation of a system
The purpose of the invention can be realized by the following technical scheme:
an improved carrier phase-shifting capacitance voltage balancing method suitable for direct current fault ride through comprises the following steps:
s1, when the system works normally, the traditional carrier phase shift modulation method is adopted, the modulated wave is compared with the carrier, the obtained switching pulse signals are sequentially sent to the sub-modules of each bridge arm, the carrier amplitude phases of the upper and lower bridge arms are the same, and the modulated wave is in phase reversal;
s2, after a direct current fault occurs, the voltage of a direct current bus is reduced to zero, a modulation wave is a sine wave which is equal around an X axis in positive and negative half cycles, the positive half cycle corresponds to a positive voltage output requirement, the negative half cycle corresponds to a negative voltage output requirement, and the positive half cycle and the negative half cycle are modulated independently based on different positive and negative voltage output requirements;
s3, in the positive half cycle of the modulation wave, positive voltage is output by the left equivalent half-bridge of HBSM and FBSM, the positive half cycle is compared with the carrier wave to obtain a switching pulse signal, the switching pulse signal is used for driving the sub-module to output the positive voltage, and similarly, the negative half cycle is compared with the carrier wave to obtain a switching pulse signal, the switching pulse signal is used for driving the sub-module to output the negative voltage;
s4, the mapping relation between the generated pulse signal and the actual sub-module is changed by considering the capacitor voltage balance control requirement, the sub-module capacitor voltage values are sequenced based on the carrier frequency, and the switch pulse signal is divided by the carrier frequency to complete the sampling and holding function.
Furthermore, on the basis of traditional carrier phase shift modulation, the distribution of signals between the half-bridge and the full-bridge sub-modules is adjusted, and the direct current fault ride-through of the few-sub-module hybrid MMC is realized by smoothly applying the carrier phase shift. On the basis, based on the idea of reconstructing the mapping relation between the sub-modules and the pulse signals, the positive half cycle and the negative half cycle of the modulation wave are distinguished according to the voltage output requirement of the system, and the established distribution relation between the pulses and the sub-modules is adjusted according to a sequencing method, so that the balance of the capacitance and the voltage of the sub-modules during the DC fault ride-through period is realized.
Furthermore, on the basis of traditional carrier phase shift modulation, the distribution of signals between a half bridge and a full bridge submodule is adjusted based on a virtual half bridge idea, positive and negative half cycles of a modulation wave are distinguished by utilizing the characteristic that the direct current of the modulation wave is biased to zero during direct current fault ride-through, the positive voltage is provided with output by the half bridge submodule and the virtual half bridge on the left side of the full bridge submodule together, the negative voltage is provided with output by the virtual half bridge on the right side of the full bridge submodule only, and the direct current fault ride-through of the mixed MMC with few submodules is realized by smoothly applying carrier phase shift.
Furthermore, during the direct-current fault ride-through period, in the positive half cycle of the modulation wave, according to a submodule capacitor voltage result obtained by a sequencing method, a submodule with higher voltage is selected from the submodules to be put into use, and the positive voltage output requirement is met; and selecting the full-bridge submodule to input according to the submodule capacitor voltage result obtained by the sequencing method on the negative half cycle wave of the modulation wave, so as to meet the negative pressure output requirement of the system.
The invention has the beneficial effects that:
1. the improved carrier phase-shifting capacitor voltage balancing method suitable for direct-current fault ride-through provided by the invention has the advantages that no correction quantity such as extra balance compensation signals is introduced, the problems of output electric energy quality, system stability and the like are not influenced, and no additional modes such as loop current injection are introduced to influence sub-module capacitor voltage ripples;
2. according to the improved carrier phase-shifting capacitance voltage balancing method suitable for direct-current fault ride-through, the pulse signal is obtained only through the separation of the positive and negative half cycles of the modulation wave, the mapping relation between the pulse and the actual sub-modules is reconstructed based on the sequencing method, the capacitance voltage balancing control of each sub-module is realized, and the switching frequency and the switching loss are not increased;
3. the invention provides an improved carrier phase-shifting capacitance voltage balancing method suitable for direct current fault ride-through, which adopts an HB + FB minority carrier module mixed type MMC, and realizes the maintenance of the capacitance voltage balance of sub-modules on the basis of ensuring that the system successfully realizes active current-limiting control to complete the direct current fault ride-through based on carrier phase-shifting modulation, thereby ensuring the stable operation of the system.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a three-phase hybrid MMC topology according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the HBSM (half bridge sub-module) operating state of an embodiment of the present invention;
FIG. 3 is a schematic diagram of the operation of an FBSM (full bridge sub-module) of an embodiment of the present invention;
FIG. 4 is a waveform diagram of the A-phase upper and lower bridge arm modulated waves according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of four sets of carriers according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of pulse trigger signals of four sub-modules of a single bridge arm according to an embodiment of the present invention;
fig. 7 is a schematic diagram of changes in transmission active power of a converter station according to an embodiment of the present invention;
FIG. 8 is a schematic illustration of the output AC current of a converter station according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of DC bus voltage of an embodiment of the present invention;
FIG. 10 is a schematic DC bus current diagram of an embodiment of the present invention;
FIG. 11 is a schematic diagram of the mean value of all sub-module capacitor voltages of an embodiment of the present invention;
fig. 12 is a schematic diagram of specific values of the capacitor voltages of the sub-modules of the upper bridge arm in phase a according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Because HBSM does not have direct current fault ride-through capability, and FBSM control is complicated, and the cost is higher than HBSM, therefore the operating condition and the voltage output requirement of the system are comprehensively considered.
As shown in fig. 1, the simulation model of this embodiment adopts a three-phase six-leg hybrid MMC structure with 2 HBSM and 2 FBSM for each leg. FIG. 2 and FIG. 3 show the working states of HBSM and FBSM, respectively, when HBSM is in positive input state, T 1 Conduction, T 2 Turning off the output voltage U of the sub-module SM Equal to the capacitor voltage U C (ii) a In the bypass state, the device T 1 Off, T 2 Conducting, bypassing the sub-module capacitor C, and outputting the sub-module output voltage U SM Equal to 0. Namely HBSM can realize 0, + U output by controlling the on-off state of the switch device C Two levels.
When the FBSM is in a positive input state, T 1 、T 4 Conduction, T 2 、T 3 Turning off the output voltage U of the sub-module SM Equal to the capacitor voltage U C (ii) a In the negative input state, the device T 1 、T 4 Off, T 2 、T 3 Conducting when the sub-module outputs voltage U SM Is equal to-U C (ii) a In the bypass state, the device T 1 、T 3 Or T 2 、T 4 Conducting, bypassing the sub-module capacitor C, and outputting the sub-module output voltage U SM Equal to 0. That is, the FBSM can output 0, + U by controlling the on-off state of the switching device C 、-U C Three levels. Therefore, the negative input state of the FBSM can be utilized to widen the bridge arm voltage output of the mixed MMCThe range is reduced, so that the direct-current output voltage of the converter station is reduced, and the control of direct-current fault current is realized.
Because FBSM has two more Insulated Gate Bipolar Transistor (IGBT) control signals than HBSM, FBSM in the conventional view is more complex than HBSM, and the two are not strongly connected, and it is difficult to find a control commonality to optimize the valve side control strategy. The invention develops a control method aiming at capacitance voltage balance on the basis of a virtual half-bridge visual angle and a hybrid modulation technology.
The system adopts the traditional carrier phase shift modulation strategy when in normal operation. The 4 submodules in the bridge arms correspond to the same modulated wave, four groups of carriers sequentially shift the phase by 360 degrees/N, the modulated waves of the lower bridge arm and the upper bridge arm are in opposite phases, and the four groups of carriers are sequentially identical, as shown in fig. 5. Comparing the modulated wave with 4 groups of carriers to obtain 4 groups of switching pulse signals, as shown in fig. 6, sequentially providing the 4 sub-modules in the bridge arm, namely realizing traditional carrier phase shift modulation. Because the capacitor voltage balancing circuit has self-balancing characteristics, the capacitor voltage balancing effect of the sub-module is better in a steady state. When the direct current fault occurs, the direct current bus voltage rapidly drops to zero, namely the direct current offset of the modulation wave drops to zero, so that the modulation wave is a sine wave which is equal around the positive half cycle and the negative half cycle of the X axis at the moment. The positive half cycle corresponds to a positive pressure output requirement, and the negative half cycle corresponds to a negative pressure output requirement. Therefore, based on different requirements of positive and negative pressure output, the positive and negative half cycles need to be modulated independently, namely, the positive and negative half cycles are classified according to the modulation wave. As shown in fig. 4, in the positive half cycle of the modulation wave (taking the a-phase upper arm as an example, and the lower arm is the same), the left equivalent half-bridges of 2 HBSMs and 2 FBSMs can both output positive voltage, so that after comparing the positive half cycle with 2 sets of carriers, 2 sets of switching pulse signals are obtained for driving the sub-modules to output positive voltage. Similarly, comparing the negative half cycle with 2 sets of carriers, 2 sets of switching pulse signals are also obtained to drive the sub-module to output negative pressure. Namely: according to the positive and negative half cycles of the modulation wave, 2 kinds of 2 groups of switching pulse signals are generated:
(1) in the positive half cycle of the modulation wave, the problem to be solved is how to give 2 groups of switching pulse signals to 2 of 4 sub-modules, so that the control system not only completes fault ride-through, but also realizes capacitor voltage balance control.
Considering the requirement of capacitance-voltage balance control, the selection investment is realized based on the idea of reconstructing the mapping relation between the pulse signal and the actual submodule. Firstly, sequencing the voltage values of the capacitors of the 4 sub-modules; and secondly, judging according to the sequencing result of the 4 sub-modules of the capacitor and the voltage and the positive and negative directions of the bridge arm current. The judgment logic is as follows: bridge arm current enables the submodules to be charged with two submodules with lower voltage and to be discharged with two submodules with higher voltage; and thirdly, in order to avoid that the switching frequency is too high due to overhigh change frequency of the comparison result and increase meaningless loss, the voltage value of the sub-module capacitor and the switching pulse signal are sampled by the carrier frequency to complete the sampling and holding function. Namely, taking the carrier frequency as a balance control period; and finally, in each balance control period, the functions of screening 2 sub-modules from the 4 sub-modules and giving pulse signals to the sub-modules are realized, and the capacitor voltage balance control is completed.
(2) In the modulation wave negative half cycle, only two FBSMs are put into the system because only the FBSMs have negative voltage output capability, and judgment is carried out only according to the sequencing result of the 2 FBSM capacitor voltages and the positive and negative directions of the bridge arm current. Since the right side of the FBSM is equivalent to a half bridge, that is, a part capable of outputting negative voltage, and is substantially equivalent to the HBSM which is reversely connected to the circuit, a signal of positive voltage is output to the normal HBSM, and the signal is equivalent to negative voltage output to the normal HBSM, so that the charge/discharge characteristics are opposite to those of the HBSM. Therefore, the higher-voltage HBSM (output negative level, substantially equivalent to discharge) should be preferentially applied to the positive arm current, and the lower-voltage sub-module (output negative level, substantially equivalent to charge) should be preferentially applied to the negative arm current. The judgment logic is equal to the previous one, and still the judgment logic is that the low level is charged firstly when charging and the high level is discharged firstly when discharging.
Although only 2 FBSM submodules participate in sequencing, reconstruction mapping and putting into the circuit to realize negative pressure output on the modulation wave negative half cycle, 2 FBSM and 2 HBSM participate in sequencing, reconstruction mapping and putting into the circuit to realize positive pressure output on the modulation wave positive half cycle, so that all the submodule capacitor voltages participate in a balance control link and all the submodule capacitor voltages can be balanced.
The scheme provided by the invention is verified by MATLAB/Simulink simulation software, and the simulation results are shown in FIGS. 7, 8, 9, 10, 11 and 12. The system is set to generate the short-circuit fault between direct current side poles when the system normally operates for 0.3 s. To verify the effectiveness of the proposed balancing control method, the failure time is set to last all the time. In normal operation, the FBSM is put into operation in an HBSM form, and the traditional carrier phase-shifting modulation enables the system to work smoothly. After the dc side inter-pole short circuit fault occurs for 0.3s, it can be seen from the active power waveform of fig. 7 that the output power of the dc side rapidly decreases to 0 after the transient process fluctuation, and it can be seen from fig. 9 that the dc voltage also rapidly decreases to 0. During the direct current fault period, the reactive power transmission is set to be zero, in order to maintain the balance of the bridge arm power and prevent the overvoltage of the sub-module capacitor, the alternating current controller reduces the active current instruction, so that the active power absorbed by the MMC from the alternating current system is reduced, and therefore, the fundamental frequency component of the bridge arm current is rapidly attenuated to be zero from fig. 8. Meanwhile, the direct-current component of the bridge arm current is gradually reduced to 0, and the bridge arm current before and after the fault almost has no obvious overcurrent. The FBSM mainly realizes the function of outputting negative pressure and realizes fault ride-through operation. As can be seen from the dc bus current waveform of fig. 11, the dc bus current is controlled to 0 during the dc fault. It can be seen from the waveform of the mean voltage of the sub-module capacitor in fig. 11 that the voltage stability of the sub-module capacitor can be well maintained in the whole process of the direct-current inter-electrode short-circuit fault, and the sub-module capacitor needs to absorb fault energy, so that the capacitor voltage rises at the early stage in the direct-current fault processing process, the deviation rating is 10%, and the capacitor voltage is within the bearable range of devices. Because the capacitance voltage balance control based on the reconstruction pulse of the sequencing method and the sub-module mapping is adopted in the direct-current fault ride-through period, the capacitance voltage of each sub-module can be maintained near a rated value not only in the mean value of the sub-module capacitance voltage, and the balance control of the capacitance voltage of all the sub-modules is realized. From the specific value of the capacitor voltage of the bridge arm submodule (taking the a-phase upper bridge arm as an example) in fig. 12, it can be seen that the capacitor voltage balance can be well realized among 2 HBSMs, 2 FBSMs, FBSMs and HBSM, and good capacitor consistency is maintained.
To sum up, the improved carrier phase-shifting capacitance voltage balancing method suitable for direct current fault ride through includes the following steps:
s1, when the system works normally, the traditional carrier phase shift modulation method is adopted, the modulated wave is compared with the carrier, the obtained switching pulse signals are sequentially sent to the sub-modules of each bridge arm, the carrier amplitude phases of the upper and lower bridge arms are the same, and the modulated wave is in phase reversal;
s2, after a direct current fault occurs, the voltage of a direct current bus is reduced to zero, a modulation wave is a sine wave which is equal around an X axis in positive and negative half cycles, the positive half cycle corresponds to a positive voltage output requirement, the negative half cycle corresponds to a negative voltage output requirement, and the positive half cycle and the negative half cycle are modulated independently based on different positive and negative voltage output requirements;
s3, in the modulation wave positive half cycle, the left equivalent half-bridge of HBSM and FBSM all outputs positive pressure, the positive half cycle is compared with carrier wave to obtain switch pulse signal, which is used to drive the sub-module to output positive pressure, similarly, the negative half cycle is compared with carrier wave to obtain switch pulse signal, which is used to drive the sub-module to output negative pressure;
s4, taking the capacitor voltage balance control requirement into consideration, changing the mapping relationship between the generated pulse signal and the actual sub-module, sorting the sub-module capacitor voltage values based on the carrier frequency, and dividing the switch pulse signal by the carrier frequency to complete the sample-hold function, i.e. after completing the sample-hold of the sub-module capacitor voltage and the switch pulse signal, taking the carrier frequency as a balance control period, the following situations will occur:
judging the positive and negative of the modulation wave positive and half cycle waves according to the sorting result of the capacitor voltage of the submodules and the direction of the bridge arm current, and inputting the submodules with lower voltage during charging and inputting the submodules with higher voltage during discharging;
in the modulation wave negative half cycle, only the FBSM has the negative voltage output capability, so the judgment is only carried out according to the sequencing result of the capacitor voltage of the FBSM and the positive and negative of the current direction of a bridge arm.
Since the right side of the FBSM is equivalent to a half bridge, that is, a part capable of outputting negative voltage, and is substantially equivalent to the HBSM which is reversely connected to the circuit, a signal of positive voltage is output to the normal HBSM, and the signal is equivalent to negative voltage output to the normal HBSM, so that the charge/discharge characteristics are opposite to those of the HBSM. Therefore, HBSM with higher voltage (negative level is output at the moment, and the effect is substantially equivalent to discharging) should be put into the positive bridge arm current, and a sub-module with lower voltage (negative level is output and the effect is charging) is put into the negative bridge arm current preferentially;
although only the FBSM sub-modules participate in sequencing, reconstruction mapping and putting into the circuit to realize negative pressure output on the modulation wave negative half cycle, the FBSM and the HBSM participate in sequencing, reconstruction mapping and putting into the circuit to realize positive pressure output simultaneously on the modulation wave positive half cycle, so that all sub-module capacitor voltages participate in a balance control link, and all sub-module capacitor voltages can be balanced.
On the basis of traditional carrier phase shift modulation, the method adjusts the distribution of signals between a half-bridge submodule and a full-bridge submodule, and smoothly uses the carrier phase shift to realize the direct current fault ride-through of the mixed MMC with few submodules. On the basis, based on the idea of reconstructing the mapping relation between the sub-modules and the pulse signals, the positive half cycle and the negative half cycle of the modulation wave are distinguished according to the voltage output requirement of the system, and the established distribution relation between the pulses and the sub-modules is adjusted according to a sequencing method to realize the balance of the capacitance and the voltage of the sub-modules during the period of the direct-current fault ride-through;
the distribution of signals between the half-bridge and the full-bridge submodule is adjusted based on the virtual half-bridge idea, the positive and negative half-cycles of a modulation wave are distinguished by the characteristic that the direct current bias of the modulation wave is zero during the direct current fault ride-through, the positive voltage is output by the half-bridge submodule and the virtual half-bridge on the left side of the full-bridge submodule together, the negative voltage is output by the virtual half-bridge on the right side of the full-bridge submodule, and the direct current fault ride-through of the few-submodule mixed MMC is realized by smoothly applying carrier phase shift.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, principal features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.

Claims (4)

1. An improved carrier phase-shifting capacitance voltage balancing method suitable for direct current fault ride through is characterized by comprising the following steps of:
s1, when the system works normally, the traditional carrier phase shift modulation method is adopted, the modulated wave is compared with the carrier, the obtained switching pulse signals are sequentially sent to the sub-modules of each bridge arm, the carrier amplitude phases of the upper and lower bridge arms are the same, and the modulated wave is in phase reversal;
s2, after a direct current fault occurs, the voltage of a direct current bus is reduced to zero, a modulation wave is a sine wave which is equal around an X axis in positive and negative half cycles, the positive half cycle corresponds to a positive voltage output requirement, the negative half cycle corresponds to a negative voltage output requirement, and the positive half cycle and the negative half cycle are modulated independently based on different positive and negative voltage output requirements;
s3, in the positive half cycle of the modulation wave, positive voltage is output by the left equivalent half-bridge of HBSM and FBSM, the positive half cycle is compared with the carrier wave to obtain a switching pulse signal, the switching pulse signal is used for driving the sub-module to output the positive voltage, and similarly, the negative half cycle is compared with the carrier wave to obtain a switching pulse signal, the switching pulse signal is used for driving the sub-module to output the negative voltage;
s4, the mapping relation between the generated pulse signal and the actual sub-module is changed by considering the capacitor voltage balance control requirement, the sub-module capacitor voltage values are sequenced based on the carrier frequency, and the switch pulse signal is divided by the carrier frequency to complete the sampling and holding function.
2. The method of claim 1, wherein based on conventional carrier phase shift modulation, the distribution of signals between the half-bridge and full-bridge sub-modules is adjusted to smoothly apply carrier phase shift to realize the dc fault ride-through of the fractional sub-module hybrid MMC. On the basis, based on the idea of reconstructing the mapping relation between the sub-modules and the pulse signals, the positive half cycle and the negative half cycle of the modulation wave are distinguished according to the voltage output requirement of the system, and the established distribution relation between the pulses and the sub-modules is adjusted according to a sequencing method, so that the balance of the capacitance and the voltage of the sub-modules during the DC fault ride-through period is realized.
3. The method according to claim 1, wherein the distribution of the signals between the half-bridge and the full-bridge submodule is adjusted based on a virtual half-bridge concept based on the conventional carrier phase shift modulation, the positive and negative half-cycles of the modulation wave are distinguished by using the characteristic that the modulation wave dc is biased to zero during the dc fault ride-through, the positive voltage is outputted by the half-bridge submodule and the virtual half-bridge on the left side of the full-bridge submodule, and the negative voltage is outputted by the virtual half-bridge on the right side of the full-bridge submodule, so that the dc fault ride-through of the fractional-submodule hybrid MMC is realized by smoothly applying the carrier phase shift.
4. The improved carrier phase-shifting capacitance voltage balancing method suitable for direct-current fault ride-through according to claim 1, characterized in that during the direct-current fault ride-through, in a positive half cycle wave of a modulation wave, according to a sub-module capacitance voltage result obtained by a sorting method, a sub-module with higher voltage is selected from the sub-modules to be put into use, so as to meet a positive-voltage output requirement; and selecting the full-bridge submodule to be put into use according to the submodule capacitor voltage result obtained by the sequencing method on the negative half cycle wave of the modulation wave, so as to meet the negative pressure output requirement of the system.
CN202210649039.0A 2022-06-09 2022-06-09 Improved carrier phase-shifting capacitance voltage balancing method suitable for direct-current fault ride-through Pending CN115001297A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210649039.0A CN115001297A (en) 2022-06-09 2022-06-09 Improved carrier phase-shifting capacitance voltage balancing method suitable for direct-current fault ride-through

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210649039.0A CN115001297A (en) 2022-06-09 2022-06-09 Improved carrier phase-shifting capacitance voltage balancing method suitable for direct-current fault ride-through

Publications (1)

Publication Number Publication Date
CN115001297A true CN115001297A (en) 2022-09-02

Family

ID=83033964

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210649039.0A Pending CN115001297A (en) 2022-06-09 2022-06-09 Improved carrier phase-shifting capacitance voltage balancing method suitable for direct-current fault ride-through

Country Status (1)

Country Link
CN (1) CN115001297A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115864879A (en) * 2022-12-15 2023-03-28 山东大学 Submodule grouping and sequencing method and system for hybrid MMC (Modular multilevel converter)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115864879A (en) * 2022-12-15 2023-03-28 山东大学 Submodule grouping and sequencing method and system for hybrid MMC (Modular multilevel converter)

Similar Documents

Publication Publication Date Title
Xu et al. A novel hybrid five-level voltage-source converter based on T-type topology for high-efficiency applications
KR102070554B1 (en) Charging method of submodule based hybrid converter
Cheng et al. A diode-clamped multi-level inverter for the StatCom/BESS
KR20190089053A (en) Charging method of sub module based hybrid converter
Xu et al. Active capacitor voltage control of flying capacitor multilevel converters
CN106030955A (en) Energy storage system comprising a modular multi-level converter
CN107505524A (en) Converter valve routine test circuit and test method
CN109787497B (en) Over-modulation voltage-sharing method for mixed MMC
Xu A new multilevel AC/DC topology based H-bridge alternate arm converter
CN115001297A (en) Improved carrier phase-shifting capacitance voltage balancing method suitable for direct-current fault ride-through
Xu et al. Multilevel-converter-based VSC transmission operating under fault AC conditions
CN110224622B (en) Sub-module capacitor voltage fluctuation suppression method for full-bridge modular multilevel converter
CN114553020B (en) Capacitor multiplexing type modular multilevel converter and control method thereof
CN113452276B (en) CCC-PHC type hybrid cascade direct current converter, rectifying station, inverter station and power transmission system
Zhao et al. Capacitor voltage ripples characterization and reduction of hybrid modular multilevel converter with circulating current injection
CN113258802B (en) Submodule topological structure with direct-current fault clearing and self-voltage-equalizing capabilities
Xu et al. A VSC transmission system using flying capacitor multilevel converters and selective harmonic elimination PWM control
Ghat et al. Series-Stacked hybrid modular converter with DC fault blocking capability for HVDC application
Sun et al. Research on topology and PWM control method of a novel cascaded multilevel inverter
CN113489359A (en) Submodule topology with direct-current fault clearing capability
Sun et al. Inter-arm Voltage Balance Control of a Modular Multilevel Matrix Converter with Injecting Dual Frequency Circulating Current
Tirupathi et al. A 3-phase nine-level inverter topology with improved capacitor voltage balancing method
Chang et al. PWM strategy of a novel cascaded multi-level converter for battery management
Liu et al. Research on MMC Improved Sub-module Topology with Capacitor Voltage Self-balancing
Xia et al. Control Strategy of Active Commutated Converter for HVDC transmission system under Unbalanced Grid

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination