CN115001270A - Direct current-to-direct current converter composed of four MOS (metal oxide semiconductor) tubes - Google Patents
Direct current-to-direct current converter composed of four MOS (metal oxide semiconductor) tubes Download PDFInfo
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- CN115001270A CN115001270A CN202210906658.3A CN202210906658A CN115001270A CN 115001270 A CN115001270 A CN 115001270A CN 202210906658 A CN202210906658 A CN 202210906658A CN 115001270 A CN115001270 A CN 115001270A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
A direct current-to-direct current converter composed of four MOS tubes comprises a mode selection unit M, an average current detection unit A1, an average current detection unit A2, a current regulation module C1, a current regulation module C2, an error amplifier E1, an error amplifier E2, a node selection unit R, PWM comparator U1, a PWM comparator U2, a logic control unit W, a driving unit D1, a driving unit D2, a peak current detection unit P1, a peak current detection unit P2, an MOS tube T1, an MOS tube V1, an MOS tube T2 and an MOS tube V2.
Description
Technical Field
The present invention relates to a dc-dc converter, and more particularly, to a single-chip multifunctional dc-dc converter composed of four MOS transistors.
Background
A DC-DC converter, which is a voltage converter that converts an input voltage and effectively outputs a fixed voltage, is abbreviated as a DC/DC converter, and is classified into three types: a step-up DC/DC converter, a step-down DC/DC converter, and a step-up/step-down DC/DC converter. With the development of the intelligence of electronic equipment, a DC/DC converter is crucial for the electronic equipment, the performance of the DC/DC converter directly affects the performance and stability of the intelligent equipment, and in order to satisfy multiple functions and environments, multiple outputs, multiple phases and buck-boost outputs are usually required, in the prior art, multiple DC/DC converters are usually used to implement the above functions, different converters are required to be selected corresponding to different outputs, which greatly restricts the development of the DC/DC converter, so that the DC/DC converter has various models, is not beneficial to users, and also results in more chips used in the whole circuit, higher cost and complex structure, although a part of the prior art center has a converter with integrated functions, the structure is complex, and the converter needs to be implemented by matching with more other elements during application, therefore, the design of a single-chip multifunctional DC/DC converter with a simplified structure becomes an urgent need in the industry, on the basis of the above, further improvement in stability and accuracy is also a direction of further improvement.
Disclosure of Invention
In order to solve the above technical problems at the same time, the present invention designs a dc-dc converter composed of four MOS transistors, which includes a mode selection unit M, an average current detection unit a1, an average current detection unit a2, a current regulation module C1, a current regulation module C2, an error amplifier E1, an error amplifier E2, a node selection unit R, PWM comparator U1, a PWM comparator U2, a logic control unit W, a driving unit D1, a driving unit D2, a peak current detection unit P1, a peak current detection unit P2, a MOS transistor T1, a MOS transistor V1, a MOS transistor T2, and a MOS transistor V2; the MODE selection unit M selects a signal MODE _ SEL according to an input/output MODE; two input ends of the average current detection unit a1 are respectively connected to the connection node SW1 of the MOS transistor T1 and the MOS transistor V1 and output an average current signal ICS1, and two input ends of the average current detection unit a2 are respectively connected to the connection node SW2 of the MOS transistor T2 and the MOS transistor V2 and output an average current signal ICS 2; the peak current detection unit P1 detects the drain current of the MOS transistor T1 and outputs a current signal IPCS1, and the peak current detection unit P2 detects the drain current of the MOS transistor T2 and outputs a current signal IPCS 2;
the input end of the current adjusting module C1 is connected to the current signals IPCS1, IACS1 and IACS2 respectively and outputs an average current signal ICS1, and the input end of the current adjusting module C2 is connected to the current signals IPCS2, IACS1 and IACS2 respectively and outputs an average current signal ICS 2; the input ends of the error amplifier E1 are respectively connected with a reference voltage VREF and an input signal VO1 and output an error signal EA _ OUT1, and the input end of the error amplifier E2 is respectively connected with the reference voltage VREF and an input signal VO2 and output an error signal EA _ OUT 2; the input end of the node selection unit R is respectively connected with the error signal EA _ OUT1 and the error signal EA _ OUT2 and outputs a node signal COMP1 and a node signal COMP 2; the input end of the PWM comparator U1 is respectively connected to the node signal COMP1 and the sum signal of the average current signal ICS1 and the ramp signal SC1 and outputs a first DUTY ratio signal DUTY1, and the input end of the PWM comparator U2 is respectively connected to the node signal COMP2 and the sum signal of the average current signal ICS2 and the ramp signal SC2 and outputs a second DUTY ratio signal DUTY 2;
the input end of the logic control unit W is respectively connected with the first DUTY ratio signal DUTY1, the MODE selection signal MODE _ SEL and the second DUTY ratio signal DUTY2, and outputs a first pulse width signal PWM1 and a second pulse width signal PWM 2; the input end of the driving unit D1 is connected with the first pulse width signal PWM1, and the input end of the driving unit D2 is connected with the second pulse width signal PWM 2; the gates of the MOS transistor T1 and the MOS transistor V1 are connected to two output ends of the driving unit D1, the source of the MOS transistor T1 is connected to the drain of the MOS transistor V1, and the connection node SW1 is connected to the source of the MOS transistor T1 and the drain of the MOS transistor V1; the gates of the MOS transistor T2 and the MOS transistor V2 are respectively connected to two output ends of the driving unit D2, the source of the MOS transistor T2 is connected to the drain of the MOS transistor V2, and the connection node SW2 is connected to the source of the MOS transistor T2 and the drain of the MOS transistor V2.
Preferably, a reference cell B is included for converting the power supply to the reference voltage VREF.
Preferably, an oscillator S is included, which outputs a clock signal CLK1, a ramp signal SC1, a clock signal CLK2, a ramp signal SC 2.
Preferably, the logic control unit W is selected from a single chip microcomputer.
Preferably, a first adder and a second adder are included, the input terminals of the first adder are respectively connected to the average current signal ICS1 and the signal SC1 and output a sum signal, and the input terminal of the second adder is respectively connected to the average current signal ICS2 and the signal SC2 and output a sum signal.
Preferably, the input terminals of the logic control unit W are further connected to a clock signal CLK1 and a clock signal CLK2, respectively.
Preferably, the dc-dc converter is a multifunctional single chip having a MODE pin MODE, a first power pin VIN1, a second power pin VIN2, a ground pin GND, a first output pin SW1, a second output pin SW2, a first input pin VO1 and a second input pin VO2, the MODE pin MODE serves as an input of the MODE selection unit M, the first power supply pin VIN1 is connected to the drain of the MOS transistor T1, the second power supply pin VIN2 is connected with the drain of the MOS transistor T2, the ground pin GND is connected with the sources of the MOS transistor V1 and the MOS transistor V2, the first output pin is connected with the source electrode of the MOS transistor T1 and the drain electrode of the MOS transistor V1, the second output pin is connected with the source electrode of the MOS transistor T2 and the drain electrode of the MOS transistor V2, the first input pin VO1 is connected to the negative input of the error amplifier E1, and the second input pin VO2 is connected to the negative input of the error amplifier E2.
Preferably, the MODE selection unit M selects a 2-channel operation MODE, the MODE pin MODE is grounded, the first power supply pin VIN1 and the second power supply pin VIN2 are both connected to the power supply VIN, the first output pin SW1 is connected to one end of the inductor LOUT1, the other end of the inductor LOUT1 outputs the signal VOUT1 and is connected to one end of the capacitor COUT1, the other end of the capacitor COUT1 is grounded, the second output pin SW2 is connected to one end of the inductor LOUT2, the other end of the inductor LOUT2 outputs the signal VOUT2 and is connected to one end of the capacitor COUT2, and the other end of the capacitor COUT2 is grounded.
Preferably, the MODE selecting unit M selects a 2-phase voltage reduction MODE, the MODE pin MODE is connected to a power supply VIN, the first power supply pin VIN1 and the second power supply pin VIN2 are connected to the power supply VIN, the first output pin is connected to one end of an inductor LOUT1, the other end of the inductor LOUT1 outputs a signal VOUT and is connected to one end of a capacitor COUT, the other end of the capacitor COUT is grounded, the second output pin is connected to one end of the inductor LOUT2, the other end of the inductor LOUT2 is connected to the output signal VOUT and is connected to one end of the capacitor COUT, and the other end of the capacitor COUT is grounded.
Preferably, the MODE selection unit M selects a buck-boost MODE, the MODE pin MODE is floating, the first power pin VIN1 is connected to a power supply VIN, the first output pin SW1 and the second output pin SW2 are connected through an inductor LOUT, the second power pin VIN2 outputs a signal VOUT and is connected to one end of a capacitor COUT, the other end of the capacitor COUT is grounded, and the first input pin VO1 and the second input pin VO2 are both connected to the output signal VOUT.
Has the advantages that:
1. according to the invention, through a single-chip mode, a proper working mode can be selected according to actual needs, the use environments of two-output, 2-phase single-output and voltage-increasing and decreasing modes can be simultaneously met, few external elements need to be matched, the structure and the use cost of the chip are greatly reduced, and the adaptability is strong.
2. The chip of the invention not only can realize mode selection, but also has stronger stability and higher conversion efficiency in each mode and high precision through the cooperation of the average current detection units A1 and A2, the current regulation modules C1 and C2, the error amplifiers E1 and E2, the node selection unit R, PWM comparators U1 and U2, the logic control unit W, the driving units D1 and D2, the peak current detection units P1 and P2, the MOS transistor T1, the MOS transistor V1, the MOS transistor T2 and the MOS transistor V.
Drawings
FIG. 1 is a schematic diagram of a functional module structure of a DC-DC converter according to the present invention;
FIG. 2 is a schematic diagram of the connection structure of FIG. 1 in two output modes according to the present invention;
FIG. 3 is a schematic diagram of the connection structure of FIG. 1 in a two-phase single-output mode according to the present invention;
fig. 4 is a schematic view of the connection structure of fig. 1 in the buck-boost mode according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a functional module of a dc-dc converter according to the present invention, which is in the form of a single chip and includes a mode selection unit M, an average current detection unit a1, an average current detection unit a2, a current adjustment module C1, a current adjustment module C2, an error amplifier E1, an error amplifier E2, a node selection unit R, PWM comparator U1, a PWM comparator U2, a logic control unit W, a driving unit D1, a driving unit D2, a peak current detection unit P1, a peak current detection unit P2, a MOS transistor T1, a MOS transistor V1, a MOS transistor T2, and a MOS transistor V2;
wherein, the MODE selection unit M selects a signal MODE _ SEL according to the input and output MODE; two input ends of the average current detection unit a1 are respectively connected to the connection node SW1 of the MOS transistor T1 and the MOS transistor V1 and output an average current signal ICS1, and two input ends of the average current detection unit a2 are respectively connected to the connection node SW2 of the MOS transistor T2 and the MOS transistor V2 and output an average current signal ICS 2; the peak current detection unit P1 detects the drain current of the MOS transistor T1 and outputs a current signal IPCS1, and the peak current detection unit P2 detects the drain current of the MOS transistor T2 and outputs a current signal IPCS 2;
the input end of the current adjusting module C1 is connected to the current signals IPCS1 and IACS1 respectively to output the current signal IACS2 and the average current signal ICS1, and the input end of the current adjusting module C2 is connected to the current signals IPCS2, IACS1 and IACS2 respectively and output the average current adjustment ICS 2;
the input end of the error amplifier E1 is respectively connected with a reference voltage VREF and an input signal VO1 and outputs an error signal EA _ OUT1, and the input end of the error amplifier E2 is respectively connected with the reference voltage VREF and an input signal VO2 and outputs an error signal EA _ OUT 2;
the input end of the node selection unit R is respectively connected with the error signal EA _ OUT1 and the error signal EA _ OUT2 and outputs a node signal COMP1 and a node signal COMP 2; the input end of the PWM comparator U1 is respectively connected to the node signal COMP1 and the sum signal of the average current signal ICS1 and the ramp signal SC1 and outputs a first DUTY ratio signal DUTY1, and the input end of the PWM comparator U2 is respectively connected to the node signal COMP2 and the sum signal of the average current signal ICS2 and the ramp signal SC2 and outputs a second DUTY ratio signal DUTY 2;
the input end of the logic control unit W is respectively connected with the first DUTY ratio signal DUTY1, the MODE selection signal MODE _ SEL and the second DUTY ratio signal DUTY2, and outputs a first pulse width signal PWM1 and a second pulse width signal PWM 2; the input end of the driving unit D1 is connected with the first pulse width signal PWM1, and the input end of the driving unit D2 is connected with the second pulse width signal PWM 2; the gates of the MOS transistor T1 and the MOS transistor V1 are connected to two output ends of the driving unit D1, the source of the MOS transistor T1 is connected to the drain of the MOS transistor V1, and the connection node SW1 is connected to the source of the MOS transistor T1 and the drain of the MOS transistor V1; the gates of the MOS transistor T2 and the MOS transistor V2 are respectively connected to two output ends of the driving unit D2, the source of the MOS transistor T2 is connected to the drain of the MOS transistor V2, and the connection node SW2 is connected to the source of the MOS transistor T2 and the drain of the MOS transistor V2. Further, a reference unit B is included for converting the voltage at the first power supply pin to a reference voltage VREF, which is designed according to the comparison of the error amplifier based on VREF; further, an oscillator S is included, which outputs a clock signal CLK1, a ramp signal SC1, a clock signal CLK2, and a ramp signal SC 2.
Further, the logic control unit W is selected from a single chip microcomputer; further, a first adder and a second adder are included, wherein the input terminals of the first adder are respectively connected to the average current signal ICS1 and the ramp signal SC1 and output a sum signal, and the input terminals of the second adder are respectively connected to the average current signal ICS2 and the ramp signal SC2 and output a sum signal; further, the input terminals of the logic control unit W are also respectively connected to the clock signal CLK1 and the clock signal CLK 2.
The dc-dc converter of the present invention is a multifunctional single chip, i.e. in the form of a single chip package, which includes a plurality of functional pins, specifically, the single chip has a MODE pin MODE, a first power pin VIN1, a second power pin VIN2, a ground pin GND, a first output pin SW1, a second output pin SW2, a first input pin VO1, and a second input pin VO2, the MODE pin MODE is used as an input of the MODE selection unit M, the first power pin VIN1 is connected to the drain of the MOS transistor T1, the second power pin VIN2 is connected to the drain of the MOS transistor T2, the ground pin GND is connected to the sources of the MOS transistor V1 and the MOS transistor V2, the first output pin is connected to the source of the MOS transistor T1 and the drain of the MOS transistor V1, the second output pin is connected to the source of the MOS transistor T2 and the drain of the MOS transistor V2, the first input pin 1 is connected to the negative input terminal of the error amplifier VO1, the second input pin VO2 is connected to the negative input of the error amplifier E2.
Based on the single chip, the present invention can implement three different MODEs by different connection MODEs for different pins, specifically, the MODE selection unit M selects a 2-channel operation MODE, the MODE pin MODE is grounded, the first power supply pin VIN1 and the second power supply pin VIN2 are both connected to the power supply VIN, the first output pin SW1 is connected to one end of the inductor LOUT1, the other end of the inductor LOUT1 outputs the signal VOUT1 and is connected to one end of the capacitor COUT1, the other end of the capacitor COUT1 is grounded, the second output pin SW2 is connected to one end of the inductor LOUT2, the other end of the inductor LOUT2 outputs the signal VOUT2 and is connected to one end of the capacitor COUT2, and the other end of the capacitor COUT2 is grounded.
Further, the MODE selection unit M selects a 2-phase step-down MODE, the MODE pin MODE is connected to the power supply VIN, the first power supply pin VIN1 and the second power supply pin VIN2 are connected to the power supply VIN, the first output pin SW1 is connected to one end of the inductor LOUT1, the other end of the inductor LOUT1 outputs a signal VOUT1 and is connected to one end of the capacitor COUT1, the other end of the capacitor COUT1 is grounded, the second output pin SW2 is connected to one end of the inductor LOUT2, the other end of the inductor LOUT2 is connected to the output signal VOUT2 and is connected to one end of the capacitor COUT2, and the other end of the capacitor COUT2 is grounded.
Further, the MODE selection unit M selects a buck-boost MODE, the MODE pin MODE is floating, the first power pin VIN1 is connected to the power supply VIN, the first output pin SW1 and the second output pin SW2 are connected through an inductor LOUT, the second power pin VIN2 outputs a signal VOUT and is connected to one end of a capacitor COUT, the other end of the capacitor COUT is grounded, and the first input pin VO1 and the second input pin VO2 are both connected to the output signal VOUT.
In summary, the present invention can realize different functions on one chip through the specific structural arrangement of the multifunctional single chip, that is, can select a suitable operation mode according to actual needs, can simultaneously satisfy the use environments of two-output, 2-phase single-output and buck-boost modes, requires few external components to be matched, greatly reduces the structure and use cost of the chip, has strong adaptability, and the chip can realize mode selection through the matching of the average current detection units a1 and a2, the current regulation modules C1 and C2, the error amplifiers E1 and E2, the node selection unit R, PWM comparators U1 and U2, the logic control unit W, the driving units D1 and D2, the peak current detection units P1 and P2, the MOS transistor T1, the MOS transistor V1, the MOS transistor T2 and the MOS transistor V, and has strong stability and high conversion efficiency in each mode, the precision is high.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of simplicity of description, all possible combinations of the technical features in the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the technical features should be considered as the scope of description in the present specification.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A DC-DC converter composed of four MOS tubes is characterized in that: the circuit comprises a mode selection unit M, an error amplifier E1, an error amplifier E2, a node selection unit R, PWM, a comparator U1, a PWM comparator U2, a logic control unit W, MOS, a transistor T1, a transistor V1, a transistor T2 and a transistor V2;
the MODE selection unit M selects a signal MODE _ SEL according to an input/output MODE;
the input end of the error amplifier E1 is respectively connected with a reference voltage VREF and an input signal VO1 and outputs an error signal EA _ OUT1, and the input end of the error amplifier E2 is respectively connected with the reference voltage VREF and an input signal VO2 and outputs an error signal EA _ OUT 2;
the input end of the node selection unit R is respectively connected with the error signal EA _ OUT1 and the error signal EA _ OUT2 and outputs a node signal COMP1 and a node signal COMP 2;
the input end of the PWM comparator U1 is connected to the node signal COMP1, the sum signal of the average current signal ICS1 and the ramp signal SC1 respectively and outputs a first DUTY ratio signal DUTY1, and the input end of the PWM comparator U2 is connected to the node signal COMP2, the sum signal of the average current signal ICS2 and the ramp signal SC2 respectively and outputs a second DUTY ratio signal DUTY 2;
the input end of the logic control unit W is respectively connected with the first DUTY ratio signal DUTY1, the MODE selection signal MODE _ SEL and the second DUTY ratio signal DUTY2, and outputs a first pulse width signal PWM1 and a second pulse width signal PWM 2;
the gates of the MOS transistor T1 and the MOS transistor V1 are connected with two output ends of a driving unit D1, the source of the MOS transistor T1 is connected with the drain of the MOS transistor V1, and a connection node SW1 is connected with the source of the MOS transistor T1 and the drain of the MOS transistor V1;
the gates of the MOS transistor T2 and the MOS transistor V2 are respectively connected to two output ends of the driving unit D2, the source of the MOS transistor T2 is connected to the drain of the MOS transistor V2, and the connection node SW2 is connected to the source of the MOS transistor T2 and the drain of the MOS transistor V2.
2. The converter of claim 1, wherein: the reference unit B is used for converting a power supply into a reference voltage VREF; the device comprises an average current detection unit A1 and an average current detection unit A2, wherein two input ends of the average current detection unit A1 are respectively connected with a connection node SW1 of a MOS tube T1 and a MOS tube V1 and output an average current signal ICS1, and two input ends of the average current detection unit A2 are respectively connected with a connection node SW2 of the MOS tube T2 and a MOS tube V2 and output an average current signal ICS 2.
3. The converter of claim 2, wherein: the circuit comprises an oscillator S, wherein the oscillator S outputs a clock signal CLK1, a ramp signal SC1, a clock signal CLK2 and a ramp signal SC 2; the current regulation module C2 is included, and the current regulation module C1 has inputs of C1 respectively connected to current signals IPCS1, IACS1 and IACS2 and outputting average current signal ICS1, and inputs of C2 respectively connected to current signals IPCS2, IACS1 and IACS2 and outputting average current signal ICS 2.
4. A converter according to claim 3, wherein: the logic control unit W is selected from a single chip microcomputer, and further comprises a driving unit D1 and a driving unit D2, wherein the input end of the driving unit D1 is connected with the first pulse width signal PWM1, and the input end of the driving unit D2 is connected with the second pulse width signal PWM 2.
5. The converter of claim 4, wherein: the adder comprises a first adder and a second adder, wherein the input end of the first adder is respectively connected with the average current signal ICS1 and the ramp signal SC1 and outputs a sum signal, and the input end of the second adder is respectively connected with the average current signal ICS2 and the ramp signal SC2 and outputs a sum signal.
6. The converter of claim 5, wherein: the input ends of the logic control unit W are also respectively connected with a clock signal CLK1 and a clock signal CLK 2; the current detection circuit further comprises a peak current detection unit P1 and a peak current detection unit P2, wherein the peak current detection unit P1 detects the drain current of the MOS transistor T1 and outputs a current signal IPCS1, and the peak current detection unit P2 detects the drain current of the MOS transistor T2 and outputs a current signal IPCS 2.
7. The converter according to any one of claims 1-6, wherein: the dc-dc converter is a multifunctional single chip having a MODE pin MODE, a first power pin VIN1, a second power pin VIN2, a ground pin GND, a first output pin SW1, a second output pin SW2, a first input pin VO1 and a second input pin VO2, the MODE pin MODE serves as an input of the MODE selection unit M, the first power supply pin VIN1 is connected to the drain of the MOS transistor T1, the second power supply pin VIN2 is connected with the drain of the MOS transistor T2, the ground pin GND is connected with the sources of the MOS transistor V1 and the MOS transistor V2, the first output pin SW1 is connected to the source of the MOS transistor T1 and the drain of the MOS transistor V1, the second output pin SW2 is connected to the source of the MOS transistor T2 and the drain of the MOS transistor V2, the first input pin VO1 is connected to the negative input terminal of the error amplifier E1, and the second input pin VO2 is connected to the negative input terminal of the error amplifier E2.
8. The converter of claim 7, wherein: the MODE selection unit M selects a 2-channel operation MODE, the MODE pin MODE is grounded, the first power supply pin VIN1 and the second power supply pin VIN2 are connected to the power supply VIN, the first output pin SW1 is connected to one end of the inductor LOUT1, the other end of the inductor LOUT1 outputs a signal VOUT1 and is connected to one end of the capacitor COUT1, the other end of the capacitor COUT1 is grounded, the second output pin SW2 is connected to one end of the inductor LOUT2, the other end of the inductor LOUT2 outputs a signal VOUT2 and is connected to one end of the capacitor COUT2, and the other end of the capacitor COUT2 is grounded.
9. The converter of claim 7, wherein: the MODE selection unit M selects a 2-phase voltage reduction MODE, the MODE pin MODE is connected to a power supply VIN, the first power supply pin VIN1 and the second power supply pin VIN2 are connected to the power supply VIN, the first output pin SW1 is connected to one end of an inductor LOUT1, the other end of the inductor LOUT1 outputs a signal VOUT1 and is connected to one end of a capacitor COUT1, the other end of the capacitor COUT1 is grounded, the second output pin SW2 is connected to one end of an inductor LOUT2, the other end of the inductor LOUT2 outputs a signal VOUT2 and is connected to one end of the capacitor COUT2, and the other end of the capacitor COUT2 is grounded.
10. The converter of claim 7, wherein: the MODE selection unit M selects a buck-boost MODE, the MODE pin MODE is in a floating connection, the first power supply pin VIN1 is connected to a power supply VIN, the first output pin SW1 and the second output pin SW2 are connected through an inductor LOUT, the second power supply pin VIN2 outputs a signal VOUT and is connected to one end of a capacitor COUT, the other end of the capacitor COUT is grounded, and the first input pin VO1 and the second input pin VO2 are both connected to the output signal VOUT.
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| CN202210906658.3A CN115001270B (en) | 2022-07-29 | 2022-07-29 | Direct current-to-direct current converter composed of four MOS (metal oxide semiconductor) tubes |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6025706A (en) * | 1998-08-21 | 2000-02-15 | Fujitsu Limited | Method for controlling the output voltage of a DC-DC converter |
| US20050088151A1 (en) * | 2003-10-22 | 2005-04-28 | Guang-Nan Tzeng | Switching dc-to-dc converter with multiple output voltages |
| US20080089101A1 (en) * | 2005-09-16 | 2008-04-17 | International Rectifier Corporation | Multi-phase converter with improved current sharing |
| DE102010049009A1 (en) * | 2010-10-21 | 2012-04-26 | Texas Instruments Deutschland Gmbh | Electronic device and method for DC-DC conversion |
| US20150054482A1 (en) * | 2013-08-23 | 2015-02-26 | Magnachip Semiconductor, Ltd. | Current controlling mode direct current (dc)-dc converter |
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2022
- 2022-07-29 CN CN202210906658.3A patent/CN115001270B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6025706A (en) * | 1998-08-21 | 2000-02-15 | Fujitsu Limited | Method for controlling the output voltage of a DC-DC converter |
| US20050088151A1 (en) * | 2003-10-22 | 2005-04-28 | Guang-Nan Tzeng | Switching dc-to-dc converter with multiple output voltages |
| US20080089101A1 (en) * | 2005-09-16 | 2008-04-17 | International Rectifier Corporation | Multi-phase converter with improved current sharing |
| DE102010049009A1 (en) * | 2010-10-21 | 2012-04-26 | Texas Instruments Deutschland Gmbh | Electronic device and method for DC-DC conversion |
| US20150054482A1 (en) * | 2013-08-23 | 2015-02-26 | Magnachip Semiconductor, Ltd. | Current controlling mode direct current (dc)-dc converter |
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| CN115001270B (en) | 2022-10-21 |
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