CN115001265A

CN115001265A - Switched capacitor type power conversion circuit and control method thereof

Info

Publication number: CN115001265A
Application number: CN202110225820.0A
Authority: CN
Inventors: 蔡育筑
Original assignee: UPI Semiconductor Corp
Current assignee: UPI Semiconductor Corp
Priority date: 2021-03-01
Filing date: 2021-03-01
Publication date: 2022-09-02

Abstract

A switched capacitor power conversion circuit and a control method thereof are provided. The output stage comprises a first switching circuit to a fourth switching circuit which are connected in series. A first node is between the first and second switch circuits. A second node is between the second and third switch circuits. And a third node is arranged between the third switching circuit and the fourth switching circuit. The first capacitor is coupled between the first and third nodes. The second capacitor is coupled between the second node and the ground voltage. The control circuit is coupled to the first node, the third node, the second switch circuit and the fourth switch circuit, and operates the second switch circuit according to the voltage of the first node from the first node and operates the fourth switch circuit according to the voltage of the third node from the third node, so that the voltages at two ends of the first capacitor are the same as the voltages at two ends of the second capacitor. The invention can avoid the large current generated at the switching moment of the second operation to burn out the switch circuit in the output stage, thereby improving the operation reliability of the switching capacitance type power supply switching circuit.

Description

Switched capacitor type power conversion circuit and control method thereof

Technical Field

The present invention relates to a switching capacitor type power conversion circuit, and more particularly, to a switching capacitor type power conversion circuit and a control method thereof.

Background

Referring to fig. 1, fig. 1 is a schematic diagram of an output stage of a conventional switched capacitor power conversion circuit.

As shown in fig. 1, the output stage 1 of the switched-capacitor power conversion circuit includes first to fourth switch circuits SW1 to SW4, first to fourth parasitic diodes D1 to D4, and first to second capacitors C1 to C2. The first switch circuit SW1 to the fourth switch circuit SW4 are connected in series between the input voltage VIN and the ground voltage GND. The first to fourth diodes D1 to D4 are connected in series between the input voltage VIN and the ground voltage GND.

One terminal of the first capacitor C1 is coupled to the node NA. The node NA is located between the first switch circuit SW1 and the second switch circuit SW 2. Node NA has a node voltage VNA. The other end of the first capacitor C1 is coupled to the node NB. The node NB is located between the third switch circuit SW3 and the fourth switch circuit SW4. Node NB has a node voltage VNB. The output voltage VOUT is provided between the second switch circuit SW2 and the third switch circuit SW 3. One end of the second capacitor C2 is coupled to the output voltage VOUT and the other end of the second capacitor C2 is coupled to the ground voltage GND.

Generally, when the output stage 1 of the switched capacitor power conversion circuit is controlled by a control signal to be in an operation mode, there are two different operation phases: in the first operation phase, the first switch circuit SW1 and the third switch circuit SW3 are turned on (Turn-on) so that the first capacitor C1 and the second capacitor C2 are connected in series to each other to operate in the series mode; in the second operation phase, the second switch circuit SW2 and the fourth switch circuit SW4 are turned on, so that the first capacitor C1 and the second capacitor C2 are connected in parallel to each other to operate in the parallel mode.

However, in practical applications, if the voltages at the two ends of the first capacitor C1 and the second capacitor C2 are different from each other, and the two ends are switched to the second operation phase, when the first capacitor C1 and the second capacitor C2 are connected in parallel, a large instantaneous current (Inrush current) is generated on the second switch circuit SW2 and the fourth switch circuit SW4, which may cause the second switch circuit SW2 and/or the fourth switch circuit SW4 to be burned out. This problem remains to be solved further.

Disclosure of Invention

In view of the above, the present invention provides a switching capacitor type power conversion circuit and a control method thereof to effectively solve the above problems encountered in the prior art.

An embodiment of the present invention is a switched capacitor power conversion circuit. In this embodiment, the switched capacitor power conversion circuit includes an output stage, a first capacitor, a second capacitor, and a control circuit. The output stage comprises a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit which are connected in series, wherein a first node is arranged between the first switch circuit and the second switch circuit, a second node is arranged between the second switch circuit and the third switch circuit, and a third node is arranged between the third switch circuit and the fourth switch circuit. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the second node and the ground voltage. The control circuit is coupled to the first node, the third node, the second switch circuit and the fourth switch circuit. The control circuit operates the second switch circuit according to a first node voltage from the first node, and operates the fourth switch circuit according to a third node voltage from the third node, so that voltages at two ends of the first capacitor are the same as voltages at two ends of the second capacitor.

In one embodiment, the control circuit further determines whether the first node voltage is equal to a first reference voltage and determines whether the third node voltage is equal to a second reference voltage.

In one embodiment, the control circuit is further coupled to the pwm signal generator. The control circuit enables the pulse width modulation signal generator according to a first node voltage of the first node, a first reference voltage, a third node voltage of the third node and a second reference voltage.

In one embodiment, the control circuit includes a first comparator and a second comparator. The first comparator has an input terminal coupled to the first node for receiving the first node voltage and another input terminal for receiving the first reference voltage, and an output terminal for outputting a first comparison signal for operating the second switch circuit. An input terminal of the second comparator is coupled to the third node for receiving the third node voltage, and another input terminal thereof receives the second reference voltage.

In one embodiment, the control circuit further comprises a logic gate. The logic gates are respectively coupled to the output ends of the first comparator and the second comparator, and are used for generating a balance signal according to the first comparison signal and the second comparison signal so as to control the power conversion circuit to enter an operation mode.

In an embodiment, the switched capacitor power conversion circuit further includes a pwm signal generator coupled to the control circuit, and when the control circuit determines that the voltages at the two ends of the first capacitor are the same as the voltages at the two ends of the second capacitor, the control circuit enables the pwm signal generator.

Another embodiment of the present invention is a control method for a switched capacitor power conversion circuit. In this embodiment, the switched capacitor power conversion circuit includes an output stage, a first capacitor, and a second capacitor. The output stage comprises a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit which are connected in series. A first node is arranged between the first switch circuit and the second switch circuit. A second node is arranged between the second switch circuit and the third switch circuit. And a third node is arranged between the third switching circuit and the fourth switching circuit. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the second node and the ground voltage. The control method comprises the following steps: (a) operating a second switch circuit according to a first node voltage of the first node; (b) operating a fourth switching circuit according to a third node voltage of the third node; and (c) making the voltage at two ends of the first capacitor the same as the voltage at two ends of the second capacitor.

In one embodiment, the step (a) further includes (a1) determining whether the first node voltage is equal to the first reference voltage and the step (b) further includes (b1) determining whether the third node voltage is equal to the second reference voltage.

In an embodiment, the control method further includes: (d) generating a balance signal according to the determination results of the steps (a1) and (b 1).

In an embodiment, the control method further includes: (e) the PWM signal is generated to the output stage according to the balance signal to control the output stage to enter an operation mode.

Compared with the prior art, the switched capacitor power conversion circuit and the control method thereof operate the second switch circuit according to the node voltage between the first switch circuit and the second switch circuit in the output stage and operate the fourth switch circuit according to the node voltage between the third switch circuit and the fourth switch circuit before the first capacitor and the second capacitor are connected in parallel, so that the voltage at two ends of the first capacitor and the voltage at two ends of the second capacitor are mutually the same and then switched to the second operation phase in which the first capacitor and the second capacitor are connected in parallel, thereby effectively avoiding the large current generated at the moment of switching the second operation phase from burning the switch circuit in the output stage, and improving the operation reliability of the switched capacitor power conversion circuit.

The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings.

Drawings

Fig. 1 is a schematic diagram of an output stage of a conventional switched capacitor power conversion circuit.

Fig. 2 is a schematic diagram of a switched-capacitor power conversion circuit according to an embodiment of the invention.

Fig. 3 is a schematic diagram of an embodiment of an enable detection signal generating circuit.

Fig. 4 is a schematic diagram of an embodiment of an output stage of a switched capacitor power conversion circuit.

Fig. 5 is a schematic diagram of another embodiment of the second switch circuit/the fourth switch circuit in the output stage of the switched capacitor power converter circuit.

Fig. 6A and 6B are waveform timing diagrams of an abnormal condition encountered in an output stage of a switched capacitor power conversion circuit according to the prior art and the present invention, respectively.

Fig. 7A and 7B are waveform timing diagrams of the output stage of the switched capacitor power conversion circuit according to the prior art and the present invention, respectively, when another abnormal condition occurs.

Fig. 8 is a flowchart of a control method of a switched capacitor power conversion circuit according to another embodiment of the invention.

Description of the main element symbols:

an output stage

SW 1-SW4

D1-D4.

C1-C2.

Output voltage

An input voltage

Ground voltage

VD.. diode voltage

NA-NB.

VNA-VNB

Switching capacitor type power supply conversion circuit

OS.. output stage

DC

Generator for pulse width modulation signal

N1.. first node

N2

N3.. third node

SW 21-SW22

SW 41-SW42

AH.. first comparison signal

BH.. second comparison signal

A first comparator

Second comparator

NOR

+.. input end

An input end

A first node voltage

Vref1

Vn3

Vref2

Balancing signals

Voltage across first capacitor

Voltage across the second capacitor

PWM

Enable a detection signal

Enable detection signal generation circuit

Input end of S, R

Output end of Q

Power ready signal

An output stage

Current flowing through the first capacitor

Current flowing through the second capacitor

Second/fourth switch circuit

A current source

R

time t 0-t3.

S10-S14

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. The same or similar numbered elements/components used in the drawings and the embodiments are used to represent the same or similar parts.

An embodiment of the present invention is a switched capacitor power conversion circuit. Referring to fig. 2, fig. 2 is a schematic diagram of a switched capacitor power conversion circuit in this embodiment. As shown in fig. 2, the switched capacitor power converter circuit 2 includes an output stage OS, a first capacitor C1, a second capacitor C2, a control circuit DC, and a pwm signal generator PG.

The output stage OS includes a first switch circuit SW1, a second switch circuit SW2, a third switch circuit SW3 and a fourth switch circuit SW4 connected in series between the input voltage VIN and the ground voltage GND. The first switch circuit SW1 and the second switch circuit SW2 have a first node N1 therebetween. The second switch circuit SW2 and the third switch circuit SW3 have a second node N2 therebetween. The third switching circuit SW3 and the fourth switching circuit SW4 have a third node N3 therebetween.

The second switch circuit SW2 includes switches SW21 and SW22. The switch SW21 is coupled between the first node N1 and the second node N2. The switch SW22 is a transistor coupled between the first node N1 and the second node N2 and has a control terminal controlled by the first comparison signal AH. The fourth switch circuit SW4 includes switches SW41 and SW42. The switch SW41 is coupled between the third node N3 and the ground voltage GND. The switch SW42 is a transistor coupled between the third node N3 and the ground voltage GND, and its control terminal is controlled by the second comparison signal BH.

Two ends of the first capacitor C1 are coupled to the first node N1 and the third node N3, respectively. Two ends of the second capacitor C2 are coupled to the second node N2 and the ground voltage GND, respectively. The control circuit DC is coupled to the first node N1, the third node N3, the second switch circuit SW2, the fourth switch circuit SW4 and the pwm signal generator PG, respectively.

The control circuit DC includes a first comparator CP1, a second comparator CP2 and a logic gate NOR. An input of the first comparator CP1 is coupled to the first node N1 to receive the first node voltage VN1. The input terminal + of the first comparator CP1 receives a first reference voltage VREF1. The output terminal of the first comparator CP1 outputs a first comparison signal AH. An input of the second comparator CP2 is coupled to the third node N3 to receive the third node voltage VN3. The input terminal + of the second comparator CP2 receives a second reference voltage VREF2. An output terminal of the second comparator CP2 outputs a second comparison signal BH.

In detail, the first comparator CP1 compares the first node voltage VN1 of the first node N1 with the first reference voltage VREF1 to determine whether the first node voltage VN1 of the first node N1 is equal to the first reference voltage VREF1. In this embodiment, the first reference voltage VREF1 is equal to the output voltage VOUT plus the turn-on threshold voltage (threshold) of the switch SW22. In some applications, the first reference voltage VREF1 may also be equal to the output voltage VOUT.

When the first node voltage VN1 of the first node N1 is not equal to the first reference voltage VREF1, the first comparator CP1 outputs a first comparison signal AH having a High level (High-level) to turn on the switch SW22. When the first node voltage VN1 of the first node N1 is equal to the first reference voltage VREF1, the first comparator CP1 outputs the first comparison signal AH having a Low level (Low-level).

Similarly, the second comparator CP2 compares the third node voltage VN3 of the third node N3 with the second reference voltage VREF2 to determine whether the third node voltage VN3 of the third node N3 is equal to the second reference voltage VREF2. In this embodiment, the second reference voltage VREF2 is equal to the ground voltage GND plus the turn-on threshold voltage of the switch SW42. In some applications, the second reference voltage VREF2 may also be equal to the ground voltage GND.

When the third node voltage VN3 of the third node N3 is not equal to the second reference voltage VREF2, the second comparator CP2 outputs the second comparison signal BH having a High level (High-level) to turn on the switch SW42. When the third node voltage VN3 of the third node N3 is equal to the second reference voltage VREF2, the second comparator CP2 outputs the second comparison signal BH having a Low level (Low-level).

Two input terminals of the logic gate NOR are respectively coupled to the output terminal of the first comparator CP1 and the output terminal of the second comparator CP2, and an output terminal of the logic gate NOR is coupled to the pwm signal generator PG. The two input terminals of the logic gate NOR respectively receive the first comparison signal AH and the second comparison signal BH and generate the balance signal BAL to the pwm signal generator PG according to the first comparison signal AH and the second comparison signal BH.

In practical applications, the logic gate NOR is an inverted or gate (NOR gate). Only when the first comparison signal AH and the second comparison signal BH received by the logic gate NOR are both Low-level (Low-level), that is, both conditions that the first node voltage VN1 of the first node N1 is equal to the first reference voltage VREF1 and the third node voltage VN3 of the third node N3 is equal to the second reference voltage VREF2 are satisfied, which means that the voltage VC1 at the two ends of the first capacitor C1 is the same as the voltage VC2 at the two ends of the second capacitor C2, the logic gate NOR outputs the balance signal BAL with High-level (High-level) to the pwm signal generator PG. When the PWM signal generator PG receives the balance signal BAL with a high level, the PWM signal generator PG controls the output stage OS by generating the PWM signal PWM, so as to enter an operation mode.

In other cases, since the two conditions that the first node voltage VN1 at the first node N1 is equal to the first reference voltage VREF1 and the third node voltage VN3 at the third node N3 is equal to the second reference voltage VREF2 are not satisfied at the same time, that is, the two-terminal voltage VC1 of the first capacitor C1 is different from the two-terminal voltage VC2 of the second capacitor C2, the logic gate NOR outputs the balance signal BAL with a Low level (Low-level) to the pwm signal generator PG. When the pwm signal generator PG receives the balance signal BAL having a low level, the pwm signal generator PG is not enabled, and the output stage OS does not enter the operation mode.

Before entering the operation mode, the first switch circuit SW1, the switch SW21 of the second switch circuit SW2, the third switch circuit SW3 and the switch SW41 of the fourth switch circuit SW4 connected in series with each other in the output stage OS are all in an off (Turn-off) state. The control terminal of the switch SW22 of the second switch circuit SW2 is controlled by the first comparison signal AH output by the first comparator CP1. A control terminal of the switch SW42 of the fourth switching circuit SW4 is controlled by the second comparison signal BH output by the second comparator CP2.

In addition, while the PWM signal PWM controls the output stage OS to enter the operation mode, the first comparator CP1 and the second comparator CP2 in the control circuit DC are disabled by the enable detection signal END, so as to prevent the first comparator CP1 and the second comparator CP2 from malfunctioning in the operation mode and affecting the normal operation of the output stage OS.

For example, as shown in fig. 3, two input terminals S and R of the enable detection signal generating circuit 3 respectively receive a Power ready (Power ready) signal POR and a balance signal BAL from the outside, and an output terminal Q of the enable detection signal generating circuit 3 outputs an enable detection signal END. In this embodiment, the enable detection signal END output by the enable detection signal generation circuit 3 is triggered by the power ready signal POR and is turned off by the balance signal BAL, but not limited thereto. The enable detection signal END may also be generated by the balance signal BAL through an inverter.

Next, referring to fig. 4, fig. 4 is a schematic diagram of an output stage of a switched capacitor power conversion circuit according to an embodiment of the invention.

As shown in fig. 4, the output stage 4 of the switched-capacitor power conversion circuit includes a first switch circuit SW1, a second switch circuit SW2, a third switch circuit SW3 and a fourth switch circuit SW4. The first switch circuit SW1, the second switch circuit SW2, the third switch circuit SW3 and the fourth switch circuit SW4 are connected in series between the input voltage VIN and the ground voltage GND. The first switch circuit SW1 and the second switch circuit SW2 have a first node N1 therebetween. The second switch circuit SW2 and the third switch circuit SW3 have a second node N2 therebetween. The third switch circuit SW3 and the fourth switch circuit SW4 have a third node N3 therebetween. A first capacitor C1 is coupled between the first node N1 and the third node N3. The voltage across the first capacitor C1 is VC1 and the current flowing through the first capacitor C1 is IC1. A second capacitor C2 is coupled between the second node N2 and the ground voltage GND. The voltage across the second capacitor C2 is VC2 and the current flowing through the second capacitor C2 is IC2.

It should be noted that the transistor switch SW22 of the second switch circuit SW2 is used as a discharge switch, which is turned on by the first comparison signal AH to discharge the first node N1. In fact, since the transistor switch SW22 as the discharge switch is usually connected in series with a large resistance (or a high on-resistance), a large current is not generated at the moment the transistor switch SW22 is turned on, and thus the switch can be effectively prevented from being burned.

Similarly, the transistor switch SW42 of the fourth switch circuit SW4 is used as a discharge switch, which is turned on by the second comparison signal BH to discharge the third node N3. In fact, since the transistor switch SW42 as a discharge switch is usually connected in series with a large resistance (or a high on-resistance), a large current is not generated at the moment when the transistor switch SW42 is turned on, and thus the switch can be effectively prevented from being burned out.

The control circuit DC operates the second switch circuit SW2 to be conductive according to the first node voltage VN1 from the first node N1, and operates the fourth switch circuit SW4 to be conductive according to the third node voltage VN3 from the third node N3, so that the voltage VC1 across the first capacitor C1 is the same as the voltage VC2 across the second capacitor C2.

In another embodiment, as shown in fig. 5, in the output stage of the switched-capacitor power conversion circuit, the second switch circuit/the fourth switch circuit 5 includes a current source 50, a resistor R, and switches SW2/SW 4. The switches SW2/SW4 are transistors and also function as discharge switches. One terminal of the resistor R is coupled to the current source 50 and the other terminal of the resistor R is coupled to the control terminal of the switch SW2/SW 4. The control terminals of the switches SW2/SW4 are controlled by the PWM signal PWM. When the first node N1/the third node N3 needs to be discharged, the current source 50 is activated by the first comparison signal AH/the second comparison signal BH to provide a small current to the control terminal of the switch SW2/SW4, so that the switch SW2/SW4 is turned on slightly (i.e. the transistor operates in a linear region) to discharge the first node N1/the third node N3 and no large current is generated to cause the switch to be burned out.

Next, a comparison and a description will be made between the prior art and an embodiment of the present invention in which the output stage of the switched capacitor power conversion circuit encounters different abnormal conditions.

Referring to fig. 6A and 6B, fig. 6A and 6B are waveform timing diagrams of an abnormal condition encountered by an output stage of a switched capacitor power conversion circuit according to the prior art and the present invention, respectively. The abnormal condition in this embodiment is (1/2) the input voltage VIN > the first node voltage VN1 at the first node N1> the output voltage VOUT and the third node voltage VN3 at the third node N3 ≦ the ground voltage GND.

As shown in fig. 6A, when the switching capacitor type power conversion circuit of the prior art encounters the above abnormal condition, since the node voltage VNA of the node NA is higher than the output voltage VOUT, the first capacitor current IC1 flowing through the first capacitor C1 and the second capacitor current IC2 flowing through the second capacitor C2 both increase instantly when switching to the second operation phase at time t1 in order to balance the node voltage VNA of the node NA.

As shown in fig. 6B, when the switched-capacitor power conversion circuit of the present invention encounters the above abnormal condition, at time t0, the enable detection signal END is triggered by the power ready signal POR to change from the low level to the high level, since the first node voltage VN1 of the first node N1 is higher than the output voltage VOUT and the third node voltage VN3 of the third node N3 is equal to the ground voltage GND, only the first comparison signal AH changes from the low level to the high level to discharge the first node voltage VN1 of the first node N1, and the third node voltage VN3 of the third node N3 and the second comparison signal BH remain unchanged.

At time t1, the first node voltage VN1 of the first node N1 has discharged to be the same as the output voltage VOUT, so that the first comparison signal AH changes from high level to low level. At this time, since the third node voltage VN3 of the third node N3 is equal to the ground voltage GND, the second comparison signal BH is also at a low level. At this time, the balance signal BAL changes from low level to high level, the pwm signal generator PG is enabled, the capacitive power conversion circuit is switched to the operating mode, the output stage OS enters the second operating phase (i.e., the second switch circuit SW2 and the fourth switch circuit SW4 are kept turned on, so that the first capacitor C1 and the second capacitor C2 are connected in parallel), and the enable detection signal END changes from high level to low level, so that the first comparator CP1 and the second comparator CP2 in the control circuit DC are disabled, and at the same time, the output voltage VOUT starts to be precharged.

At time t2, when the output voltage VOUT is precharged to (1/2) the output voltage VOUT, this embodiment also reserves a delay time between time t2 and time t3 for other functional circuits to operate. In other embodiments, the switched capacitor power conversion circuit can omit the delay time and directly perform the power conversion operation.

At time t3, complementary switching between the first switch circuit SW 1/the third switch circuit SW3 and the second switch circuit SW 2/the fourth switch circuit SW4 is initiated, i.e., the second switch circuit SW 2/the fourth switch circuit SW4 are turned off when the first switch circuit SW 1/the third switch circuit SW3 is turned on, and vice versa, to perform the power conversion operation.

Referring to fig. 7A and 7B, fig. 7A and 7B are waveform timing diagrams of an output stage of a switched-capacitor power conversion circuit according to the prior art and the present invention, respectively, in another abnormal condition. It should be noted that the abnormal condition in this embodiment is that the first node voltage VN1 ≦ output voltage VOUT < (1/2) input voltage VIN of the first node N1 and the third node voltage VN3> ground voltage GND of the third node N3.

As shown in fig. 7A, when the conventional switched-capacitor power conversion circuit encounters the above abnormal condition, since the node voltage VNB of the node NB is higher than the ground voltage GND, the first capacitor current IC1 flowing through the first capacitor C1 and the second capacitor current IC2 flowing through the second capacitor C2 both increase instantaneously when switching to the second operation phase at time t1 for balancing the node voltage VNB of the node NB.

As shown in fig. 7B, when the switched-capacitor power conversion circuit of the present invention encounters the above abnormal condition, at time t0, the enable detection signal END is triggered by the power ready signal POR to change from the low level to the high level, since the first node voltage VN1 of the first node N1 is less than or equal to the output voltage VOUT and the third node voltage VN3 of the third node N3 is greater than the ground voltage GND, only the second comparison signal BH changes from the low level to the high level to start discharging the third node voltage VN3 of the third node N3, and the first node voltage VN1 and the first comparison signal AH of the first node N1 remain unchanged.

At time t1, the third node voltage VN3 of the third node N3 is discharged to be the same as the second voltage GND, such that the second comparison signal BH changes from high level to low level. At this time, since the first node voltage VN1 of the first node N1 is equal to the output voltage VOUT, the first comparison signal AH is also at a low level. At this time, the balance signal BAL changes from low level to high level, the pwm signal generator PG is enabled, the capacitive power conversion circuit is switched to the operating mode, the output stage OS enters the second operating phase (i.e., the second switch circuit SW2 and the fourth switch circuit SW4 are kept turned on to connect the first capacitor C1 and the second capacitor C2 in parallel), and the enable detection signal END changes from high level to low level to disable the first comparator CP1 and the second comparator CP2 in the control circuit DC.

It should be noted that, since the output voltage VOUT has already reached (1/2) the input voltage VIN, the power conversion operation is performed directly without performing the precharge procedure. Although a delay time is reserved between time t1 and t3 for other circuits, the delay time may be omitted in other embodiments.

At time t3, complementary switching between the first switch circuit SW 1/the third switch circuit SW3 and the second switch circuit SW 2/the fourth switch circuit SW4 is initiated, i.e., when the first switch circuit SW 1/the third switch circuit SW3 is turned on, the second switch circuit SW 2/the fourth switch circuit SW4 is turned off, and vice versa, to perform the power conversion operation

Another embodiment of the present invention is a method for controlling a switched-capacitor power conversion circuit. In this embodiment, the switched capacitor power conversion circuit includes an output stage, a first capacitor, and a second capacitor. The output stage comprises a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit which are connected in series. A first node is arranged between the first switch circuit and the second switch circuit. A second node is arranged between the second switch circuit and the third switch circuit. And a third node is arranged between the third switching circuit and the fourth switching circuit. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the second node and the ground voltage.

Referring to fig. 8, fig. 8 is a flowchart of a control method of the switched capacitor power conversion circuit in this embodiment. As shown in fig. 8, the control method includes the following steps:

step S10: operating a second switch circuit according to a first node voltage of the first node;

step S12: operating a fourth switching circuit according to a third node voltage of the third node; and

step S14: so that the voltage at two ends of the first capacitor is the same as the voltage at two ends of the second capacitor.

In practical applications, step S10 further includes: it is determined whether the first node voltage is equal to a first reference voltage. Step S12 further includes: and judging whether the voltage of the third node is equal to the second reference voltage or not. Next, the control method further includes: generating a balance signal according to a judgment result of whether the first node voltage is equal to the first reference voltage and a judgment result of whether the third node voltage is equal to the second reference voltage; generating a pulse width modulation signal to the output stage according to the balance signal to control the output stage to enter an operation mode; and disabling steps S10 and S12 according to the balance signal in the operation mode.

Compared with the prior art, the switched capacitor power conversion circuit and the control method thereof operate the second switch circuit according to the node voltage between the first switch circuit and the second switch circuit in the output stage and operate the fourth switch circuit according to the node voltage between the third switch circuit and the fourth switch circuit before the first capacitor and the second capacitor are connected in parallel, so that the voltage at two ends of the first capacitor and the voltage at two ends of the second capacitor are mutually the same and then switched to the second operation phase in which the first capacitor and the second capacitor are connected in parallel, thereby effectively avoiding the phenomenon that the switch circuit in the output stage is burnt by large current generated at the moment of switching the second operation phase, and improving the operation reliability of the switched capacitor power conversion circuit.

Claims

1. A switched-capacitor power conversion circuit, comprising:

an output stage, comprising a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit connected in series, wherein a first node is provided between the first switch circuit and the second switch circuit, a second node is provided between the second switch circuit and the third switch circuit, and a third node is provided between the third switch circuit and the fourth switch circuit;

a first capacitor coupled between the first node and the third node;

a second capacitor coupled between the second node and a ground voltage; and

a control circuit coupled to the first node, the third node, the second switch circuit and the fourth switch circuit,

the control circuit operates the second switch circuit according to a first node voltage from the first node, and operates the fourth switch circuit according to a third node voltage from the third node, so that the voltage across the first capacitor is the same as the voltage across the second capacitor.

2. The switched-capacitor power conversion circuit as claimed in claim 1, wherein the control circuit further determines whether the first node voltage is equal to a first reference voltage and determines whether the third node voltage is equal to a second reference voltage.

3. The switched-capacitor power conversion circuit as claimed in claim 2, wherein the control circuit is further coupled to a pwm signal generator, and the control circuit controls the pwm signal generator according to the first node voltage, the first reference voltage, the third node voltage and the second reference voltage.

4. The switched-capacitor power converter circuit as claimed in claim 1, wherein the control circuit comprises:

a first comparator having an input terminal coupled to the first node for receiving the first node voltage and another input terminal for receiving a first reference voltage, and an output terminal for outputting a first comparison signal for operating the second switch circuit; and

a second comparator, an input terminal of which is coupled to the third node to receive the third node voltage and another input terminal of which receives a second reference voltage, and an output terminal of which outputs a second comparison signal for operating the fourth switch circuit.

5. The switched-capacitor power converter circuit as claimed in claim 4, wherein said control circuit further comprises:

and a logic gate coupled to the output ends of the first comparator and the second comparator, respectively, for generating a balance signal according to the first comparison signal and the second comparison signal to control the power conversion circuit to enter an operation mode.

6. The switched-capacitor power conversion circuit as claimed in claim 1, further comprising a pulse width modulation signal generator coupled to the control circuit, wherein when the control circuit determines that the voltage across the first capacitor is the same as the voltage across the second capacitor, the control circuit enables the pulse width modulation signal generator.

7. A control method of a switched-capacitor power conversion circuit, the switched-capacitor power conversion circuit including an output stage, a first capacitor and a second capacitor, the output stage including a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit connected in series, the first switch circuit and the second switch circuit having a first node therebetween, the second switch circuit and the third switch circuit having a second node therebetween, the third switch circuit and the fourth switch circuit having a third node therebetween, the first capacitor being coupled between the first node and the third node, the second capacitor being coupled between the second node and a ground voltage, the control method comprising:

(a) operating the second switch circuit according to a first node voltage of the first node;

(b) operating the fourth switching circuit according to a third node voltage of the third node; and

(c) so that the voltage at two ends of the first capacitor is the same as the voltage at two ends of the second capacitor.

8. The control method of claim 7, wherein step (a) further comprises (a1) determining whether the first node voltage is equal to a first reference voltage and step (b) further comprises (b1) determining whether the third node voltage is equal to a second reference voltage.

9. The control method according to claim 8, characterized in that the control method further comprises:

(d) generating a balance signal according to the determination results of the steps (a1) and (b 1).

10. The control method according to claim 9, characterized in that the control method further comprises:

(e) generating a pulse width modulation signal to the output stage according to the balance signal to control the output stage to enter an operation mode.