CN114999541A - Impedance matching circuit of memory - Google Patents
Impedance matching circuit of memory Download PDFInfo
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- CN114999541A CN114999541A CN202210638530.3A CN202210638530A CN114999541A CN 114999541 A CN114999541 A CN 114999541A CN 202210638530 A CN202210638530 A CN 202210638530A CN 114999541 A CN114999541 A CN 114999541A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses an impedance matching circuit of a memory, which comprises: the device comprises a resistance value matching module, a resistance value realizing module and a controller; the resistance matching module is used for connecting an output line of the controller with a DQ line of the memory so as to load the resistance of the DQ line of the memory on the output line of the controller; the controller obtains an optimal resistance value of a DQ line loaded in the memory as a matching resistance value; the controller outputs a control signal to the resistance value realizing module according to the matching resistance value, controls the first resistor connected with the address line of the memory by the resistance value realizing module, and controls the second resistor connected with the data line of the memory by the resistance value realizing module. The resistance matching of the address line and the data line of the memory is realized respectively, the requirements of the address line and the control of different impedance matching can be realized, the signal integrity is improved, and the difficulty of high-speed data transmission and the distortion of output data are avoided.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to an impedance matching circuit of a memory.
Background
In the current household communication equipment, in order to eliminate signal reflection of the memory and increase voltage and time sequence margin, the impedance matching of the memory mostly adopts the series matching of a single resistor or the line connection matching mode.
The impedance matching method adopted at present realizes single impedance matching. However, due to the difference of copper thickness and surface roughness in the manufacturing process of the chip of the memory, the line impedance cannot reach the same standard, and a certain error exists, under such a condition, a single impedance matching system cannot well meet the requirement of impedance matching, so that the impedance at the interface line is mismatched, and the difficulty of high-speed data transmission and the distortion of output data are caused.
Disclosure of Invention
In order to solve the above problems, embodiments of the present invention provide an impedance matching circuit for a memory, which can dynamically adjust a matching resistance of impedance matching of the memory, improve signal integrity, and avoid difficulty in high-speed data transmission and distortion of output data.
An embodiment of the present invention provides an impedance matching circuit for a memory, where the circuit includes: the resistance value matching module, the resistance value realizing module and the controller are arranged;
the resistance matching module is used for connecting an output line of the controller with a DQ line of the memory so as to load the resistance of the DQ line of the memory on the output line of the controller;
the controller sends step signals through output lines, collects reflection signals on the output lines, and changes resistance values of the DQ lines loaded on the memory by controlling a mode register of the memory so as to enable the reflection signals to be matched with waveforms of the step signals, and obtains the resistance values of the DQ lines loaded on the memory as matching resistance values;
the controller outputs a control signal to the resistance value realizing module according to the matching resistance value, controls the first resistor connected with the address line of the memory by the resistance value realizing module, and controls the second resistor connected with the data line of the memory by the resistance value realizing module.
Preferably, the resistance matching module includes a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit;
the input end of the first switch unit is used as the first input end of the resistance value matching module and is connected with the output line of the controller; the output end of the first switch unit is used as the output end of the resistance value matching module and is connected with a DQ line of the memory; the control end of the first switch unit is used as a first control signal end of the resistance value matching module;
the input end of the second switch unit is used as a second input end of the resistance value matching module and is connected with a DQ line of the controller; the output end of the second switch unit is connected with the output end of the first switch unit; the control end of the second switch unit is used as a second control signal end of the resistance value matching module;
the input end of the third switching unit is connected with the input end of the first switching unit, and the output end of the third switching unit is grounded; the control end of the third switching unit is used as a third control signal end of the resistance value matching module;
the input end of the fourth switching unit is connected with the input end of the second switching unit, and the output end of the fourth switching unit is grounded; and the control end of the fourth switching unit is used as a fourth control signal end of the resistance value matching module.
As an improvement of the above scheme, the controller outputs a high level signal to the first control signal terminal and the fourth control signal terminal, and outputs a low level signal to the second control signal terminal and the third control signal terminal, so that an output line of the controller is connected to a DQ line of the memory, and the DQ line of the controller is grounded.
As a preferred scheme, the circuit further comprises an analog-to-digital conversion module;
the controller is connected with an output line thereof through the analog-to-digital conversion module and collects a reflected signal of a step signal output by the output line and reflected by a DQ line of the memory.
Preferably, the controller controls the mode register to set a resistance value of a DQ line loaded with the memory to a preset initial value;
sending a step signal through an output line, and collecting a reflection signal on the output line;
detecting the waveform of the received reflection signal, and comparing whether the detected waveform is the same as the waveform of the step signal;
when the detected waveform is different from the waveform of the step signal, judging that the received reflection signal is not matched with the waveform of the step signal, controlling the mode register to change the resistance value of a DQ line loading the memory, detecting the waveform of the received reflection signal again, and when the detected waveform is compared with the waveform of the step signal, controlling the mode register to change the resistance value of the DQ line loading the memory again until the detected waveform is the same as the waveform of the step signal;
and when the detected waveform is the same as the waveform of the step signal, acquiring the resistance value of the resistor loaded on the DQ line of the memory as a matching resistance value.
Preferably, the resistance value realizing module comprises a first resistance value unit and a second resistance value unit;
the first resistance unit comprises m switch subunits and m resistor subunits, the input end of the ith switch subunit is connected with the first end of the ith resistor subunit, and the second end of the ith resistor subunit is used as the input end of the first resistance unit, is used as the first input end of the resistance realizing module and is connected with the first power supply end of the controller; the control end of the ith switch subunit is used as the control end of the first resistance value unit and is used as the first control end of the resistance value realization module and is connected with the high-level output end of the controller; the output end of the ith switch subunit is used as the output end of the first resistance value unit and is used as the first output end of the resistance value realizing module, and the output end of the ith switch subunit is connected with an address wire of the memory;
the second resistance unit comprises n switch subunits and n resistor subunits, the input end of the jth switch subunit is connected with the first end of the jth resistor subunit, and the second end of the jth resistor subunit is used as the input end of the second resistance unit, is used as the second input end of the resistance realizing module, and is connected with the second power supply end of the controller; the control end of the jth switch subunit is used as the control end of the second resistance value unit and is used as the second control end of the resistance value realization module, and is connected with the first level output end of the controller; the output end of the jth switch subunit is used as the output end of the second resistance value unit and is used as the second output end of the resistance value realization module, and is connected with the data line of the memory;
wherein m, n is more than or equal to 2, i is 1,2 … m, j is 1,2 … n.
Furthermore, any resistor subunit of the first resistance unit is an impedance device, a polysilicon resistor or a variable resistor formed by connecting a plurality of resistors in series and in parallel;
any resistor subunit of the second resistance unit is an impedance device, a polysilicon resistor or a variable resistor formed by connecting a plurality of resistors in series and in parallel.
As a parallel scheme of the above scheme, any switch subunit of the first resistance unit is a triode, an MOS transistor or a field effect transistor;
any switch subunit of the second resistance unit is a triode, an MOS (metal oxide semiconductor) tube or a field effect tube.
Preferably, the output line of the controller is an address line or a data line.
Preferably, the memory is a DDR3 DRAM, and the controller is a DDR3 DRAM controller.
The invention provides an impedance matching circuit of a memory, which comprises: the resistance value matching module, the resistance value realizing module and the controller are arranged; the resistance matching module is used for connecting an output line of the controller with a DQ line of the memory so as to load the resistance of the DQ line of the memory on the output line of the controller; the controller sends step signals through output lines, collects reflection signals on the output lines, and changes resistance values of the DQ lines loaded on the memory by controlling a mode register of the memory so as to enable the reflection signals to be matched with waveforms of the step signals, and obtains the resistance values of the DQ lines loaded on the memory as matching resistance values; the controller outputs a control signal to the resistance value realizing module according to the matching resistance value, controls the first resistor connected with the address line of the memory by the resistance value realizing module, and controls the second resistor connected with the data line of the memory by the resistance value realizing module. Inquiring a corresponding output signal in a preset resistance and output signal table according to the matching resistance, outputting the output signal to a resistance realizing module, and controlling a first resistor of a resistance realizing unit connected with an address line of the memory so as to realize impedance matching of the address line of the memory; controlling a second resistor of a resistance value realization unit connected with a data line of the memory to realize impedance matching of the data line of the memory; the resistance value implementation module can respectively implement the resistance value matching of the address line and the data line of the memory, can implement the requirements of address lines and controlling different impedance matching, improves the signal integrity, and avoids the difficulty of high-speed data transmission and the distortion of output data.
Drawings
Fig. 1 is a schematic structural diagram of an impedance matching circuit of a memory according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a resistance matching module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a resistance value implementation module according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Referring to fig. 1, a schematic diagram of a structure of an impedance matching circuit of a memory according to an embodiment of the present invention is shown, where the impedance matching circuit includes: the resistance value matching module, the resistance value realizing module and the controller are arranged;
the resistance value matching module is used for realizing the connection of an output line of the controller and DQ of a memory so as to load the resistance of the DQ line of the memory on the output line of the controller;
the controller generates a step signal and outputs the step signal to a DQ line of the memory through an output line and a resistance matching module; a mode register of the memory is provided with a preset resistance value on a terminal resistor of a DQ line in advance; through the reflection of a DQ line of the memory, the controller detects a reflected signal, and the resistance value information of the terminal resistor is loaded on the reflected signal;
adding a termination matching resistor at the end of the farthest branch to absorb reflection to improve signal integrity is an economical and compromised solution, and by adopting the solution, the DDR3 can provide a higher signal transmission rate and improve the scalability of the memory system while improving signal quality.
Whether the resistance value of the terminal resistor is proper or not can be determined through the waveform of the reflected signal, and the impedance mismatch of a line can be small; adjusting the resistance on the DQ line loaded by the mode register to enable the reflected signal to be matched with the waveform of the step signal, and obtaining the resistance value of the resistance on the DQ line loaded in the memory as a matching resistance value;
by signal waveform matching of the controller, an impedance value with small impedance mismatch can be determined and used as a matching resistance value;
inquiring a corresponding output signal in a preset resistance and output signal table according to the matching resistance, outputting the output signal to a resistance realizing module, and controlling a first resistor of a resistance realizing unit connected with an address line of the memory so as to realize impedance matching of the address line of the memory; controlling a second resistor of a resistance value realization unit connected with a data line of the memory to realize impedance matching of the data line of the memory; the resistance value implementation module can respectively implement the resistance value matching of the address line and the data line of the memory, can implement the requirements of address lines and controlling different impedance matching, improves the signal integrity, and avoids the difficulty of high-speed data transmission and the distortion of output data.
Example two
Fig. 2 is a schematic structural diagram of a resistance matching module according to an embodiment of the present invention; the resistance matching module comprises a first switch unit Q1, a second switch unit Q2, a third switch unit Q3 and a fourth switch unit Q4;
the input end of the first switching unit Q1 is used as the first input end IN1 of the resistance value matching module and is connected with the output line of the controller; the output end of the first switching unit Q1 is used as the output end OUT of the resistance value matching module and is connected with a DQ line of the memory; a control terminal of the first switching unit Q1 is used as a first control signal terminal C1 of the resistance matching module;
an input terminal of the second switching unit Q2 is used as a second input terminal IN2 of the resistance matching module, and is connected with a DQ line of the controller; the output terminal of the second switching unit Q2 is connected with the output terminal of the first switching unit Q1; the control terminal of the second switching unit Q2 is used as the second control signal terminal C2 of the resistance matching module;
the input end of the third switching unit Q3 is connected with the input end of the first switching unit Q1, and the output end of the third switching unit Q3 is grounded; a control terminal of the third switching unit Q3 is used as a third control signal terminal C3 of the resistance matching module;
the input end of the fourth switching unit Q4 is connected with the input end of the second switching unit Q2, and the output end of the fourth switching unit Q4 is grounded; the control terminal of the fourth switching unit Q4 is used as the fourth control signal terminal C4 of the resistance matching module.
The connection relationship between the first/second input terminals and the output terminal of the impedance matching unit can be changed by controlling the potential of the first control signal terminal C1, the potential of the second control signal terminal C2, the potential of the third control signal terminal C3 and the potential of the fourth control signal terminal C4.
EXAMPLE III
Based on the above embodiments, in a further embodiment of the present invention, the controller outputs high level signals to the first control signal terminal C1 and the fourth control signal terminal C4, outputs low level signals to the second control signal terminal C2 and the third control signal terminal C3, so that the first switching unit Q1 and the fourth switching unit Q4 are turned on, the second switching unit Q2 and the third switching unit Q3 are turned off, an output line of the controller is connected to a DQ line of the memory, and the DQ line of the controller is grounded.
In other embodiments, the controller outputs a high level signal to the second control signal terminal C2 and the third control signal terminal C3, and outputs a low level signal to the first control signal terminal C1 and the fourth control signal terminal C4, so that the first switching unit Q1 and the fourth switching unit Q4 are turned off, the second switching unit Q2 and the third switching unit Q3 are turned on, a DQ line of the controller is connected to a DQ line of the memory, and an output line of the controller is grounded.
After the controller and the memory are initialized, the controller controls the control signal end of the resistance value matching module, and the output line of the controller can be connected with the DQ line of the memory.
The output line of the controller can be connected with the DQ line of the memory by controlling the control signal end of the resistance matching module through the controller, so that the resistance of the DQ line of the memory is loaded on the output line of the controller.
Example four
In yet another embodiment provided by the present invention, the circuit further comprises an analog-to-digital conversion module;
the controller is connected with the output line of the controller through the analog-to-digital conversion module, collects the reflected signals of the step signals output by the output line and reflected by the DQ lines of the memory, can convert the analog signals reflected by the DQ lines into digital signals, eliminates the noise generated in reflection, and is convenient for comparison of signal matching.
EXAMPLE five
In another embodiment provided by the present invention, the process of the controller determining the matching resistance value includes:
after the controller and the memory are initialized, controlling the mode register to set the resistance value of a resistor of a DQ line loaded with the memory to be a preset initial value ZQ;
sending a step signal with a voltage amplitude of 1v through an output line, and collecting a reflection signal on the output line;
detecting the waveform of the received reflection signal, and comparing whether the detected waveform is the same as the waveform of the step signal;
when the detected waveform is different from the waveform of the step signal, namely the amplitude of the waveform is greatly changed, the error is out of a preset range, and the waveform generates an oscillation signal, the received reflection signal is judged not to be matched with the waveform of the step signal, the mode register is controlled to change the resistance value of a DQ line loaded with the memory, and the resistance values on the DQ line are adjusted to be ZQ/2, ZQ/3, ZQ/4, ZQ/5, ZQ/6, ZQ/7 and the like through the mode register, so that a proper resistance value is found to enable the impedance mismatch to be small;
detecting the waveform of the received reflection signal again, and when the detected waveform is different from the waveform of the step signal by comparison, controlling the mode register again to change the resistance value of the resistor of the DQ line loaded on the memory until the detected waveform is the same as the waveform of the step signal;
and when the detected waveform is the same as the waveform of the step signal, acquiring the resistance value of the DQ line loaded in the memory as a matching resistance value.
The controller controls and adjusts the impedance of the DQ line by comparing the reflected signal with the step signal, so that the optimal matching of the impedance can be realized, the impedance difference caused by different plates and plate factories can be adapted, and each product is in the optimal impedance matching state.
EXAMPLE six
Fig. 3 is a schematic structural diagram of a resistance value implementation module provided in the embodiment of the present invention; the resistance value realizing module comprises a first resistance value unit and a second resistance value unit; the first resistance unit is used for realizing impedance matching of an address line of the memory, and the second resistance unit is used for realizing impedance matching of a data line of the memory;
the first resistance unit comprises four switch subunits, namely a first switch subunit Q1 ', a second switch subunit Q2', a third switch subunit Q3 'and a fourth switch subunit Q4', and comprises four resistor subunits, namely a first resistor subunit R1, a second resistor subunit R2, a third resistor subunit R3 and a fourth resistor subunit R4, wherein the resistance values of the resistor subunits are different from each other;
an input end of the first switch subunit Q1' is connected with a first end of a first resistor subunit R1, a second end of the first resistor subunit R1 is used as an input end of the first resistance unit and is used as a first input end in1 of the resistance realizing module, and is connected with a first power supply end of the controller to VDDQ 1; the control terminal of the first switch subunit Q1' is used as the control terminal of the first resistance unit, and is used as the first control terminal c1 of the resistance realizing module, and is connected with the high-level output terminal VOH of the controller; the output end of the first switch subunit Q1' is used as the output end of the first resistance value unit, and is used as the first output end out1 of the resistance value implementation module, and is connected with the address line address of the memory;
the input end of the second switch subunit Q2 ' is connected to the input end of the first resistance unit through a second resistor subunit R2, the control end of the second switch subunit Q2 ' serves as the control end of the first resistance unit, and the output end of the second switch subunit Q2 ' serves as the output end of the first resistance unit;
an input terminal of a third switching subunit Q3 ' is connected with an input terminal of the first resistance unit through a third resistor subunit R3, a control terminal of the third switching subunit Q3 ' serves as a control terminal of the first resistance unit, and an output terminal of the third switching subunit Q3 ' serves as an output terminal of the first resistance unit;
an input end of a fourth switch subunit Q4 ' is connected with the input end of the first resistance unit through a fourth resistor subunit R4, a control end of the fourth switch subunit Q4 ' serves as a control end of the first resistance unit, and an output end of the fourth switch subunit Q4 ' serves as an output end of the first resistance unit;
the second resistance unit comprises four switch subunits, namely a fifth switch subunit Q5 ', a sixth switch subunit Q6', a seventh switch subunit Q7 'and an eighth switch subunit Q8', and comprises four resistor subunits, namely a fifth resistor subunit R5, a sixth resistor subunit R6, a seventh resistor subunit R7 and an eighth resistor subunit R8, wherein the resistance values of the resistor subunits are different;
an input end of the fifth switch subunit Q5' is connected with a first end of the fifth resistor subunit R5, a second end of the fifth resistor subunit R5 is used as an input end of the second resistance unit, and is used as a second input end in2 of the resistance realizing module, and is connected with a second power supply end of the controller to VDDQ 2; a control terminal of the fifth switch subunit Q5' is used as a control terminal of the second resistance unit, and is used as a second control terminal c2 of the resistance realizing module, and is connected to the low level output terminal VOL of the controller; the output terminal of the fifth switch subunit Q5' is used as the output terminal of the second resistance unit, and is used as the second output terminal out2 of the resistance realizing module, and is connected to the data line date of the memory;
an input end of a sixth switch subunit Q6 ' is connected with an input end of the second resistance unit through a sixth resistor subunit R6, a control end of the sixth switch subunit Q6 ' serves as a control end of the second resistance unit, and an output end of the sixth switch subunit Q6 ' serves as an output end of the second resistance unit;
the input terminal of the seventh switch subunit Q7 ' is connected to the input terminal of the second resistance unit through a seventh resistor subunit R7, the control terminal of the seventh switch subunit Q7 ' serves as the control terminal of the second resistance unit, and the output terminal of the seventh switch subunit Q7 ' serves as the output terminal of the second resistance unit;
an input terminal of the eighth switch subunit Q8 ' is connected to the input terminal of the second resistance unit through an eighth resistor subunit R8, a control terminal of the eighth switch subunit Q8 ' serves as a control terminal of the second resistance unit, and an output terminal of the eighth switch subunit Q8 ' serves as an output terminal of the second resistance unit.
Voltage signals input by a first control end of the module are respectively matched with different switch subunits in the first resistance unit to be conducted, and different resistor subunits are connected into an address line to realize impedance matching of the address line;
the voltage signals input by the second control end of the module are respectively matched with different switch subunits in the second resistance unit to be conducted, and different resistor subunits are connected into the address line to realize the impedance matching of the data line.
It should be noted that the first resistance unit or the second resistance unit controls the voltage to control at least one of the switch subunits to be conducted, and the corresponding resistor subunit is connected to the circuit; when more than two switch subunits are conducted, the conducted resistor subunits are connected into the circuit in parallel;
it should be noted that, in this embodiment, a specific connection relationship is described by taking an example that the number of the switch subunits and the resistor subunits in the first resistance unit and the second resistance unit is 4, in other embodiments, the number of the switch subunits and the resistor subunits in the first resistance unit and the second resistance unit may be other, and the more the number of the switch subunits and the resistor subunits is, the higher the accuracy of the resistor can be achieved.
EXAMPLE seven
In another embodiment of the present invention, any one of the resistor sub-units of the first resistance unit may adopt any one of the following resistor devices: the resistor device, the polysilicon resistor or the variable resistor are formed by connecting a plurality of resistors in series and in parallel;
any one of the resistor subunits of the second resistance unit can adopt any one of the following resistor devices: the resistor device, the polysilicon resistor or the variable resistor are formed by connecting a plurality of resistors in series and in parallel;
the resistance precision of the resistor subunit can be improved through the impedance device formed by connecting the resistors in series and parallel, the resistance can be changed in an infinite way through the polysilicon resistor or the variable resistor, and the accuracy of impedance matching is improved.
Example eight
In another embodiment of the present invention, any one of the switch subunits of the first resistance unit may adopt any one of the following switching function devices: a triode, an MOS tube or a field effect tube;
any switch subunit of the second resistance unit can adopt any one of the following switch functional devices: a triode, an MOS tube or a field effect tube.
The switching tubes such as the triode, the MOS tube or the field effect tube are adopted, so that the circuit has excellent conduction performance, high stability and lower circuit cost.
Example nine
In another embodiment provided by the present invention, the output line of the controller is an address line or a data line;
the controller may output the step potential signal through the address line or the data line.
Example ten
In yet another embodiment provided by the present invention, the memory is a DDR3 DRAM and the controller is a DDR3 DRAM controller.
The DDR3 DRAM memory has a clock rate of 800Mhz, a signal transmission rate is very high, the DDR3 DRAM memory has high safety and reliability, signal integrity has very large influence on the performance of the DDR3 DRAM memory, and the matching resistance for dynamically adjusting the impedance matching of the memory is adopted, so that the accuracy of the matching resistance can be ensured.
It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and such improvements and modifications are also considered to be within the scope of the present invention.
Claims (10)
1. An impedance matching circuit for a memory, the circuit comprising: the resistance value matching module, the resistance value realizing module and the controller are arranged;
the resistance value matching module is used for connecting an output line of the controller with a DQ line of the memory so as to load the resistance of the DQ line of the memory on the output line of the controller;
the controller sends step signals through output lines, collects reflection signals on the output lines, and changes resistance values of the DQ lines loaded on the memory by controlling a mode register of the memory so as to enable the reflection signals to be matched with waveforms of the step signals, and obtains the resistance values of the DQ lines loaded on the memory as matching resistance values;
the controller outputs a control signal to the resistance value realizing module according to the matching resistance value, controls the first resistor connected with the address line of the memory by the resistance value realizing module, and controls the second resistor connected with the data line of the memory by the resistance value realizing module.
2. The impedance matching circuit of the memory according to claim 1, wherein the resistance matching module comprises a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit;
the input end of the first switch unit is used as the first input end of the resistance value matching module and is connected with the output line of the controller; the output end of the first switch unit is used as the output end of the resistance value matching module and is connected with a DQ line of the memory; the control end of the first switch unit is used as a first control signal end of the resistance value matching module;
the input end of the second switch unit is used as a second input end of the resistance value matching module and is connected with a DQ line of the controller; the output end of the second switch unit is connected with the output end of the first switch unit; the control end of the second switch unit is used as a second control signal end of the resistance value matching module;
the input end of the third switching unit is connected with the input end of the first switching unit, and the output end of the third switching unit is grounded; the control end of the third switching unit is used as a third control signal end of the resistance value matching module;
the input end of the fourth switch unit is connected with the input end of the second switch unit, and the output end of the fourth switch unit is grounded; and the control end of the fourth switching unit is used as a fourth control signal end of the resistance value matching module.
3. The impedance matching circuit of claim 2, wherein the controller outputs a high level signal to the first control signal terminal and the fourth control signal terminal, and outputs a low level signal to the second control signal terminal and the third control signal terminal, so that an output line of the controller is connected to a DQ line of the memory, and the DQ line of the controller is grounded.
4. The impedance matching circuit of memory of claim 1, wherein said circuit further comprises an analog-to-digital conversion module;
the controller is connected with an output line thereof through the analog-to-digital conversion module and collects a reflected signal of a step signal output by the output line and reflected by a DQ line of the memory.
5. The impedance matching circuit of claim 1, wherein the controller controls the mode register to set a resistance value of a DQ line loaded into the memory to a preset initial value;
sending a step signal through an output line, and collecting a reflection signal on the output line;
detecting the waveform of the received reflection signal, and comparing whether the detected waveform is the same as the waveform of the step signal;
when the detected waveform is different from the waveform of the step signal, judging that the received reflection signal is not matched with the waveform of the step signal, controlling the mode register to change the resistance value of a DQ line loading the memory, detecting the waveform of the received reflection signal again, and when the detected waveform is compared with the waveform of the step signal, controlling the mode register to change the resistance value of the DQ line loading the memory again until the detected waveform is the same as the waveform of the step signal;
and when the detected waveform is the same as the waveform of the step signal, acquiring the resistance value of the resistor loaded on the DQ line of the memory as a matching resistance value.
6. The impedance matching circuit of the memory according to claim 1, wherein the resistance value realizing module includes a first resistance value unit and a second resistance value unit;
the first resistance unit comprises m switch subunits and m resistor subunits, the input end of the ith switch subunit is connected with the first end of the ith resistor subunit, and the second end of the ith resistor subunit is used as the input end of the first resistance unit, is used as the first input end of the resistance realizing module and is connected with the first power supply end of the controller; the control end of the ith switch subunit is used as the control end of the first resistance value unit and is used as the first control end of the resistance value realization module and is connected with the high-level output end of the controller; the output end of the ith switch subunit is used as the output end of the first resistance value unit and is used as the first output end of the resistance value realizing module and is connected with the address line of the memory;
the second resistance value unit comprises n switch subunits and n resistor subunits, the input end of the jth switch subunit is connected with the first end of the jth resistor subunit, and the second end of the jth resistor subunit is used as the input end of the second resistance value unit, is used as the second input end of the resistance value realizing module and is connected with the second power supply end of the controller; the control end of the jth switch subunit is used as the control end of the second resistance value unit, is used as the second control end of the resistance value realization module, and is connected with the first level output end of the controller; the output end of the jth switch subunit is used as the output end of the second resistance value unit and is used as the second output end of the resistance value realization module, and is connected with the data line of the memory;
wherein m, n is more than or equal to 2, i is 1,2 … m, j is 1,2 … n.
7. The impedance matching circuit of claim 6, wherein any resistor subunit of the first resistance unit is an impedance device, a polysilicon resistor or a variable resistor formed by connecting a plurality of resistors in series and parallel;
any resistor subunit of the second resistance unit is an impedance device, a polysilicon resistor or a variable resistor formed by connecting a plurality of resistors in series and parallel.
8. The impedance matching circuit of claim 6, wherein any switch subunit of the first resistance unit is a triode, a MOS transistor or a field effect transistor;
any switch subunit of the second resistance unit is a triode, an MOS (metal oxide semiconductor) tube or a field effect tube.
9. The impedance matching circuit of claim 1, wherein an output line of the controller is an address line or a data line.
10. The impedance matching circuit of claim 1, wherein the memory is a DDR3 DRAM and the controller is a DDR3 DRAM controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210638530.3A CN114999541A (en) | 2022-06-08 | 2022-06-08 | Impedance matching circuit of memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210638530.3A CN114999541A (en) | 2022-06-08 | 2022-06-08 | Impedance matching circuit of memory |
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| Publication Number | Publication Date |
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| CN114999541A true CN114999541A (en) | 2022-09-02 |
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| CN202210638530.3A Pending CN114999541A (en) | 2022-06-08 | 2022-06-08 | Impedance matching circuit of memory |
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| CN (1) | CN114999541A (en) |
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