CN114996174A - Method, device, equipment and medium for dynamically mapping register address - Google Patents
Method, device, equipment and medium for dynamically mapping register address Download PDFInfo
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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Abstract
The embodiment of the invention provides a method, a device, equipment and a medium for dynamically mapping register addresses, wherein the method comprises the following steps: integrating a pre-established register model in a verification environment; the register model comprises register blocks with a plurality of layers, and each register block corresponds to at least one address mapping table; during simulation, an unlock _ model () method is called to finish unlocking the register block and the register blocks below the level; the method comprises the steps of calling an unregister () method to unlock a register and a memory in an address mapping table; assigning the address mapping table for unlocking as null; re-instantiating the address mapping table according to the address mapping state, and re-configuring and mapping the address mapping table; a lock _ model () method is called again to lock the register block related to the register model and the corresponding address mapping table; the address mapping table is re-linked to the adapter and the sequencer. The present invention can dynamically change the register access address space.
Description
Technical Field
The invention relates to the field of chip design, in particular to a method, a device, equipment and a medium for dynamically mapping register addresses.
Background
UVM provides a RAL (register interaction layer) to model registers, which can be used to conveniently access registers and storage in the design to be tested, and mirrors the values of the registers in the RAL to compare and verify the functions of the registers in the design to be tested.
Fig. 1 is a diagram of a typical UVM-based verification platform architecture including a register model. The UVM register model (register _ model in fig. 1) can be used to conveniently model the registers and storage inside the DUT (Design under test). After the register model is created, the handle of the register model can be obtained in the sequence (sequence) and the component (component) to call the interface method in the register model to complete the read-write access to the register, for example, in the sequence on the left side of fig. 1, the interface method in the register model is called to realize the read-write access to the register, and like in the lower right corner, the sequence of the register bus can be directly started, that is, the read-write access to the register is realized by operating the bus.
In general, a register in a design to be tested can be modeled as follows:
first, the uvm _ reg base class is derived to create a register.
Second, the uvm _ reg _ block base class is derived to create a register block.
Third, uvm _ reg _ adapter is derived to create an adapter (adapter).
The fourth step, integrating the register model (the top register block) in the verification environment, specifically includes:
(1) an instantiated register model is declared.
(2) All registers included in the register model are recursively instantiated.
(3) The initial value of the register is set to a configured reset value.
(4) An address mapping table is linked to the adapter and the sequencer. Since the front door access operation of the register model will be finally completed by the address mapping table, it is necessary to inform the adapter and the sequencer (sequence, for transferring the excitation sequence) to the address mapping table corresponding to the register model through the set _ sequence () method.
(5) And setting a prediction mode of the register model mirror image value, thereby completing the prediction of the register value in the design to be tested and updating the corresponding mirror image value.
In general, the above-described prior art solution is feasible, but becomes no longer feasible for the following four cases:
in the first case: if there are multiple CPUs or hosts (masters) on a chip, it is likely that multiple hosts will access the same register block (or register bus), and the addresses of the accesses may vary.
In the second case: in different user modes, the access addresses to the same register may be different.
In the third case: for security reasons, there may be a reconfiguration, i.e. a dynamic change, of the register access addresses during operation of the chip.
In a fourth case: due to the requirement of special application scenarios, in the process of chip operation, a situation that a host needs to be dynamically added to access an existing register is needed.
This is mainly due to the fact that usually one register block (uvm reg _ block) may correspond to a plurality of address mapping tables (uvm reg _ map) defining the base address of the register block and the registers and offset addresses stored therein, i.e. each address mapping table defines a register access space. Just because the lock _ model () method is called in the prior art scheme, both the register block and the corresponding address mapping table are locked. After that, the address mapping table can not be changed any more, and the remapping of the register address under the above four conditions can not be performed.
Disclosure of Invention
It is therefore an objective of the claimed invention to provide a method, apparatus, device, and medium for dynamically mapping register addresses to improve the above-mentioned problems.
The embodiment of the invention provides a method for dynamically mapping register addresses, which comprises the following steps:
integrating a pre-established register model in a verification environment; the register model comprises register blocks with a plurality of hierarchies, and each register block corresponds to at least one address mapping table;
during simulation, an unlock _ model () method is called to finish unlocking the register block and the register blocks below the level;
the method of unregister () is called to complete unlocking the register and the storage in the address mapping table;
assigning the address mapping table which is unlocked to null;
re-instantiating the address mapping table according to the address mapping state, and re-configuring and mapping the address mapping table;
a lock _ model () method is called again to lock the register block related to the register model and the corresponding address mapping table;
the address mapping table is re-linked to the adapter and the sequencer.
Preferably, before integrating the pre-established register model in the verification environment, the method further comprises:
deriving uvm _ reg base class to create a register;
deriving uvm _ reg _ block base class to create a register block;
uvm _ reg _ adapter is derived to create an adapter.
Preferably, the integrating of the pre-established register model in the verification environment specifically comprises:
declaring an instantiated register model;
recursively instantiating all registers contained in the register model;
setting an initial value of a register to be a configured reset value;
linking the address mapping table to the adapter and the sequencer so as to inform the corresponding address mapping table of the register model through a set _ sequence () method through the adapter and the sequencer;
and setting a prediction mode of the mirror image value of the register model, thereby completing the prediction of the register value in the design to be tested and updating the corresponding mirror image value.
Preferably, deriving the uvm _ reg base class to create the register specifically includes:
declaring the register field segment included in the instantiation;
configuring register field attribute information;
the register width and supported coverage collection type are passed in the new constructor.
Preferably, deriving the uvm _ reg _ block base class to create the register block specifically includes:
declaring the registers involved;
configuring and constructing register attribute information;
declaring an instantiated address mapping table and transmitting attribute information of the address mapping table;
adding the contained register to an address mapping table, and indicating the offset address of the register in the mapping table;
providing two interface methods of map _ default _ state () and map _ other _ state () for remapping the address mapping table;
an address remapping interface method re _ map () is provided.
Preferably, when the unregister () method is called to complete unlocking the registers and the memory in the address mapping table, if the entire address mapping table is unlocked, the this. unregister (map) method is used; the map. unregister (reg/mem) method is called if part of the registers or stores in the address mapping table are unlocked.
Preferably, deriving uvm _ reg _ adapter to create the adapter specifically includes:
creating a reg2bus () method for converting the register read-write access data type initiated by the register model into a format type which can be accepted on a register bus interface;
and creating a bus2reg () method for converting the bus transaction types collected by monitoring into the format types accepted by the register model when the access operation to the register on the register bus interface is monitored.
An embodiment of the present invention further provides a device for dynamically mapping a register address, where the device includes:
an integration unit for integrating a pre-established register model in a verification environment; the register model comprises register blocks with a plurality of layers, and each register block corresponds to at least one address mapping table;
the first unlocking unit is used for calling an unlock _ model () method to finish unlocking the register block and the register blocks below the level of the register block during simulation;
the second unlocking unit is used for calling the unregister () method to unlock the register and the storage in the address mapping table;
the assigning unit is used for assigning the unlocked address mapping table to null;
the mapping unit is used for revising the address mapping table according to the address mapping state and carrying out configuration mapping on the address mapping table again;
the locking unit is used for recalling the lock _ model () method to lock the register block related to the register model and the corresponding address mapping table;
and the linking unit is used for re-linking the address mapping table to the adapter and the sequencer.
The embodiment of the present invention further provides an apparatus for dynamically mapping register addresses, which includes a memory and a processor, where a computer program is stored in the memory, and the computer program can be executed by the processor, so as to implement the above method for dynamically mapping register addresses.
An embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program, where the computer program can be executed by a processor of a device where the computer-readable storage medium is located, so as to implement the method for dynamically mapping register addresses as described above.
In summary, in this embodiment, the register block and the corresponding address mapping table are unlocked, and after the address mapping table is remapped, the address mapping table is locked again and linked. Therefore, the adapter and the sequencer can dynamically change the register access address space in the simulation process. Therefore, even if the lock _ model () method is called to lock the register block and the corresponding address mapping table, the register block and the corresponding address mapping table can still be unlocked and the corresponding address mapping table can be reconfigured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a diagram of a typical UVM-based verification platform architecture incorporating a register model.
Fig. 2 is a flowchart illustrating a method for dynamically mapping register addresses according to a first embodiment of the present invention.
Fig. 3 is a schematic structural diagram of an apparatus for dynamically mapping register addresses according to a second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The invention is described in further detail below with reference to the following detailed description and accompanying drawings:
referring to fig. 3, a first embodiment of the present invention provides a method for dynamically mapping register addresses, which is performed by a device for dynamically mapping register addresses (hereinafter referred to as a dynamic mapping device), and in particular, is performed by one or more processors in the dynamic mapping device, so as to implement at least the following steps:
s101, integrating a register model established in advance in a verification environment; wherein the register model includes register blocks having a plurality of levels, each register block corresponding to at least one address mapping table.
In this embodiment, first, a register model needs to be established, where the register model is established as follows:
first, the uvm _ reg base class is derived to create a register.
Specifically, the method comprises the following steps:
declaring the register field segment included in the instantiation;
configuring register field attribute information;
the register width and supported coverage collection type are passed in the new constructor.
The uvm _ reg _ block base class is then derived to create a register block.
Specifically, the method comprises the following steps:
declaring registers involved in the instantiation;
configuring and constructing register attribute information;
declaring an instantiated address mapping table and transmitting attribute information of the address mapping table;
adding the contained register to an address mapping table, and indicating the offset address of the register in the mapping table;
providing two interface methods of map _ default _ state () and map _ other _ state () for remapping of the address mapping table;
an address remapping interface method re _ map () is provided.
Finally, uvm _ reg _ adapter is derived to create an adapter.
Specifically, the method comprises the following steps:
creating a reg2bus () method for converting the register read-write access data type initiated by the register model into a format type which can be accepted on a register bus interface;
and creating a bus2reg () method for converting the bus transaction types collected by monitoring into format types accepted by the register model when the access operation of the register on the register bus interface is monitored.
In this embodiment, after obtaining the register model, the register model may be integrated into the verification environment, and specifically, step S101 includes:
declaring an instantiated register model;
recursively instantiating all registers contained in the register model;
setting an initial value of a register to be a configured reset value;
linking the address mapping table to the adapter and the sequencer so as to inform the corresponding address mapping table of the register model through a set _ sequence () method through the adapter and the sequencer;
and setting a prediction mode of the mirror image value of the register model, thereby completing the prediction of the register value in the design to be tested and updating the corresponding mirror image value.
In this embodiment, after the register model is integrated into the verification environment, the dynamic mapping of the register address can be implemented by the address remapping interface method re _ map () during emulation.
S102, during simulation, an unlock _ model () method is called to complete unlocking of the register block and the register blocks below the register block.
S103, the unregister () method is called to unlock the register and the storage in the address mapping table.
When the unregister () method is called to unlock the register and the memory in the address mapping table, if the whole address mapping table is unlocked, the unregister (map) method is used; the map. unregister (reg/mem) method is called if part of the registers or stores in the address mapping table are unlocked.
S103, assigning the address mapping table which is unlocked to null;
s104, the address mapping table is re-instantiated according to the address mapping state, and the address mapping table is re-configured and mapped.
Wherein the address mapping state may be represented by the value of the associated identification register.
S105, a lock _ model () method is called again to lock the register block related to the register model and the corresponding address mapping table;
s106, the address mapping table is re-linked to the adapter and the sequencer.
Since the address mapping table was previously cleared, the chaining operation would need to be redone after the address mapping table is re-instantiated.
In summary, in the embodiment, the register block and the corresponding address mapping table are unlocked, and after the address mapping table is remapped, the address mapping table is locked again and linked. Thus, the adapter and the sequencer can dynamically change the register access address space in the simulation process. Therefore, even if the lock _ model () method is called to lock the register block and the corresponding address mapping table, the register block and the corresponding address mapping table can still be unlocked and the corresponding address mapping table can be reconfigured.
Referring to fig. 3, a second embodiment of the present invention further provides an apparatus for dynamically mapping register addresses, including:
an integration unit 210 for integrating a pre-established register model in a verification environment; the register model comprises register blocks with a plurality of layers, and each register block corresponds to at least one address mapping table;
a first unlocking unit 220, configured to invoke an unlock _ model () method to complete unlocking of the register block and the register blocks below the level thereof during emulation;
a second unlocking unit 230, configured to invoke the unregister () method to unlock the register and the storage in the address mapping table;
an assigning unit 240, configured to assign the unlocked address mapping table to null;
a mapping unit 250, configured to revitalize the address mapping table according to the address mapping state, and revitalize the address mapping table;
a locking unit 260, configured to recall the lock _ model () method to lock the register block and the corresponding address mapping table related to the register model;
a linking unit 270 for re-linking the address mapping table to the adapter and the sequencer.
The third embodiment of the present invention further provides an apparatus for dynamically mapping register addresses, which includes a memory and a processor, where the memory stores a computer program, and the computer program can be executed by the processor to implement the method for dynamically mapping register addresses as described above.
The fourth embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program, where the computer program can be executed by a processor of a device where the computer-readable storage medium is located, so as to implement the method for dynamically mapping register addresses as described above.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus and method embodiments described above are illustrative only, as the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention or a part thereof which substantially contributes to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for dynamically mapping register addresses, comprising:
integrating a pre-established register model in a verification environment; the register model comprises register blocks with a plurality of layers, and each register block corresponds to at least one address mapping table;
during simulation, an unlock _ model () method is called to complete unlocking of the register block and the register blocks below the register block;
the method of unregister () is called to complete unlocking the register and the storage in the address mapping table;
assigning the address mapping table which is unlocked to null;
re-instantiating the address mapping table according to the address mapping state, and re-configuring and mapping the address mapping table;
a lock _ model () method is called again to lock the register block related to the register model and the corresponding address mapping table;
the address mapping table is re-linked to the adapter and the sequencer.
2. The method for dynamically mapping register addresses according to claim 1, further comprising, prior to integrating the pre-established register model in the validation environment:
deriving uvm _ reg base class to create a register;
deriving uvm _ reg _ block base class to create a register block;
uvm _ reg _ adapter is derived to create an adapter.
3. The method of claim 1, wherein integrating the pre-established register model in the verification environment specifically comprises:
declaring an instantiated register model;
recursively instantiating all registers contained in the register model;
setting an initial value of a register to be a configured reset value;
linking the address mapping table to the adapter and the sequencer so as to inform the corresponding address mapping table of the register model through a set _ sequence () method through the adapter and the sequencer;
and setting a prediction mode of the register model mirror image value, thereby completing the prediction of the register value in the design to be tested and updating the corresponding mirror image value.
4. The method of claim 1, wherein deriving the uvm _ reg base class to create the register specifically comprises:
declaring the register field segment included in the instantiation;
configuring register field attribute information;
the register width and supported coverage collection type are passed in the new constructor.
5. The method of claim 1, wherein deriving the uvm _ reg _ block base class to create the register block comprises:
declaring the registers involved;
configuring and constructing register attribute information;
declaring an instantiated address mapping table and transmitting attribute information of the address mapping table;
adding the contained register to an address mapping table, and indicating the offset address of the register in the mapping table;
providing two interface methods of map _ default _ state () and map _ other _ state () for remapping of the address mapping table;
an address remapping interface method re _ map () is provided.
6. The method for dynamically mapping register addresses according to claim 1, wherein when the unregister () method is called to complete the unlocking of the register and the memory in the address mapping table, if the entire address mapping table is unlocked, then the unregister (map) method is used; the map. unregister (reg/mem) method is called if part of the registers or stores in the address mapping table are unlocked.
7. The method for dynamically mapping register addresses of claim 2,
deriving uvm _ reg _ adapter to create an adapter, specifically comprising:
creating a reg2bus () method for converting the register read-write access data type initiated by the register model into a format type which can be accepted on a register bus interface;
and creating a bus2reg () method for converting the bus transaction types collected by monitoring into format types accepted by the register model when the access operation of the register on the register bus interface is monitored.
8. An apparatus for dynamically mapping register addresses, comprising:
an integration unit for integrating a pre-established register model in a verification environment; the register model comprises register blocks with a plurality of hierarchies, and each register block corresponds to at least one address mapping table;
the first unlocking unit is used for calling an unlock _ model () method to finish unlocking the register block and the register blocks below the hierarchy of the register block during simulation;
the second unlocking unit is used for calling the unregister () method to unlock the register and the storage in the address mapping table;
the assigning unit is used for assigning the unlocked address mapping table to null;
the mapping unit is used for revising the address mapping table according to the address mapping state and reconfiguring and mapping the address mapping table;
the locking unit is used for recalling the lock _ model () method to lock the register block related to the register model and the corresponding address mapping table;
and the linking unit is used for re-linking the address mapping table to the adapter and the sequencer.
9. An apparatus for dynamically mapping register addresses, comprising a memory and a processor, wherein the memory stores a computer program, and the computer program is executable by the processor to implement the method for dynamically mapping register addresses according to any one of claims 1 to 7.
10. A computer-readable storage medium, in which a computer program is stored, the computer program being executable by a processor of a device in which the computer-readable storage medium is located, to implement the method for dynamically mapping register addresses according to any one of claims 1 to 7.
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| CN115983173A (en) * | 2023-03-21 | 2023-04-18 | 湖北芯擎科技有限公司 | Register model generation method and device, computer equipment and storage medium |
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Country or region after: China Address after: 3 / F, 665 Zhangjiang Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Applicant after: Yunhe Zhiwang (Shanghai) Technology Co.,Ltd. Address before: 310016 room 107, building D, integrated circuit design Industrial Park, No. 858, Jianshe Second Road, Xiaoshan Economic and Technological Development Zone, Xiaoshan District, Hangzhou City, Zhejiang Province Applicant before: Hangzhou yunhezhi Network Technology Co.,Ltd. Country or region before: China |