CN114996172A - Method and system for accessing host memory based on SSD - Google Patents
Method and system for accessing host memory based on SSD Download PDFInfo
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- CN114996172A CN114996172A CN202210913196.8A CN202210913196A CN114996172A CN 114996172 A CN114996172 A CN 114996172A CN 202210913196 A CN202210913196 A CN 202210913196A CN 114996172 A CN114996172 A CN 114996172A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention relates to the technical field of data storage, and provides a method and a system for accessing a host memory based on an SSD (solid State disk), wherein the method comprises the following steps: establishing a first data interaction path between the NVMeSSD and a video command in an NVMe protocol; acquiring a target host memory address related to NVMeSSD in the host memory based on the first data interaction path; sending a data reading control instruction to the NVMeSSD based on the first data interaction path, and controlling the NVMeSSD to access the memory address of the target host so as to read the target memory data in the memory address of the target host into the NVMeSSD; and acquiring target memory data from the NVMeSSD based on the first data interaction path. The invention can acquire the host memory information from the SSD end, and provides necessary positioning information for SSD problem positioning and development and debugging, thereby effectively accelerating the problem convergence speed and improving the development efficiency.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a method and a system for accessing a host memory based on an SSD.
Background
The NVMe SSD is an SSD interacting with a host based on an NVMe (Non-Volatile Memory Express) protocol, and has the characteristics of low delay, high performance and the like. In order to enable the NVMe SSD to work normally, besides that the SSD itself needs to support the NVMe protocol, an operating system of the host also needs to support the NVMe protocol, common operating systems include linux and windows, and an NVMe driver in the operating system provides support for the NVMe protocol. The host interacts with the NVMe SSD through the NVMe drive.
When the SSD normally operates, it is not necessary to check the memory information related to the NVMe SSD in the host memory, but in some application scenarios, for example, when the SSD is debugged and located and the NVMe driver is developed, it is greatly helpful to analyze the problem if the host memory related to the SSD can be checked conveniently and quickly. Based on the difference of operating systems, the method for checking the memory of the SSD related host in the prior art scheme mainly includes: the Linux operating system provides an Mmap access interface for a driver developer, so that the developer can access a kernel space from a user space, and the purpose of checking the memory of the SSD-related host is achieved. Windows is more harsh than Linux in terms of checking the memory of the host, and if a driver is not a professional driver, the driver cannot check the related memory information of the SSD of the host.
It can be seen that, in the existing technical scheme, checking that the host memory related to the SSD depends on the openness of the operating system to a great extent, and a professional developer may be required to perform further processing on the system and the driver to read the host memory information related to the SSD from the host. In addition, for some operating systems with stricter system restrictions, such as windows, host memory information related to the SSD may not be obtained from the host side.
Disclosure of Invention
In view of the above, the present invention has been developed to provide a method and system for SSD-based access to host memory that overcomes or at least partially solves the above-mentioned problems.
In one aspect of the present invention, a method for accessing a host memory based on an SSD is provided, the method comprising:
a first data interaction channel between the NVMeSSD and the NVMe protocol is established by a vendor command in the NVMe protocol;
acquiring a target host memory address related to the NVMeSSD in the host memory based on the first data interaction path;
sending a data reading control instruction to the NVMeSSD based on the first data interaction path, wherein the data reading control instruction carries the memory address of the target host, and controlling the NVMeSSD to access the memory address of the target host so as to read the target memory data in the memory address of the target host to a specified storage position inside the NVMeSSD;
and acquiring the target memory data from the NVMeSSD based on the first data interaction path.
Further, the method further comprises:
establishing a second data interaction channel with the NVMeSSD by adopting a hardware interface of the NVMeSSD device;
when the first data interaction channel is abnormal in communication, acquiring a target host memory address related to the NVMeSSD in a host memory based on the second data interaction channel;
sending a data reading control instruction to the NVMeSSD based on the second data interaction channel, wherein the data reading control instruction carries the memory address of the target host, and controlling the NVMeSSD to access the memory address of the target host so as to read the target memory data in the memory address of the target host to a specified storage position inside the NVMeSSD;
and acquiring the target memory data from the NVMeSSD based on the second data interaction path.
Further, the controlling the nvmesd to access the target host memory address includes:
and controlling the NVMeSSD to access the memory address of the target host through a PCIe bus.
Further, after obtaining the target memory data from the nvmesd, the method further includes:
and performing data display on the target memory data.
Further, the target memory data includes data information in a host memory address corresponding to the commit queue SQ, the completion queue CQ, and/or the Doorbell mechanism Doorbell.
Further, after obtaining the target memory data from the nvmesd, the method further includes:
and when the target memory data comprises a commit queue SQ, analyzing data information in the host memory address corresponding to the commit queue SQ to obtain the host memory address related to the read-write data in the command of the commit queue SQ and the read-write data in the address.
In another aspect of the present invention, a system for accessing a host memory based on an SSD is provided, and the system includes a memory information processing module and a host memory access module:
the memory information processing module is used for establishing a first data interaction channel between the memory information processing module and a host memory access module by adopting a vendor command in an NVMe protocol, acquiring a target host memory address related to NVMeSSD in a host memory based on the first data interaction channel, sending a data reading control instruction to the host memory access module based on the first data interaction channel, wherein the data reading control instruction carries the target host memory address, controlling the host memory access module to access the target host memory address so as to read target memory data in the target host memory address to a specified storage position inside the NVMeSSD, and acquiring the target memory data from the NVMeSSD based on the first data interaction channel;
and the host memory access module is used for accessing the target host memory address according to the data reading control instruction sent by the memory information processing module so as to read the target memory data in the target host memory address to a specified storage position in the NVMeSSD.
Further, the memory information processing module is further configured to establish a second data interaction path with the host memory access module by using a hardware interface of the nvmesd device; when the first data interaction channel is abnormal in communication, acquiring a target host memory address related to the NVMeSSD in a host memory based on the second data interaction channel; sending a data reading control instruction to the host memory access module based on the second data interaction channel, wherein the data reading control instruction carries the target host memory address, and controlling the host memory access module to access the target host memory address so as to read target memory data in the target host memory address to a specified storage position inside the NVMeSSD; and acquiring the target memory data from the NVMeSSD based on the second data interaction path.
Further, the target memory data comprises data information in a host memory address corresponding to a commit queue SQ, a completion queue CQ and/or a Doorbell mechanism Doorbell;
the memory information processing module is further configured to, after the target memory data is obtained from the nvmesd, when the target memory data includes a commit queue SQ, parse data information in the host memory address corresponding to the commit queue SQ to obtain a host memory address related to read and write data in a commit queue SQ command and read and write data in the address.
Further, the host memory access module includes:
the PCIe interface sub-module is used for connecting with a PCIe module in the NVMeSSD through an AXI bus so as to access the memory address of the target host through the PCIe bus and obtain target memory data in the memory address of the target host;
the CPU interface sub-module is used for being connected with a CPU module inside the NVMe SSD through an AXI bus and establishing connection with a hardware interface of the NVMe SSD equipment;
the address resolution submodule is used for resolving initialization information issued by a host driver so as to acquire a target host memory address related to the NVMe SSD in a host memory;
the data transmission submodule is used for establishing a first data interaction channel and/or a second data interaction channel with the memory information processing module and transmitting data;
and the data receiving sub-module is used for receiving the data transmitted from the PCIe interface sub-module.
According to the method and the system for accessing the host memory based on the SSD, provided by the embodiment of the invention, the host memory information related to the SSD can be quickly and conveniently acquired from the SSD end through the arrangement of the upper-layer software function module, so that necessary positioning information is provided for SSD problem positioning, development and debugging, the problem convergence speed is effectively increased, and the development efficiency is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a flowchart of a method for accessing a host memory based on an SSD according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating command path division in the method for accessing the host memory based on the SSD according to the embodiment of the present invention;
fig. 3 is a block diagram of a device for accessing a host memory based on an SSD according to an embodiment of the invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In practical application, the content of the host interacting with the NVMe SSD through the NVMe driver is mainly classified into the following categories:
admin interaction with NVM commands. Commands are organized in Admin Queue and NVM Command Queue, which are placed in the host's memory.
In the command notification interaction, the NVMe informs the SSD of whether a new command needs to be processed in the command queue through a Doorbell mechanism (Doorbell), and the actual address of the Doorbell is also in the host memory.
And the SSD starts data transmission after receiving the read-write command, and the interactive data can also be stored in the host memory.
Normally, when the SSD operates normally, it is not necessary to check the queues in the host memory, the Doorbell, and the read/write data, but in the following cases, the host memory may need to be checked.
1. When the SSD works abnormally, online positioning and debugging are needed. The reason for the exception may be because the Firmware (Firmware) on the SSD is defective, and may also be because the host NVMe drive is defective. Under the condition, if the information such as SQ, CQ queue, Doorbell and transmitted data in the memory of the host can be observed, the problem positioning is greatly facilitated.
2. The SSD firmware development stage belongs to a development debugging stage, the firmware may have many defects, the SSD often works abnormally due to the defects in interaction with the host, and if the host memory can be checked to obtain SQ, CQ queue, Doorbell, transmitted data and other information in the stage, the convergence speed of the defects can be greatly accelerated, and the development period can be shortened.
3. NVMe drives the development phase. The NVMe drive development period may cause host exception, such as blue screen, crash, and the like, under which the host memory cannot be viewed from the host, and at this time, if the relevant information of the host memory can be obtained, great help is also provided for problem analysis.
In order to conveniently acquire host memory information related to SSD, the invention provides a method and a system for accessing a host memory based on SSD.
Fig. 1 schematically shows a system architecture diagram for accessing a host memory based on an SSD according to an embodiment of the present invention. Referring to fig. 1, the SSD-based system for accessing a host memory according to the embodiment of the present invention includes a memory information processing module 10 (i.e., Mem Dbg module) and a host memory access module 20.
The memory information processing module is a pre-designed upper-layer software function module, and is a final receiver and a final presenter of the memory information of the NVMeSSD-related host. The software provides a friendly interface, and can display the acquired host memory data related to the NVMeSSD to a user. The host memory data related to the nvmesd includes, but is not limited to, data information in the host memory address corresponding to the host commit queue sq (submission queue), completion queue cq (completion queue), and/or Doorbell mechanism Doorbell, and detailed information of read and write data.
The memory information processing module has no requirement on the running platform, and the memory information processing module can run on the host platform in the embodiment of the invention.
The memory information processing module 10 is configured to establish a first data interaction path with the host memory access module 20 by using a vendor command in the NVMe protocol, acquire a target host memory address related to the nvmes in the host memory based on the first data interaction path, send a data reading control instruction to the host memory access module 20 based on the first data interaction path, where the data reading control instruction carries the target host memory address, control the host memory access module 20 to access the target host memory address, so as to read target memory data in the target host memory address to a specified storage location inside the nvmes, and acquire the target memory data from the nvmes based on the first data interaction path.
The host memory access module 20 is configured to access the target host memory address according to the data reading control instruction sent by the memory information processing module, so as to read the target memory data in the target host memory address to a specified storage location inside the nvmesd.
According to the method for accessing the host memory based on the SSD, provided by the embodiment of the invention, the host memory information related to the SSD can be quickly and conveniently acquired from the SSD end through the deployment of the upper layer software functional module, so that necessary positioning information is provided for SSD problem positioning and development and debugging, the problem convergence speed is effectively increased, and the development efficiency is improved.
In an embodiment of the invention, the memory information processing module runs on a host platform, and establishes a first data interaction path through a vendor command defined in the NVMe protocol to realize data interaction. When the host NVMe driver can work normally and can respond to the NVMeAdmin command normally, the memory information processing module controls the host memory access module to access the target host memory address by using the data interaction channel so as to acquire target memory data in the target host memory address.
Specifically, the memory information processing module obtains host memory addresses related to the SSD from the SSD end through the first data interaction path, for example, memory addresses of SQ, CQ, and Doorbell, which are configured to the SSD by the host driver during initialization, so that the SSD knows detailed information of the addresses, and the memory information processing module can obtain the memory address information from the host memory access module during the initialization stage. The memory information processing module controls a host memory access module in the SSD to access a specific host memory address through a data reading control instruction, the host memory access module passively receives a control signal, and all addresses to be accessed are controlled by the Mem Dbg. After the host memory access module receives the data reading control instruction sent by the memory information processing module, the host memory access module reads target memory data into the SSD through the PCIe bus, and then returns the data to the memory information processing module through the first data interaction path. Such as to obtain the contents of the data in the SQ queue.
Further, the memory information processing module 10 is further configured to establish a second data interaction path with the host memory access module 20 by using a hardware interface of the nvmesd device; when the first data interaction channel is abnormal in communication, acquiring a target host memory address related to the NVMeSSD in a host memory based on the second data interaction channel; sending a data reading control instruction to the host memory access module based on the second data interaction channel, wherein the data reading control instruction carries the target host memory address, and controlling the host memory access module to access the target host memory address so as to read target memory data in the target host memory address to a specified storage position inside the NVMeSSD; and acquiring the target memory data from the NVMeSSD based on the second data interaction path.
Specifically, the memory information processing module establishes a second data interaction path by using a hardware interface of the nvmesd device, and the hardware interface is a debug interface. Debug is a Debug interface, and is generally a dedicated interface line connected when a problem occurs, and can communicate with the SSD through the Debug interface, generally most commonly a serial port, but not limited to a serial port or other hardware paths. The path is to ensure the completeness of the link, and can realize the access of the memory data of the host under the condition that the first data interaction path cannot work normally. The specific method is similar to the first data interaction path, and is mainly different in that a host memory access module and a memory information processing module in the SSD interact through a second data interaction path, and data is transmitted to a debug interface path when the data is transmitted back.
The memory information processing module has no requirement on the operation platform, can be operated on the host platform and can also be operated on other platforms, the memory information processing module can be deployed according to different use scenes, when the memory information processing module is operated on other platforms, the memory information processing module needs to interact with the host memory access module based on the second data path, and the host memory access module is operated on the NVMe SSD.
The invention provides two data access paths, a second data interaction path can be used under the condition that a first data interaction path is not communicated, the completeness of a data link is ensured, a host memory access module in an SSD can receive upper-layer software address configuration, host memory related information is obtained through a PCIe bus, and the path for returning data to is determined according to the path for providing a request. According to the invention, when the host NVMe driver can normally work and can normally respond to the NVMeAdmin command, the first data interaction path can be preferentially used, the first data interaction path carries out data transmission through PCIe, and the transmission efficiency is higher.
In the embodiment of the present invention, the target host memory address includes a host memory address corresponding to a commit queue SQ, a completion queue CQ, and/or a Doorbell mechanism Doorbell, and correspondingly, the target memory data includes data information in the host memory address corresponding to the commit queue SQ, the completion queue CQ, and/or the Doorbell mechanism Doorbell.
Further, the memory information processing module is further configured to, after the target memory data is obtained from the nvmesd, when the target memory data includes a commit queue SQ, parse data information in the host memory address corresponding to the commit queue SQ to obtain a host memory address related to read and write data in a command of the commit queue SQ and read and write data in the address.
In this embodiment, the memory information processing module may further obtain a host memory address related to read-write data in the SQ command by analyzing detailed contents of the read-write command in the SQ command, so as to further read out the data in the address, that is, the memory information processing module may track data interaction between the host and the SSD, which is very helpful for locating a data transmission problem on the SSD. The system can further analyze SQ content data, further can track the data content of read-write data in the host memory area, provides necessary positioning information for problem positioning and development and debugging, and can effectively accelerate problem convergence speed and improve development efficiency.
In the embodiment of the present invention, as shown in fig. 2, the host memory access module 20 specifically includes a PCIe interface sub-module 201, a CPU interface sub-module 202, an address resolution sub-module 203, a data transmission sub-module 204, and a data reception sub-module 205, where:
the PCIe interface sub-module 201 is configured to connect, through an AXI bus, to a PCIe module inside the nvmesd, so as to access the target host memory address through the PCIe bus, and obtain target memory data in the target host memory address;
the CPU interface sub-module 202 is configured to connect with a CPU module inside the NVMe SSD through the AXI bus, and establish a connection with a hardware interface of the NVMe SSD device;
the address resolution sub-module 203 is configured to resolve initialization information issued by a host driver to obtain a target host memory address related to the NVMe SSD in a host memory;
the data transmission submodule 204 is used for establishing a first data interaction path and/or a second data interaction path with the memory information processing module and performing data transmission;
and the data receiving sub-module 205 is used for receiving the data transmitted from the PCIe interface sub-module.
The invention can conveniently acquire the required positioning information from the SSD end, thoroughly solves the defect that the prior art is inconvenient to acquire the host memory information in some scenes, and has important significance for accelerating problem positioning and shortening development and debugging.
Fig. 3 schematically shows a flowchart of a method for accessing a host memory based on an SSD according to an embodiment of the present invention. Referring to fig. 3, the method for accessing the host memory based on the SSD according to the embodiment of the present invention specifically includes the following steps:
s11, establishing a first data interaction path between the NVMeSSD and a video command in the NVMe protocol;
s12, acquiring a target host memory address related to the NVMeSSD in the host memory based on the first data interaction channel;
and S13, sending a data reading control instruction to the NVMeSSD based on the first data interaction path, wherein the data reading control instruction carries the target host memory address, and controlling the NVMeSSD to access the target host memory address so as to read the target memory data in the target host memory address to a specified storage position inside the NVMeSSD.
Specifically, the controlling the nvmesd to access the memory address of the target host includes: and controlling the NVMeSSD to access the memory address of the target host through a PCIe bus.
S14, obtaining the target memory data from the NVMeSSD based on the first data interaction path.
Further, after obtaining the target memory data from the nvmesd, the method further includes: and performing data display on the target memory data.
The method for accessing the host memory based on the SSD can quickly and conveniently acquire the host memory information related to the SSD from the SSD end, provides necessary positioning information for SSD problem positioning and development and debugging, and further effectively accelerates the problem convergence speed and improves the development efficiency.
The method for accessing the memory of the host based on the SSD, provided by the embodiment of the invention, further comprises the following steps which are not shown in the attached drawings:
s21, establishing a second data interaction path between the NVMeSSD and the NVMeSSD by adopting a hardware interface of the NVMeSSD device;
s22, when the first data interaction path is abnormal in communication, acquiring a target host memory address related to the NVMeSSD in the host memory based on the second data interaction path;
s23, sending a data reading control instruction to the NVMeSSD based on the second data interaction channel, wherein the data reading control instruction carries the target host memory address, and controlling the NVMeSSD to access the target host memory address so as to read target memory data in the target host memory address to a specified storage position inside the NVMeSSD;
s24, obtaining the target memory data from the NVMeSSD based on the second data interaction path.
Further, after the target memory data is obtained from the nvmesd, data display of the target memory data is also performed.
In an embodiment of the present invention, the target host memory address includes a host memory address corresponding to the commit queue SQ, the completion queue CQ, and/or the Doorbell mechanism Doorbell, and correspondingly, the target memory data includes data information in the host memory address corresponding to the commit queue SQ, the completion queue CQ, and/or the Doorbell mechanism Doorbell.
Further, after obtaining the target memory data from the nvmesd, the method further includes: and when the target memory data comprises a commit queue SQ, analyzing data information in the host memory address corresponding to the commit queue SQ to obtain the host memory address related to the read-write data in the command of the commit queue SQ and the read-write data in the address.
In this embodiment, the host memory address related to the read-write data in the SQ command can be further obtained by analyzing the detailed content of the read-write command in the SQ command, so as to further read the data in the address, that is, the data interaction between the host and the SSD can be tracked, which is very helpful for locating the data transmission problem on the SSD.
The invention can further analyze SQ content data, further can track the data content of read-write data in the host memory area, provides necessary positioning information for problem positioning and development and debugging, and can effectively accelerate problem convergence speed and improve development efficiency.
According to the method and the system for accessing the host memory based on the SSD, provided by the embodiment of the invention, the host memory information related to the SSD can be quickly and conveniently acquired from the SSD end through the arrangement of the upper-layer software function module, so that necessary positioning information is provided for SSD problem positioning, development and debugging, the problem convergence speed is effectively increased, and the development efficiency is improved.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, any of the claimed embodiments may be used in any combination.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for accessing a host memory based on an SSD, the method comprising:
establishing a first data interaction path between the NVMeSSD and a video command in an NVMe protocol;
acquiring a target host memory address related to the NVMeSSD in the host memory based on the first data interaction path;
sending a data reading control instruction to the NVMeSSD based on the first data interaction path, wherein the data reading control instruction carries the memory address of the target host, and controlling the NVMeSSD to access the memory address of the target host so as to read the target memory data in the memory address of the target host to a specified storage position inside the NVMeSSD;
and acquiring the target memory data from the NVMeSSD based on the first data interaction path.
2. The method of claim 1, further comprising:
establishing a second data interaction channel with the NVMeSSD by adopting a hardware interface of the NVMeSSD device;
when the first data interaction channel is abnormal in communication, acquiring a target host memory address related to the NVMeSSD in a host memory based on the second data interaction channel;
sending a data reading control instruction to the NVMeSSD based on the second data interaction channel, wherein the data reading control instruction carries the memory address of the target host, and controlling the NVMeSSD to access the memory address of the target host so as to read target memory data in the memory address of the target host to a specified storage position inside the NVMeSSD;
and acquiring the target memory data from the NVMeSSD based on the second data interaction path.
3. The method of claim 1 or 2, wherein the controlling the nvmesd to access the target host memory address comprises:
and controlling the NVMeSSD to access the memory address of the target host through a PCIe bus.
4. The method of claim 1 or 2, wherein after obtaining the target memory data from the nvmesd, the method further comprises:
and performing data display on the target memory data.
5. The method of any of claims 1 to 4, wherein the target memory data comprises data information in a host memory address corresponding to a commit queue SQ, a completion queue CQ, and/or a Doorbell mechanism Doorbell.
6. The method of claim 5, wherein after obtaining the target memory data from the NVMeSSD, the method further comprises:
and when the target memory data comprises a submission queue SQ, analyzing data information in the host memory address corresponding to the submission queue SQ to obtain the host memory address related to the read-write data in the submission queue SQ command and the read-write data in the address.
7. A system for accessing a host memory based on an SSD is characterized by comprising a memory information processing module and a host memory access module:
the memory information processing module is used for establishing a first data interaction path between the memory information processing module and a host memory access module by adopting a vendor command in an NVMe protocol, acquiring a target host memory address related to NVMeSSD in a host memory based on the first data interaction path, sending a data reading control instruction to the host memory access module based on the first data interaction path, wherein the data reading control instruction carries the target host memory address, controlling the host memory access module to access the target host memory address so as to read target memory data in the target host memory address to a specified storage position inside the NVMeSSD, and acquiring the target memory data from the NVMeSSD based on the first data interaction path;
and the host memory access module is used for accessing the target host memory address according to the data reading control instruction sent by the memory information processing module so as to read the target memory data in the target host memory address to a specified storage position in the NVMeSSD.
8. The system according to claim 7, wherein the memory information processing module is further configured to establish a second data interaction path with the host memory access module by using a hardware interface of the nvmesd device; when the first data interaction channel is abnormal in communication, acquiring a target host memory address related to the NVMeSSD in a host memory based on the second data interaction channel; sending a data reading control instruction to the host memory access module based on the second data interaction channel, wherein the data reading control instruction carries the target host memory address, and controlling the host memory access module to access the target host memory address so as to read target memory data in the target host memory address to a specified storage position inside the NVMeSSD; and acquiring the target memory data from the NVMeSSD based on the second data interaction path.
9. The system of claim 7 or 8, wherein the target memory data comprises data information in a host memory address corresponding to a commit queue SQ, a completion queue CQ, and/or a Doorbell mechanism Doorbell;
the memory information processing module is further configured to, after the target memory data is obtained from the nvmesd, when the target memory data includes a commit queue SQ, analyze data information in a host memory address corresponding to the commit queue SQ to obtain a host memory address related to read and write data in a commit queue SQ command and read and write data in the address.
10. The system of claim 8, wherein the host memory access module comprises:
the PCIe interface sub-module is used for connecting with a PCIe module in the NVMeSSD through an AXI bus so as to access the memory address of the target host through the PCIe bus and obtain target memory data in the memory address of the target host;
the CPU interface sub-module is used for being connected with a CPU module inside the NVMe SSD through an AXI bus and establishing connection with a hardware interface of the NVMe SSD device;
the address resolution submodule is used for resolving initialization information issued by a host driver so as to acquire a target host memory address related to the NVMe SSD in a host memory;
the data transmission submodule is used for establishing a first data interaction channel and/or a second data interaction channel with the memory information processing module and transmitting data;
and the data receiving sub-module is used for receiving the data transmitted from the PCIe interface sub-module.
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