CN114996073A

CN114996073A - Hot removal protection system and method for peripheral expansion equipment of FPGA (field programmable Gate array) system

Info

Publication number: CN114996073A
Application number: CN202210262834.4A
Authority: CN
Inventors: 张旭升; 杨一峰
Original assignee: Shanghai Guowei Silcore Technology Co ltd
Current assignee: Shanghai Guowei Silcore Technology Co ltd
Priority date: 2022-03-17
Filing date: 2022-03-17
Publication date: 2022-09-02

Abstract

The invention provides a hot removal protection system of peripheral extension equipment of an FPGA prototype verification system, which comprises a hot removal processing device and a processing module; the hot removal processing device comprises a judging module and a protecting module; the judgment module and the protection module are electrically connected with the peripheral expansion equipment; the processing module is arranged in the FPGA prototype verification system; the judging module judges the power supply connection state of the FPGA prototype verification system and sends the power supply connection state to the protection module and the processing module; according to the first authentication strategy, peripheral extension equipment of the FPGA prototype verification system can be released or locked in the power-off state, and according to the second authentication strategy, power-off processing or early warning processing is carried out on the peripheral extension equipment of the FPGA prototype verification system in the power-on state. The invention also provides a hot removal protection method of the peripheral extension equipment of the FPGA prototype verification system. The invention provides a real mode for providing the hot plug of the interrupt card.

Description

Hot unplugging protection system and method for peripheral expansion equipment of FPGA (field programmable Gate array) system

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a hot unplugging protection system and method for peripheral expansion equipment of an FPGA system. And more particularly to the field of FPGA prototype verification.

Background

Generally, in the prototype verification of chip design in the FPGA prototype verification system, an FPGA board is required to be used when debugging and programming an FPGA chip, and the FPGA board is a PCB printed circuit board having up to dozens of layers.

In the PCB, the communication between the FPGA logic system and the peripheral circuit is usually realized mainly by an on-board connector. The connected channels are mainly divided into two categories: daughter cards and cables. And a male connector of the daughter card/cable is tightly combined with a female connector of the FPGA mainboard, so that the communication and the functional interaction on the circuit are realized.

At present, the FPGA system itself does not have the hot plug supporting performance. Therefore, under the condition of power-on, the IO pin of the FPGA is extremely easy to damage due to misoperation or hot plugging under an unknown condition. And from an electrical standpoint, such damage is irreversible, i.e., cannot be repaired. When the damaged pin reaches a certain scale, the debugging IO interface of the FPGA system is greatly reduced; for designs that require a large number of debug IOs, the work will be greatly affected. At present, the repair method can only be to replace the main chip of the FPGA. Because the cost of the FPGA chip at the middle and high ends is very expensive, tens of thousands or even hundreds of thousands of RMB are frequently generated; such a method would therefore entail very expensive repair costs. From the current FPGA prototype verification market, there is no real way for manufacturers to provide hot plug of the intervener cards.

In addition, the number of interconnection interfaces in the FPGA prototype verification system in the prior art is small, and it is difficult to add additional function design to the FPGA prototype verification system without affecting the main function of the FPGA prototype verification system, thereby increasing the technical difficulty.

Based on the above, the present application provides a technical solution to solve the above technical problems.

Disclosure of Invention

The first purpose of the invention is to obtain an early warning system for removing peripheral extension equipment of an FPGA system.

A second object of the present invention is to obtain a prototype verification system with an FPGA system peripheral extension device removal early warning system.

The third purpose of the invention is to obtain an early warning method for removing peripheral extension equipment of an FPGA system.

The first aspect of the invention provides a hot-unplugging protection system for peripheral extension equipment of an FPGA prototype verification system, which comprises a hot-unplugging processing device and a processing module;

the hot removal processing device comprises a judgment module and a protection module, and is arranged near peripheral expansion equipment of the peripheral FPGA prototype verification system; the judging module and the protecting module are electrically connected with peripheral extension equipment of the FPGA prototype verification system;

the processing module is arranged in the FPGA prototype verification system;

wherein the content of the first and second substances,

according to a preset judgment strategy, the judgment module is configured to judge the power supply connection state of the FPGA prototype verification system, obtain power supply connection state information of the FPGA prototype verification system in a power-on state or a power-off state, and send the power supply connection state information to the protection module and the processing module;

-the protection module is configured to release or lock a peripheral extension device of the FPGA prototype verification system if the FPGA prototype verification system is in a powered-down state according to a preset first authentication policy,

according to a preset second authentication strategy, under the condition that the FPGA prototype verification system is in a power-on state, the processing module is configured to perform power-off processing or early warning processing on peripheral extension equipment of the FPGA prototype verification system.

In a specific embodiment of the present invention, after the processing module performs power-down processing on the peripheral expansion device of the FPGA prototype verification system, the peripheral expansion device of the FPGA prototype verification system may be released or locked according to a preset first authentication policy.

The judgment module comprises a voltage judgment module or a current judgment module;

the protection module comprises a fixing device, and the fixing device is used for releasing or locking peripheral extension equipment of the FPGA prototype verification system; and/or

The processing module includes a system on a chip.

In one embodiment, the fixation device is a screw fixation device.

Preferably, the judging module is a voltage judging module. Specifically, when the voltage is determined to be not powered on, the connector is 0V, and when the voltage is powered on, the connector is 1.8V or 3.3V.

Optionally, the determining module is a current determining module. If the current is, it can also be judged that: the FPGA system has no current when not powered on, and has current after being powered on.

In one embodiment of the present invention, the hot-plug protection device further includes an authentication unit, where the authentication unit includes a biological information identification module and a first storage unit;

the first storage unit is set to store a biological information database of a legal user, and the biological information identification unit identifies an illegal user and the legal user according to the biological information of the legal user.

The biometric information may be a fingerprint, an iris, or a combination thereof. Preferably a fingerprint is used.

In a specific embodiment, the fixing device releases or locks the peripheral extension device of the FPGA prototype verification system according to an authentication result fed back by the authentication unit and according to a preset first authentication policy.

In a specific embodiment, the processing module performs release processing or early warning processing on the peripheral extension device of the FPGA prototype verification system according to an authentication result fed back by the authentication unit and according to a preset second authentication policy.

In a specific embodiment of the present invention, the FPGA prototype verification system includes an FPGA main board unit and a power control unit, and is characterized in that the peripheral extension device for FPGA prototype verification is electrically connected to the FPGA main board unit, and the processing module is disposed in the power control unit.

In an embodiment of the present invention, the FPGA main board unit is a plurality of FPGA main board units.

In one embodiment of the invention, the power control unit comprises a system on a chip;

the processing module is arranged in the power control unit and comprises: the processing module is arranged in the system on chip.

In one embodiment of the present invention, the system on chip (SOC chip) may control the power-on or power-off operation of the upper FPGA board.

In a specific embodiment of the present invention, the FPGA prototype verification system further includes a second storage unit, and the second storage unit is used for storing or recording a biological information database of a legal user and/or the prompt information.

In a specific embodiment, the record is stored in a second Flash chip. More specifically, the Flash chip is disposed on the PCM board on the power control board.

Preferably, the first storage unit stores biological information, and the second storage unit stores or records a biological information database of a legitimate user and the prompt information.

Preferably, the biometric information is a fingerprint. Alternatively, an iris or other biometric information that can identify a legitimate user may be used, or a combination thereof.

In a second aspect, the invention provides an FPGA prototype verification system including the thermal unplugging protection system of the invention.

A third aspect of the present invention provides a hot-plug protection method for peripheral expansion devices of an FPGA prototype verification system, which is applicable to the hot-plug protection system and the FPGA prototype verification system of the present invention, and the hot-plug protection method includes:

according to a preset judgment strategy, the judgment module judges the power supply communication state of the FPGA prototype verification system to obtain the power supply communication state information of the FPGA prototype verification system in a power-on state or a power-off state, and sends the power supply communication state information to the protection module and the processing module;

according to a preset first authentication strategy, the protection module releases or locks the peripheral expansion equipment of the FPGA prototype verification system under the condition that the FPGA prototype verification system is in a power-off state,

according to a preset second authentication strategy, under the condition that the FPGA prototype verification system is in a power-on state, the processing module performs release processing or early warning processing on peripheral extension equipment of the FPGA prototype verification system.

In an embodiment of the present invention, the processing module powers down peripheral extension devices of the FPGA prototype verification system.

In one embodiment of the present invention, the pre-warning process includes providing a prompt message;

the prompt information comprises first prompt information and second prompt information, the first prompt information comprises information prompted by an LED lamp, and the second prompt information comprises information prompted by a buzzer.

The invention can bring at least one of the following beneficial effects:

1. not only can the IO interface damage caused by misoperation of hot removal be effectively reduced, but also the hot plug phenomenon can be actively interfered;

2. the early warning function is realized by utilizing various existing resources on the existing FPGA system without adding additional modules or circuits, and the effective early warning function is realized without increasing additional cost.

3. Furthermore, active intervention can be performed on the problem of hot plug of the daughter card, which is difficult to solve for a long time.

Drawings

The foregoing features, technical features, advantages and embodiments are further described in the following detailed description of the preferred embodiments, which is to be read in connection with the accompanying drawings.

FIG. 1 illustrates a multiple FPGA board system;

FIG. 2 shows the overall structure of a conventional FPGA system;

fig. 3 shows a schematic view of a daughter card connector and securing screw holes;

FIG. 4 shows a partial block diagram of an FPGA system with a strap card dongle;

FIG. 5 shows a FPGA system component distribution architecture;

fig. 6 shows a body structure diagram of a daughter card protection device (lock);

FIG. 7 illustrates a fingerprint set data acquisition flow diagram;

FIG. 8 shows a flow chart for software controlled powering down and unplugging the daughter card.

Detailed Description

In the invention, the inventor finds that the working efficiency and the design precision of the FPGA system during debugging can be greatly improved as long as the IO interface damage caused by hot removal of misoperation is effectively reduced through extensive and deep experiments; more importantly, hot unplug is prevented by an authentication policy. In addition, the technical scheme provided by the invention utilizes various existing resources on the existing FPGA system, does not need to add an additional module or circuit to realize the early warning function, and realizes an effective protection function without increasing additional cost.

Unless explicitly stated or limited otherwise, the term "or" as used herein includes the relationship of "and". The "sum" is equivalent to the boolean logic operator "AND", the "OR" is equivalent to the boolean logic operator "OR", AND "is a subset of" OR ".

The terms "connected," "communicating," and "connecting" are used broadly and encompass, for example, a fixed connection, a connection through an intervening medium, a connection between two elements, or an interaction between two elements, unless expressly stated or limited otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

Terms such as "top," "bottom," "above," "below," "over," "under," and the like, may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass other orientations of the device in addition to the orientation depicted in the figures.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present inventive concept.

Various aspects of the invention are described in detail below:

hot-plug protection system

The invention relates to a hot removal protection system of peripheral extension equipment of an FPGA prototype verification system, which is used for planting the hot removal protection system of the peripheral extension equipment of the FPGA prototype verification system, wherein the hot removal processing system comprises a hot removal processing device and a processing module; the hot removal processing device comprises a judgment module and a protection module, and is arranged near peripheral expansion equipment of the peripheral FPGA prototype verification system; the judging module and the protecting module are electrically connected with peripheral extension equipment of the FPGA prototype verification system; the processing module is arranged in the FPGA prototype verification system; the judging module is configured to judge the power supply communication state of the FPGA prototype verification system according to a preset judging strategy to obtain power supply communication state information of the FPGA prototype verification system in a power-on state or a power-off state, and send the power supply communication state information to the protection module and the processing module; according to a preset first authentication strategy, the protection module is configured to release or lock the peripheral extension equipment of the FPGA prototype verification system under the condition that the FPGA prototype verification system is in a power-off state, and according to a preset second authentication strategy, the processing module is configured to perform power-off processing or early warning processing on the peripheral extension equipment of the FPGA prototype verification system under the condition that the FPGA prototype verification system is in a power-on state.

The inventor utilizes various existing resources on the existing FPGA prototype verification system, does not need to add additional modules or circuits to realize the early warning function, realizes an effective protection function under the condition of not increasing additional cost, and particularly adopts a hardware approach to the peripheral extension equipment so as to greatly prolong the service life of a main chip in the FPGA prototype verification system.

For purposes herein, the "external object proximate to the FPGA prototype verification system" includes, but is not limited to, a hand, finger, or other object.

In one embodiment, the peripheral extension devices of the FPGA prototype verification system include two types: daughter cards and cables.

The peripheral extension equipment of the FPGA prototype verification system is a hot-unplugging protection object of the invention, preferably performs hot-unplugging protection on daughter cards, can perform hot-unplugging protection on one daughter card, and can also perform hot-unplugging protection on a plurality of daughter cards.

In one embodiment, the communication mode of the FPGA prototype verification system and the peripheral circuit (used for connecting the peripheral expansion equipment) is mainly realized through a connector. Connectors generally have two specifications, and are respectively installed at two places: the first specification is arranged on the FPGA board, is mostly a female connector and is connected with most of available IO of the FPGA chip; the second specification is provided on peripheral expansion equipment, and is mostly a male connector, which is used for connecting components on a daughter card, such as functional chips, discrete components and the like. For example, a male connector arranged on the daughter card or the cable is tightly combined with a female connector arranged on the FPGA system, so as to realize communication and functional interaction on a circuit.

In one embodiment, the daughter card provides various protocol support, storage media, and data paths between external devices and the FPGA system. The various protocol supports include, but are not limited to, PCIe, DDR4, MIPI protocols, or combinations thereof.

In a specific embodiment of the present invention, the FPGA prototype verification system includes an FPGA main board unit and a power control unit, wherein the peripheral extension device for FPGA prototype verification is electrically connected to the FPGA main board unit, and the monitoring module is disposed in the power control unit.

In a specific embodiment, the FPGA motherboard unit includes an FPGA main chip (an FPGA chip to be debugged), a plurality of connectors to lead out various devices and modules of an IO (input/output) pin of the FPGA chip, a user debug pin bank, an LED display lamp, a button switch, a JTAG interface, and the like, and the above components constitute an FPGA system for chip function development and interaction.

In a specific embodiment, the FPGA prototype verification system is further provided with other optional peripheral components of the SOC, such as: FLASH chip, fingerprint identification chip, capacitance induction button, LED luminotron, Beep buzzer or their combination.

In one embodiment, a PCM Power Control unit (all referred to as Power and Control Module) is used to connect the FPGA board and the Power supply. Generally, the PCM power control unit also has some external interface to realize the interconnection function of the FPGA system and the external device, such as USB, ethernet, global reset button, or a combination thereof.

Hot-removing protection device

In one embodiment of the invention, the hot-unplug protection device comprises a daughter card dongle.

In one embodiment of the present invention, the hot-plug protection device further includes an authentication unit, and the authentication unit includes a biological information identification module and a first storage unit.

The first storage unit is arranged to store a biological information database of a legal user, and the biological information identification unit identifies an illegal user and the legal user according to the biological information of the legal user.

The authentication unit comprises a fingerprint identification unit and a first storage unit; the first storage unit stores a fingerprint information database of a legal user, the fingerprint identification unit performs fingerprint identification according to the fingerprint information of the legal user and sends the fingerprint identification signal to the judgment module, and the fixing device releases or locks the peripheral extension equipment of the FPGA prototype verification system according to a judgment result fed back by the judgment module; thereby enabling the protection module to release or lock the peripheral extension devices of the FPGA prototype verification system.

In one embodiment of the invention, the hot unplugging protection device is internally provided with a cruising module. More specifically, the endurance module is a battery. For example, when a battery is arranged in the hot unplugging protection device, the battery provides power to work, so that the work of the voltage judgment module cannot be influenced no matter whether the FPGA system is powered on or not. However, it should be understood that the endurance module may be disposed outside the thermal removal protection device as long as the judgment module is not affected.

Judging module of hot-removing processing device

The judging module comprises a voltage judging module or a current judging module.

Preferably, the judging module is a voltage judging module.

In a specific embodiment of the present invention, when the determining module (specifically, the voltage determining module) determines the power connection state of the FPGA prototype verification system, according to an interface voltage value (specifically, an interface voltage value of a power line), it may be determined whether the FPGA prototype verification system is powered on.

Protection module of hot-removing processing device

The protection module of the invention comprises a fixing means.

And the fixing device of the protection module is used for releasing or locking the peripheral extension equipment of the FPGA prototype verification system.

In one embodiment, the fixation device is a screw fixation device.

The "release or lock" is a physical release or lock. When released, the peripheral expansion device is available for use. When locked, the peripheral expansion device is unusable.

Processing module

In one embodiment of the invention, the power control unit comprises a system on chip.

In an embodiment of the present invention, the system on chip (SOC chip) may control the operation of powering on or powering off the FPGA board in the upper layer.

In an embodiment of the present invention, the FPGA prototype verification system includes an FPGA main board unit and a power control unit, the peripheral extension device of the FPGA prototype verification is electrically connected to the FPGA main board unit, and particularly, the processing module is disposed in the power control unit.

Preferably, the processing module is disposed in the power control unit and includes: the processing module is disposed within the system-on-chip.

In a specific embodiment of the present invention, the processing module is driven by an output pin of the SOC monitoring module; the PCM power supply monitoring module is also provided with a Flash storage chip (a second storage unit) which is connected with the SOC control chip through an SPI4 bus.

In one embodiment, the SOC control chip contains an ARM module. Preferably Zynq from Xilinx or a Cyclone chip from Intel.

In a specific embodiment, the early warning mode of the processing module is set to adopt a polling operation mode to detect whether the sensing signal sent by the protection module is received.

In a specific embodiment, when the sensing signal is a fingerprint identification signal, the SOC chip detects whether the following condition is satisfied by using a polling operation mode: whether a finger touches the daughter card is identified through a capacitive fingerprint identification module.

In one embodiment, the period of the polling may be set to be not more than 10 seconds. Specifically, but not limited to, 0.5-10 seconds, such as 0.5 seconds, 1 second, 2 seconds, 3 seconds, 4 seconds, or 5 seconds, or any interval at the above values.

In a specific embodiment, the early warning mode includes using a warning buzzer, an LED warning lamp, or a combination thereof.

Hot-drawing protection method

The invention provides a hot removal protection method for peripheral extension equipment of an FPGA prototype verification system, which is suitable for the hot removal protection system and the FPGA prototype verification system, and comprises the following steps:

according to a preset judgment strategy, the judgment module judges the power supply communication state of the FPGA prototype verification system to obtain power supply communication state information of the FPGA prototype verification system in a power-on state or a power-off state, and sends the power supply communication state information to the protection module and the processing module;

In one embodiment of the present invention, the pre-warning process includes providing a prompt;

Based on the present application, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number and aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details. The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features described as being defined as "first," "second," etc., may explicitly or implicitly include one or more of the features. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings. The terms "inner" and "outer" are used to refer to directions toward and away from, respectively, the geometric center of a particular component.

Examples and comparative examples

The terminology of this implementation is explained as follows:

the FPGA chip (FPGA) is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), which not only solves the defect of the custom circuit, but also overcomes the defect of limited Gate circuits of the original Programmable device. The basic structure of the FPGA comprises a configurable logic block, a digital clock management module, an embedded block RAM, a wiring resource, an embedded special hard core, a bottom layer embedded functional unit and a programmable input/output unit. The FPGA has the characteristics of abundant wiring resources, high repeatable programming and integration level and low investment, and is widely applied to the field of digital circuit design. The design process of the FPGA comprises algorithm design, code simulation, design and trigger debugging, wherein an algorithm framework is established by a designer and actual requirements, an EDA (electronic design automation) scheme or HDL (hardware description language) is used for compiling design codes, the code simulation is used for ensuring that the design scheme meets the actual requirements, finally, the trigger debugging is carried out, a configuration circuit is used for downloading related files into an FPGA chip, and the actual operation effect is verified.

The FPGA upper board is connected with the PCM board through a board lower connector, and the daughter card is connected with the FPGA upper board connector through a card upper connector. In a typical connector structure, since several hundreds of pins are included, a 'power line' and a 'data bus' can be transmitted simultaneously to achieve communication of the entire data link.

FPGA IO: i.e., input/output pins. The method is a main contact way for interaction of the FPGA verification system and an external network circuit; the IO of the FPGA is generally divided into a normal IO and a high-speed IO. The transmission rate of a common IO can reach hundreds of MHz generally; high-speed IO can currently be single-pass to the order of tens of gigabits.

An FPGA board: the PCB is a PCB printed circuit board with less than ten layers and dozens of layers; the chip plays a role of a carrier of the FPGA chip. The FPGA chip main body and various peripheral components are welded on the FPGA board, so that the FPGA chip can be normally started and run subsequent functions. Meanwhile, a plurality of connectors (described in detail later) are mounted on the FPGA board to lead out IO pins of the FPGA. And the FPGA board is also provided with various debugging interfaces such as a user debugging pin header, an LED display lamp, a button switch, a JTAG debugging interface, a USB debugging interface, an Ethernet interface and the like.

A connector: IO connecting bodies of the FPGA and main interconnection modes of the peripheral circuits; typically, a connector contains tens to hundreds of metal pins. Correspondingly, the external connection board or daughter card also has connector elements that mate with the connectors on the FPGA board. Therefore, the main head connectors are arranged on the FPGA board and connected with most of the available IO of the FPGA; secondly, on the daughter card, the number of the daughter cards is the male connector; components on the daughter card such as functional chips, discrete components, etc. The connector on the daughter card is tightly buckled with the connector on the FPGA board, so that the realization of the channel, interaction and design functions on data is realized.

PCM: all of them are called Power and Control modules (Power Control modules), and in a complete FPGA system, the PCM is generally in the position of the middle layer; the function of connecting the FPGA board and the power supply is achieved. Meanwhile, a PCM board is usually provided with a certain external interface such as a USB, an Ethernet, a global reset button and the like; so as to realize the interconnection function of the FPGA system and the external equipment.

Daughter card: the peripheral extended circuit board of the FPGA system has small size. Chips with different functions are soldered on the daughter card to provide various protocol support (such as PCIe, DDR4, ethernet, MIPI, etc.), storage media, and data paths between external devices and the FPGA board. In most cases, the IO of each chip on the daughter card is also connected to the connector of the daughter card, and is connected to the FPGA system through the connector.

SOC chip: the various functional blocks of storage, processing, logic and interfaces are implemented in one chip rather than in several different physical chips as is the case with on-board systems. Compared with an on-board system, the SoC solution is lower in cost, can realize faster and safer data transmission among different system units, and has higher overall system speed, lower power consumption, smaller physical size and better reliability. Taking the VU series logic system of sierra core company as an example, an SOC control chip is installed on a PCM board, which plays roles of controlling the power on and off of the whole system, monitoring hardware environment in real time and the like, and is better than the human brain.

A plurality of FPGA systems: usually, one PCM board is mounted with one FPGA board, which we call a single FPGA system. As the name implies, a plurality of FPGA systems are formed by installing more than 1 FPGA board on one PCM bottom board. The system can run a large-capacity design, and multiple users can simultaneously and independently use different FPGA boards to perform function tests without mutual influence. And each FPGA board can be independently powered on and powered off.

Hot plug-in (Hot-plugging or Hot Swap), that is, Hot plug-in, the Hot plug function is to allow a user to take out and replace damaged components such as a hard disk, a power supply or a board card without closing the system or cutting off the power supply, so that the timely recovery capability, expansibility, flexibility and the like of the system to disasters are improved, for example, some high-end application-oriented disk mirroring systems can provide the Hot plug function of a disk. For the FPGA sold in the market at present, only a few high-speed channel IO of the FPGA supports hot plug; most FPGA IOs do not support hot plug. The operation of hot plug can be divided into 2 parts after being subdivided: hot insertion and hot removal; the hot plug means that the daughter card is inserted into a connector of the system when the FPGA mainboard is in a power-on state; hot-unplugging means the operation of the FPGA motherboard to remove an inserted daughter card from the system while it is powered up. Typically with hot-plug/hot-unplug, the IOs of an FPGA are extremely vulnerable and difficult to repair. Hot plug behaviour in use should be strictly prohibited. By comprehensively considering the scheme, the occurrence of the hot removal condition can be prohibited.

As shown in fig. 1, a multiple FPGA board system is shown.

As shown in fig. 2, the overall structure of a common FPGA system is shown; for the FPGA sold in the market at present, only a small part of high-speed channel IO supports hot plug; ordinary IO is not supported. Fig. 1 shows a schematic diagram of a conventional FPGA system connection structure. Belonging to a common IO type which does not support hot plug.

Referring to fig. 1, an FPGA board in an FPGA system is connected to a PCM board through a connector, and daughter cards are connected to the FPGA board through another connector. The FPGA system is used for prototype verification.

An FPGA board is typically a PCB printed circuit board of up to dozens of layers; is a carrier of the FPGA chip. Generally speaking, an FPGA chip main body is soldered on an FPGA board, and a plurality of connectors are installed to lead out IO pins of the FPGA chip. And the FPGA board is also provided with devices such as a user debugging pin header, an LED display lamp, a button switch, a JTAG port and the like.

The invention is suitable for various FPGA chips in the field, in particular to the FPGA chip of a prototype verification system. Specifically, the basic structure of the FPGA chip may include a programmable input output unit, a configurable logic block, a digital clock management module, an embedded block RAM, a wiring resource, an embedded dedicated hardmac, a bottom embedded functional unit, or a combination thereof. The scope of the FPGA is not so limited.

FIG. 3 is a schematic view of a daughter card connector and securing screw;

fig. 3 is an enlarged view of the daughter card connector: the intermediate portion is a connector body, as described in the first section, and the daughter card is most often mounted with a male connector. And two sides of the daughter card are respectively provided with a round hole, and the fixing screw is screwed into the nut on the main board and fastened after passing through the holes.

FIG. 4 is a diagram of a portion of an FPGA system with daughter card protection locks; the structure of the daughter card with the pluggable protection device (or called daughter card protection lock) is overall, and the whole system is not changed greatly. The daughter card protection lock is arranged above the daughter card, and meanwhile, the daughter card protection lock is also provided with two intervals and sizes, and the openings which are the same as the daughter card can be penetrated by fixing screws for fixing.

That is, the present invention can change the FPGA prototype verification system to a small extent, which is advantageous for upgrading and modifying the existing FPGA prototype verification system.

FIG. 5 is a diagram of a FPGA system component distribution architecture; referring again to the refined detail distribution diagram of the elements, for clarity of description, the stereo hierarchy of fig. 3 is converted into a tiled form as in fig. 5.

Fig. 6 is a body structure view of the daughter card protection device (lock).

It should be understood that the daughter card protection devices of the present invention may be one or more.

The structure of the body of the daughter card protection device (lock) is described in detail as follows:

in order to be convenient and fast to use, the daughter card protection lock takes fingerprint identification as an authentication mode; the lock top surface comprises a fingerprint identification unit, a storage chip (for storing fingerprint information and unlocking logs), a voltage judgment module and a micro battery. The daughter card protective lock is also provided with a pair of screw fixing means for fixing the two fixing screws as explained above in view of physical structure. When the FPGA system is in a power-off state and fingerprint identification and authentication are passed, the screw fixing device makes a release action, and the screw can be rotated and taken down; when the FPGA system connector is in a power-on state, the screw fixing device is always fastened and cannot rotate. The daughter card fixing and protecting functions are achieved on the mechanical structure.

Figure 7 shows a fingerprint set data acquisition flow diagram.

Before the fingerprint identification function of the daughter card protection lock is used, authorized fingerprints must be recorded, the mode described in the text is that computer software is used for connecting a PCM board, a fingerprint identification unit carries out collection work and checks the integrity of a sample, and then a fingerprint set is stored in the daughter card protection lock and a Flash memory chip on the PCM board. The specific process is as shown in fig. 7, firstly, the USB data line is connected to the PCM board on the hardware, and the daughter card protection lock and the daughter card are also connected to the connector of the FPGA board at the same time. And then starting the hardware system, after the start is finished, the software sends a fingerprint acquisition command to the SOC chip, and then the SOC chip sends a command to the fingerprint acquisition module. And after receiving the instruction, the acquisition module returns a ready feedback signal, and meanwhile, the LED indicator lamp is lightened to indicate that the preparation for fingerprint acquisition is made. And then, fingerprint acquisition is carried out, and the fingerprint is stored in a storage chip of Flash and cannot be lost after the fingerprint acquisition is finished. The steps are repeated until all the fingerprints are acquired.

FIG. 8 shows a flow chart for powering up and unplugging daughter cards under software control.

The daughter card protection device of the present invention operates as follows:

considering the working effect of the daughter card protection lock, to achieve the intervention protection of hot unplugging the daughter card, first, the preset condition of the unplugging event is considered, that is, the preset condition is satisfied under the condition that the whole FPGA system is powered on. If the system is plugged in the state of complete power failure, the system is cold plugged, and the hazard described above does not exist.

Secondly, specific methods of intervention protection are considered. The present embodiment will mainly describe 2 kinds of input conditions and output results:

input condition 1: is the FPGA system already in a powered-on state?

The judging method comprises the following steps: mainly through a voltage judgment module on the protection lock. And judging whether the power-on state exists or not according to the interface voltage value of the power line. Because the battery provides power for working, the working of the voltage judgment module on the daughter card cannot be influenced no matter whether the FPGA system is electrified or not.

Input condition 2: is the result of fingerprint recognition legitimate? Before the protection device is formally started, the fingerprint collection and storage work can be carried out. If the identification result is that the fingerprints which are set in advance and stored in the Flash chip are concentrated, the fingerprint is considered to be legal; otherwise, it is an illegal fingerprint.

The overall protection process is divided into two cases:

case 1: the FPGA system is entirely in a power-down state.

Firstly, according to the judgment input condition 1, a battery supply circuit on the protection lock continuously works, and meanwhile, the power-off of the system is known through a level judgment module; at the moment, when a fingerprint identification signal is generated, the identification result of the input condition 2 is judged, if the fingerprint identification signal accords with the fingerprint database subset stored in the Flash chip, the unlocking is legal, and the judgment module releases the screw fixing device; the user then removes the two set screws and removes the daughter card and the daughter card dongle. The whole daughter card unplugging operation flow is completed; if the fingerprint is illegal, the process is ended. And storing the log in a Flash chip of the daughter card protection lock for recording whether the identification is successful or failed.

Case 2: if the FPGA board is in the power-on state, the level judgment module of the protection lock can obtain the power-on state of the FPGA board through a power line communicated by the connector, and then the enable signal of the fingerprint identification module is controlled to be closed, the fingerprint identification module does not work, and a signal of identification failure is output by default; the screw fixing device will also keep the closed state, which plays the role of protecting and locking the daughter card. On the other hand, the system is in a power-on state, the SOC is controlled to feed back a signal through the fingerprint input by the connector, and a user is known to contact the daughter card; at this time, the SOC makes a warning action on the board by flashing the LED and sounding the buzzer.

Further, in this state, the user may have two options to pull out the daughter card:

and A-powering off the whole FPGA system physically, namely, all components including a power supply, a PCM board and an FPGA upper board are powered off by pressing a power supply button. Thus returning to the state of case 1; and the user performs fingerprint authentication, and the daughter card can be taken down after the fingerprint authentication is passed.

B-as shown in FIG. 8, the user powers off the FPGA upper board through software control, and then the operation of unplugging and unplugging the daughter card can be performed. Especially in a system with a plurality of FPGA upper plates, the method is very convenient; because one daughter card can be powered down and removed, and the state of the continuous work of the other FPGA upper boards is not influenced.

Conclusion

The embodiments of the present invention obtain the following effects:

firstly, the invention provides a hardware device for preventing the damage to FPGA IO caused by hot unplugging; more specifically, for example, with the daughter card dongle device described in the embodiments;

secondly, the control SOC and software in the FPGA system can control the FPGA board to be powered off to pull out the daughter card; the use is convenient and the control effect is reliable;

thirdly, the daughter card protection lock is provided with a battery, Flash and fingerprint identification, and autonomous identification is carried out;

in addition, the operation log of the Flash is read by the computer, and the operation behavior of the user can be analyzed.

Compared with the conventional prototype verification system, the method has the effect of effectively reducing IO interface damage caused by hot removal of misoperation, and does not increase extra cost.

It should be understood that the described embodiments illustrate implementations of daughter card dongle.

It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

All documents referred to herein are incorporated by reference into this application as if each were individually incorporated by reference. Furthermore, it should be understood that various changes and modifications can be made by those skilled in the art after reading the above disclosure, and equivalents also fall within the scope of the invention as defined by the appended claims.

Claims

1. A hot-unplugging protection system of peripheral extension equipment of an FPGA prototype verification system is characterized in that the hot-unplugging processing system comprises a hot-unplugging processing device and a processing module;

the processing module is arranged in the FPGA prototype verification system;

wherein the content of the first and second substances,

-the protection module is configured to release or lock peripheral extension devices of the FPGA prototype verification system in case the FPGA prototype verification system is in a powered-down state according to a preset first authentication policy,

2. The thermal unplug protection system of claim 1 wherein,

the judgment module comprises a voltage judgment module, a current judgment module or a combination thereof;

The processing module includes a system on a chip.

3. The thermal unplug protection system of claim 1 wherein said thermal unplug protection device further comprises an authentication unit, said authentication unit comprising a biometric identification module, a first memory unit;

4. The hot-plug protection system according to any one of claims 1 to 3, wherein the FPGA prototype verification system includes an FPGA motherboard unit and a power control unit, and the peripheral expansion device of the FPGA prototype verification is electrically connected to the FPGA motherboard unit, and the processing module is disposed in the power control unit.

5. The hot unplug protection system of claim 4 wherein the power control unit comprises a system on a chip;

6. The hot unplug protection system as claimed in claim 5 wherein said FPGA prototype verification system further comprises a second storage unit for recording a biometric database of a legitimate user and/or said prompt message.

7. An FPGA prototype verification system comprising the thermal unplugging protection system of any of claims 1-6.

8. A hot-plug protection method for peripheral extension devices of an FPGA prototype verification system, the hot-plug protection method being applied to the hot-plug protection system according to any one of claims 1 to 6 and the FPGA prototype verification system according to claim 7, the hot-plug protection method comprising:

9. The method for hot unplug protection as recited in claim 8, wherein the processing module powers down peripheral expansion devices of the FPGA prototype verification system.

10. The hot unplug protection method as recited in claim 8, wherein said pre-alarm processing comprises providing a prompt;