CN114995158A - Adaptive sampling switching control method for complex circuit network system under DoS attack - Google Patents

Abstract

The invention discloses an adaptive sampling switching control method for a complex circuit network system under DoS attack. A sensor samples the complex circuit network system with a period T, and a transmitter sends a data packet composed of an error sampling state and a sampling point sequence to a communication network. ; When the data packet arrives in the buffer, the buffer immediately generates the first control signal, the comparator captures the key information of the DoS attack according to the data packet and the time point sequence, and the intelligent logic processor sends different signals to the controller according to the key information of the DoS attack; control The controller switches the control gain parameters according to the signal sent by the intelligent logic processor, and feeds it back to the complex circuit network system through the zero-order holder and the actuator, thereby driving the complex circuit network system. The invention combines an intelligent logic processor and an adaptive sampling switching control mechanism, adopts different controllers for different DoS attack situations, and effectively enhances the robustness of the system against DoS attacks.

Description

Adaptive sampling switching control method for complex circuit network system under DoS attack

technical field

The invention relates to the technical field of circuit system security control, in particular to an adaptive sampling switching control method of a complex circuit network system under DoS attack.

Background technique

With the rapid development of networking and informatization, the complex circuit network system brings people wealth and convenience, but also increasingly highlights its security issues. Because a complex circuit network system is a complex system composed of multiple circuit systems connected through a network. The interior of each circuit system is an organic whole composed of sensors, controllers, actuators and networks, and the information exchange between circuit systems is carried out through the network. Due to the high degree of openness and sharing of the network, it is very vulnerable to network attacks. In recent years, the frequent occurrence of global network attacks has made people more and more aware of the importance of network security. Because network security control can effectively resist various network attacks, the security control of complex circuit network systems has become the focus of research. For complex circuit network systems, most of the current control methods are mainly designed based on continuous feedback information. In continuous feedback control, the information of state variables needs to be continuously transmitted to the controller and fed back to the system. This continuous feedback control mode results in a waste of computing and network communication resources to a certain extent. Compared with the continuous feedback control method, the sampling control only needs to transmit the signal at the sampling point to the controller, which can greatly reduce the amount of information transmission and effectively save the network communication resources. At present, the sampling control of complex circuit network systems has become the focus of research. As a kind of common network attack, DoS attack will seriously affect the synchronization performance and security of complex circuit network system. Therefore, it is of far-reaching significance to explore the secure sampling control of complex circuit network systems under DoS attacks, but there is still a lack of relevant research. In addition, in order to effectively combat the impact of DoS attacks on the performance of network systems, the paper "Resilient Control Design of a Class of Networked Control Systems Based on Sampling Models under DoS Attacks", IEEE Transactions on Cybernetics, August 2020" in Sampling In this model, an elastic safety sampling control method is proposed. In this method, in order to capture DoS attack information, the author embeds a logic processor in the design of the sampling controller, and the method has been successfully applied to solve the consistency problem of multi-agent systems under DoS attack, and its logic processor can effectively Capturing DoS attack information and the proposed elastic security sampling control method can effectively combat the impact of DoS attack on network system performance. However, this method has three shortcomings: (1) the designed logical processor cannot fully capture the key information of DoS attacks, such as the total number of attacked sampling points and the attack launch time; (2) the frequency of DoS attacks and the duration of DoS attacks are ignored. The relationship between domain, sampling period and maximum dwell time; (3) Regardless of whether a DoS attack occurs, the same control gain is used at all times, which will result in poor control robustness to a certain extent.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an adaptive sampling switching control method of complex circuit network system under DoS attack, which is used to solve the problem of insufficient capture of DoS when the elastic security sampling control method in the prior art resists the impact of DoS attack on network system performance. Attacking key information, ignoring the DoS attack frequency, DoS attack residence area, the relationship between the sampling period and the maximum residence time, and the problem of poor control robustness.

The present invention solves the above-mentioned problems through the following technical solutions:

An adaptive sampling switching control method for a complex circuit network system under DoS attack, comprising:

Step S100, the sensor samples the complex circuit network system with a period T to obtain the error sampling state and sampling point sequence of the circuit system;

The sensor samples the complex circuit network system with a period T, and obtains the error sampling state η _i (s _l ) of the ith circuit system at the sampling point s _l and the sampling point sequence S={s ₀ ,s ₁ ,...,s _{l , . _ _} ..., m; m is the number of circuit systems;

Step S200, the data packet formed by the error sampling state and the sampling point sequence is sent to the communication network by the transmitter; that is, the data packet (s1, η _i (s _{1 )} ) is composed of the error sampling state η _i (s ₁ ) and the sampling point. sequence S={s ₀ ,s ₁ ,…,s _l ,…,s _L };

智能逻辑处理器的比较器根据数据包和时间点序列捕获DoS攻击关键信息，智能逻辑处理器根据DoS攻击关键信息发送不同的信号给控制器；Step S300, when the data packet reaches the buffer of the intelligent logic processor, and the data in the buffer is updated, the first control signal is immediately generated, and the first control signal is used to realize the system safety synchronization control; the intelligent logic processor sends the data to the controller time point series of packets

The comparator of the intelligent logic processor captures the key information of the DoS attack according to the data packet and time point sequence, and the intelligent logic processor sends different signals to the controller according to the key information of the DoS attack;

Step S400, the controller controls the switching control gain parameter according to the signal sent by the intelligent logic processor, and generates a second control signal according to the signal sent by the intelligent logic processor and the control gain, and then uses the zero-order holder to discretely sample the second control signal. It is converted into a continuous signal, and then fed back to the complex circuit network system through the actuator, thereby driving the complex circuit network system.

The key information for capturing DoS attacks includes:

DoS攻击的发生次数N₀＝0、被检测后的攻击驻留总时长D₀＝0、最大驻留时间h_M＝T、第一关键参数σ₁＝1和第二关键参数σ₂＝0，其中，

，第一关键参数σ₁和第二关键参数σ₂用于控制器自适应调节控制输入；Initial sampling time

The number of occurrences of DoS attacks N ₀ =0, the total attack residence time after detection D ₀ =0, the maximum residence time h _M =T, the first key parameter σ ₁ =1 and the second key parameter σ ₂ =0 ,in,

, the first key parameter σ ₁ and the second key parameter σ ₂ are used for the controller to adaptively adjust the control input;

Let the systematic error state η(t)=[η ₁ ^T (t),η ₂ ^T (t),...,η _i ^T (t),...] ^T , where η _i ^T (t) is the ith circuit the error state of the system;

比较器首先判断数据包

是否到达缓存器，如果到达，则把

赋值给时间点序列的当前时间点t_l，发送信号(σ₁,σ₂)＝(1,0)和数据包(t_l,η(t_l))到控制器，并将t_l的值赋值给

如果未到达，警报器被触发，即数据包

遭受了DoS攻击，此时

为攻击发起时刻；更新DoS攻击发生次数N₀＝N₀+1，发送信号(σ₁,σ₂)＝(0,1)到控制器，并等待采样数据包(t_l,η(t_l))到达缓存器，如果数据包(t_l,η(t_l))到达缓存器，则这次攻击结束，更新

其中

表示该次攻击在被检测后的持续时间，

为被检测时间点；for a given initial value and

The comparator first judges the packet

Whether to reach the buffer, if so, put

Assign the current time point t _l of the time point sequence, send the signal (σ ₁ ,σ ₂ )=(1,0) and the data packet (t _l ,η(t _l )) to the controller, and use the value of t _l assign to

If it doesn't arrive, the siren is triggered, i.e. the packet

suffered a DoS attack,

is the attack initiation time; update the number of DoS attacks N ₀ =N ₀ +1, send signals (σ ₁ ,σ ₂ )=(0,1) to the controller, and wait for the sampling data packets (t _l ,η(t _{l )} )) reach the buffer, if the data packet (t _l , η(t _l )) reaches the buffer, the attack ends, and the update

in

Indicates the duration of the attack after it was detected,

is the detected time point;

的大小，如果h_M小于

则更新

发送信号(σ₁,σ₂)＝(1,0)和数据包(t_l,η(t_l))到控制器，并将t_l赋值给

即获取DoS攻击关键信息：攻击发起时刻

攻击总次数N₀、攻击驻留总时长D₀、被攻击的采样数和最大驻留时间h_M。The comparator judges the maximum dwell time h _M and

size, if h _M is less than

then update

Send the signal (σ ₁ ,σ ₂ )=(1,0) and the data packet (t _l ,η(t _l )) to the controller and assign t _l to

That is, to obtain the key information of the DoS attack: the moment when the attack was launched

The total number of attacks N ₀ , the total attack dwell time D ₀ , the number of attacked samples and the maximum dwell time h _M .

The controller controls the switching control gain according to the signal sent by the intelligent logic processor, and generates the second control signal according to the signal sent by the intelligent logic processor and the control gain. Specifically:

If the interval [t _l , t _l+1 ), l=1, 2, ... is not subject to DoS attack, then there is t _l+1 =t _l +T; then the controller is:

u _i (t)=-k _1i η _i (t _l ),t∈[t _l ,t _l +T),i=1,2,…m

Among them, m is the number of circuit systems; u _i (t) is the control input of the ith circuit system, k _1i is the control gain of the controller u _i (t); η _i (t _l ) is the ith circuit system Error state at time t _l ;

If the interval [t _l ,t _l+1 ),l=1,2,... suffers from DoS attacks, then t _l +T<t _l+1 ≤t _l +h _M ; then the controller is:

u _i (t)=-σ ₁ (t)k _1i η _i (t _l )-σ ₂ (t)k _2i η _i (t _l ),i=1,2,...m

σ₁(t)、σ₂(t)的取值分别是由智能逻辑处理器输出的第一关键参数σ₁、第二关键参数σ₂的值确定的，k_1i、k_2i是控制增益。in

The values of σ ₁ (t) and σ ₂ (t) are respectively determined by the values of the first key parameter σ ₁ and the second key parameter σ ₂ output by the intelligent logic processor, and k _1i and k _2i are control gains.

Compared with the prior art, the present invention has the following advantages and beneficial effects:

(1) The present invention combines an intelligent logic processor and a sampling control mechanism, adopts an adaptive sampling switching control method, adopts different controllers for different DoS attack situations, and can effectively enhance system resistance under the premise of ensuring the safety performance of complex circuit network systems Robustness to DoS attacks.

(2) The present invention designs an alarm device in the intelligent logic processor, which can automatically detect the moment when the system is attacked; through the intelligent logic processor, the total number of sampled points to be attacked can be obtained, and the DoS attack frequency and DoS attack domain can be established. , the relationship between the sampling period and the maximum dwell time.

(3) The present invention adaptively selects control gains for different attack situations, thereby effectively enhancing the robustness of the system against DoS attacks.

Description of drawings

Figure 1 is the circuit diagram of Cai;

Fig. 2 is the track diagram of Cai's circuit system;

Fig. 3 is a communication topology diagram structure diagram between circuit systems;

Fig. 4 is the control flow chart of complex circuit network system under DoS attack;

Fig. 5 is the logic operation flow chart of the comparator of the present invention;

6 is a flowchart of a comparator in the prior art;

Figure 7 is a sequence diagram of a DoS attack;

Fig. 8 is a complex circuit network system node trajectory diagram;

Fig. 9 is a synchronization error diagram;

Figure 10 is a diagram of an adaptive sampling switching controller.

Detailed ways

The present invention will be further described in detail below with reference to the examples, but the embodiments of the present invention are not limited thereto.

Example:

An adaptive sampling switching control method for a complex circuit network system under DoS attack, comprising:

1. System parameter setting: Take the circuit system as the Cai circuit as an example, the Cai circuit is shown in Figure ₁ , where R, R1 are resistors, _C1 , _C2 are capacitors, L is inductance _; V1, _V2 are respectively The voltages across the capacitors C ₁ and C ₂ , i ₁ , i _R are the currents flowing through the inductor L and the resistor R respectively; g is the nonlinear resistance;

2. According to Kirchhoff's current law, the dynamic characteristics of the circuit system are:

where g(V ₂ ) is the current flowing through the nonlinear resistor g, defined as:

Wherein _Ga , _Gb , E are diode parameters.

(1)可变为如下形式by variable substitution

(1) It can be changed to the following form

m₁＝RG_b，m₂＝RG_a，

这里取γ₁＝-1.3018，γ₂＝-0.0135，γ₃＝-0.0297，m₁＝-0.5700，m₂＝0.1091。在初值[0.9,-1.1,0.05]^T下，上述电路系统状态轨迹图如图2所示，从图2可以看出系统展现出混沌行为。in

m ₁ =RG _b , m ₂ =RG _a ,

Here, γ ₁ =-1.3018, γ ₂ =-0.0135, γ ₃ =-0.0297, m ₁ =-0.5700, and m ₂ =0.1091. Under the initial value [0.9,-1.1,0.05] ^T , the state trajectory diagram of the above circuit system is shown in Figure 2. From Figure 2, it can be seen that the system exhibits chaotic behavior.

3. Describe the network communication connection topology of the multi-circuit system: Take the communication connection topology relationship of five circuit systems as an example, as shown in Figure 3, each circuit system and the target system are Cai circuit systems. Set a communication connection coefficient b _ij , if the information of the jth (j=1,2,...,5) circuit system can be transmitted to the ith (i=1,2,...,5) circuit system, then b _ij >0, otherwise b _ij =0. Let b ₁₂ =0.57, b ₂₁ =6.65, b ₄₅ =5.5, b ₅₄ =0.6, then the Laplacian matrix L, weighted adjacency matrix B and in-degree matrix D of the topology can be obtained as:

D=diag{0.57, 6.65, 0, 5.5, 0.6}.

比较器通过执行一些逻辑操作来捕获DoS攻击信息，具体逻辑操作如图5所示，设置初始参数，

为采样时刻且

N₀表示DoS攻击的发生次数，D₀表示被检测后的攻击驻留总时长，h_M表示最大驻留时间。σ₁,σ₂是控制器的关键参数，用以自适应调节控制输入。并赋初值

N₀＝0，D₀＝0，h_M＝T，σ₁＝1，σ₂＝0。4. Suppose the state variables of the circuit system and the target system are θ _i (t) (i=1, 2,...5) and ι(t) respectively, then the error state is η _i (t)=θ _i (t)- ι(t) (i=1,2,...5). Under the DoS attack, the control flow chart of the complex circuit network system is shown in Figure 4. In Fig. 4, η _i (t) (i=1, 2,...5) is first sampled by the sensor with a period T, and the sampling point sequence is S={s ₀ ,s ₁ ,...,s _l ,...}, where s ₀ =0 and s _l =1T. Then the data packet (s _l , η _i (s _l )) composed of the sampling point s _l and the sampling state η _i (s _l ) (i=1, 2, . . . , 5) is sent by the transmitter to the communication network, via The controller, zero-order retainer, and actuator are then fed back to the complex circuit network system. If the channel from the sensor to the controller suffers a DoS attack, the packets (s _l , η _i (s _l )) cannot reach the controller. In order to analyze the impact of DoS attack, the present invention designs a new intelligent logic processor. The intelligent logic processor consists of a buffer and a comparator. The buffer is used to store the latest sampling packets. When the data in the buffer is updated, the updated data will be used to generate the control signal immediately to realize the security synchronization control performance of the system, and the sequence of time points when the controller receives the data packet is set as

The comparator captures DoS attack information by performing some logical operations. The specific logical operations are shown in Figure 5. The initial parameters are set,

is the sampling time and

N ₀ represents the number of occurrences of DoS attacks, D ₀ represents the total residence time of the attack after detection, and h _M represents the maximum residence time. σ ₁ , σ ₂ are the key parameters of the controller to adjust the control input adaptively. and assign initial value

N ₀ =0, D ₀ =0, h _M =T, σ ₁ =1, σ ₂ =0.

比较器首先会判断数据包

是否到达缓存器。如果到达，则把

赋值给t_l，发送信号(σ₁,σ₂)＝(1,0)和数据包(t_l,η(t_l))到控制器，并将t_l的值赋值给

如果未到达，警报器被触发，说明数据包

遭受了DoS攻击，此时

为攻击发起时刻。这时，更新DoS攻击发生次数N₀＝N₀+1，发送信号(σ₁,σ₂)＝(0,1)到控制器，并等待采样数据包(t_l,η(t_l))到达缓存器。如果数据包(t_l,η(t_l))到达缓存器，则这次攻击结束，更新

其中

表示该次攻击在被检测后的持续时间，

为被检测时间点。然后比较器将进一步判断最大驻留时间h_M与

的大小，如果h_M小于

则更新

发送信号(σ₁,σ₂)＝(1,0)和数据包(t_l,η(t_l))到控制器，并将t_l赋值给

通过比较器，DoS攻击关键信息包括攻击发起时刻、攻击总次数、攻击驻留总时长、被攻击的采样数和最大驻留时间可被获得。Let η(t) = [η ₁ ^T (t), η ₂ ^T (t), . . . , η ₅ ^T (t)] ^T . for a given initial value and

The comparator first judges the packet

whether to reach the buffer. If it arrives, put

assign to t _l , send the signal (σ ₁ ,σ ₂ )=(1,0) and the data packet (t _l ,η(t _l )) to the controller, and assign the value of t _l to

If it doesn't arrive, the alarm is triggered, indicating that the packet

suffered a DoS attack,

Time for the attack. At this time, update the number of DoS attacks N ₀ =N ₀ +1, send the signal (σ ₁ ,σ ₂ )=(0,1) to the controller, and wait for the sampling data packet (t _l ,η(t _l )) reach the buffer. If the data packet (t _l , η(t _l )) reaches the buffer, the attack ends, and the update

in

Indicates the duration of the attack after it was detected,

is the detected time point. Then the comparator will further judge the maximum dwell time h _M and

size, if h _M is less than

then update

Send the signal (σ ₁ ,σ ₂ )=(1,0) and the data packet (t _l ,η(t _l )) to the controller and assign t _l to

Through the comparator, the key information of the DoS attack, including the attack initiation time, the total number of attacks, the total duration of the attack residence, the number of attacked samples, and the maximum residence time can be obtained.

Since the attacker's energy is usually limited, in this case, the DoS attack frequency and DoS attack domain will meet certain constraints. In order to better understand the DoS attack and expose the internal connection between the key information of the DoS attack, for a given time interval [t ₀ , t), define D(t) as the total duration of all detected DoS attacks, N (t) is the total number of attacks that have occurred. According to the operating principle of the intelligent logic processor, the relationship between the frequency of DoS attacks, the DoS attack domain, the sampling period and the maximum dwell time can be established as follows:

where: t∈[t _l ,t _l+1 ),

为被攻击的采样点总数，

表示向下取整，

表示t_j的左极限，h_l＝t_l+1-t_l∈(T,h_M]。but

is the total number of sampling points attacked,

means round down,

represents the left limit of t _j , h _l =t _l+1 -t _l ∈(T,h _M ].

Prove: For t∈[t _l ,t _l+1 ), l=0,1,2...have

则

根据该结论则有Note that if

but

According to this conclusion, there are

From (4), we can get

From equations (4) and (5), (2) and (3) can be obtained.

分别表示逻辑处理器成功接收到的数据包时刻、最小攻击驻留时间、最大攻击驻留时间、攻击总次数、攻击驻域(攻击驻留时间总和)、两个相邻成功传输数据包之间的时间间隔和特定时间内逻辑处理器成功接收到的数据包时刻。如果两个相邻成功传输数据包之间的时间间隔Δ不大于采样周期T₀，则将d_k赋值给

如果两个相邻成功传输数据包之间的时间间隔Δ大于采样周期T₀，则将T_m+Δ-T₀赋值给T_m，更新n₀＝n₀+1；并进一步判断当前两个相邻成功传输数据包之间的时间间隔Δ是否大于h_M。如果是，则将Δ赋值给h_M，如果否，进一步Δ是否小于等于h_m，如果是，将Δ-T₀赋值给h_m，如果否将d_k赋值给

与现有技术中比较器相比，本发明所设计的比较器有如下优点：①操作流程中安装了警报器，该警报器可自动检测系统被DoS攻击时刻；②可得到被攻击采样点总数

③并可建立DoS攻击频率N(t)、DoS攻击驻域D(t)、采样周期T和最大驻留时间h_M之间的关系

④可根据不同的攻击情形，反馈不同的控制参数。FIG. 6 is a flow chart of a comparator in the prior art, wherein d _k , h _m , h _M , n ₀ , T _m , Δ and

Respectively represent the time of the packet successfully received by the logical processor, the minimum attack dwell time, the maximum attack dwell time, the total number of attacks, the attack dwell domain (the sum of the attack dwell time), and the interval between two adjacent successfully transmitted packets. The time interval and the moment when the logical processor successfully received the packet within the specified time. If the time interval Δ between two adjacent successfully transmitted data packets is not greater than the sampling period T ₀ , then assign d _k to

If the time interval Δ between two adjacent successfully transmitted data packets is greater than the sampling period T ₀ , assign T _m +Δ-T ₀ to T _m , update n ₀ =n ₀ +1; and further judge the current two Whether the time interval Δ between adjacent successfully transmitted data packets is greater than h _M . If yes, assign Δ to h _M , if no, whether further Δ is less than or equal to h _m , if yes, assign Δ-T ₀ to h _m , if no, assign d _k to

Compared with the comparator in the prior art, the comparator designed by the present invention has the following advantages: 1. an alarm device is installed in the operation process, and the alarm device can automatically detect the moment when the system is attacked by DoS; 2. the total number of sampling points to be attacked can be obtained

③ The relationship between DoS attack frequency N(t), DoS attack resident area D(t), sampling period T and maximum residence time h _M can be established

④ Different control parameters can be fed back according to different attack situations.

5. Design of adaptive sampling switching controller. The controller cooperates closely with the intelligent logic processor. When the intelligent logic processor receives the sampling data packet, the controller immediately uses the sampling packet to generate the control signal, and then uses the zero-order hold, and the discrete sampling control signal is converted into continuous sampling. The signal is fed back to the system through the actuator to drive the complex circuit network system. The adaptive sampling switching control protocol in the controller is designed as follows:

Case i: If the interval [t _l , t _l+1 ), l=1, 2, ... is not subject to DoS attack, then there is t _l+1 =t _l +T;

Case ii: If the interval [t _l , t _l+1 ), l=1, 2, . . . suffers from a DoS attack, then t _l +T<t _l+1 ≤t _l +h _M .

For case i, design the following sampling controller

u _i (t)=-k _1i η _i (t _l ),t∈[t _l ,t _l +T),i=1,2,…5 (6)

where u _i (t) is the control input of the ith circuit system and k _1i is the control gain of the controller u _i (t).

For case ii, design the following sampling controller

u _i (t)=-σ ₁ (t)k _1i η _i (t _l )-σ ₂ (t)k _2i η _i (t _l ),i=1,2,...5 (7)

σ₁(t)、σ₂(t)的取值分别是由逻辑处理器输出的σ₁、σ₂的值确定的，k_1i、k_2i(i＝1,2,…,5)是控制增益。in

The values of σ ₁ (t) and σ ₂ (t) are determined by the values of σ ₁ and σ ₂ output by the logic processor, respectively, and k _1i and k _2i (i=1,2,...,5) are control gain.

Regardless of whether a DoS attack occurs, the controller in the prior art has a constant control gain. The present invention designs an adaptive sampling switching control protocol—formulas (6) and (7) according to different attack situations. In this protocol, for any interval [t _l , t _l+1 ), according to different attack situations, under the premise of ensuring the safety and synchronization performance of complex circuit network systems, different control gains k _1i and k _2i (i=1, 2, ...,5) will be selected. If no DoS attack occurs in the interval [t _l , t _l+1 ), the control gain k _1i is adopted. If a DoS attack occurs on the interval [t _l , t _l+1 ), the data packet (t _l +T, η _i (t _l +T)) will not reach the buffer, and the logical processor will issue an alarm immediately. In this case, when t∈[t _l , t _l +T), the control gain k _1i is used; when t∈[t _l +T, t _l+1 ), the control gain k _2i is used. The adaptive switching selection of k _1i and k _2i is determined by the values of the logic processor outputs σ ₁ and σ ₂ . Compared with the control methods in the prior art, the adaptive sampling switching control method proposed by the present invention is more flexible, and can effectively enhance the robustness of the system against DoS attacks.

In order to verify the effectiveness of the present invention and the advantages of the method, the following simulation experiments are carried out. Considering that the sensor-to-controller channel of the above complex circuit network system suffers from DoS attacks, the attack sequence is shown in Figure 7. According to the knowledge of graph theory, when nodes 1, 3, and 5 are pinned down, then Figure 3 has a spanning tree. Under the DoS attack shown in Figure 7, take the control gain

k ₁₁ =10.1742, k ₁₂ =0, k ₁₃ =7.9494, k ₁₄ =0, k ₁₅ =12.9165,

k ₂₁ =4.9895, k ₂₂ =0, k ₂₃ =4.4786, k ₂₄ =0, k ₂₅ =5.0785.

Under the control of the adaptive sampling switching control protocol - formulas (6) and (7), the node trajectory diagram, synchronization error trajectory diagram and adaptive sampling switching controller diagram of the complex circuit network system are shown in Figure 8, Figure 9 and Figure 9, respectively. shown in Figure 10. From Figure 8, it can be found that the state trajectories of all nodes are synchronized, and from Figure 9, it can be found that the synchronization error tends to 0, thereby verifying that the adaptive sampling switching control method designed in the present invention can effectively resist the impact of DoS attacks and ensure that Safe synchronization performance of complex circuit network systems.

Under the same system parameters above, the maximum attack dwell time h _M = 0.18 can be obtained by the fixed control gain method in the prior art, and the maximum attack dwell time h _M can be obtained by the adaptive sampling switching control method designed in the present invention = 0.24. The larger the upper bound of the attack residence time, the stronger the robustness of the designed control method. Therefore, the control method of the present invention has a stronger anti-DoS attack capability, thereby enhancing the robustness of the complex circuit network system against DoS attacks.

Although the present invention is described herein with reference to the illustrative embodiments of the present invention, the above-mentioned embodiments are only preferred embodiments of the present invention, and the embodiments of the present invention are not limited by the above-mentioned embodiments, and it should be understood that those skilled in the art Numerous other modifications and embodiments can be devised that will fall within the scope and spirit of the principles disclosed herein.

Claims (3)

1. the adaptive sampling switching control method of complex circuit network system under a DoS attack, is characterized in that, comprises: Step S100, the sensor samples the complex circuit network system with a period T to obtain the error sampling state and sampling point sequence of the circuit system; Step S200, the transmitter sends the data packet composed of the error sampling state and the sampling point sequence to the communication network; Step S300, when the data packet reaches the buffer of the intelligent logic processor, and the data in the buffer is updated, the first control signal is immediately generated, and the first control signal is used to realize the system safety synchronization control; the intelligent logic processor sends the data to the controller time point sequence of packets, time point sequence

Sampling point sequence; the comparator of the intelligent logic processor captures the key information of the DoS attack according to the data packet and time point sequence, and the intelligent logic processor sends different signals to the controller according to the key information of the DoS attack; Step S400, the controller determines the key parameters of the switching control gain according to the signal sent by the intelligent logic processor, and generates a second control signal according to the signal sent by the intelligent logic processor and the control gain, and then uses the zero-order holder to discretely sample the second control signal. The signal is converted into a continuous signal, and then fed back to the complex circuit network system through the actuator, thereby driving the complex circuit network system. 2. the adaptive sampling switching control method of complex circuit network system under the DoS attack according to claim 1, is characterized in that, capturing the DoS attack key information specifically comprises: Initial sampling time

The number of occurrences of DoS attacks N ₀ =0, the total attack residence time after detection D ₀ =0, the maximum residence time h _M =T, the first key parameter σ ₁ =1 and the second key parameter σ ₂ =0 ,in,

The first key parameter σ ₁ and the second key parameter σ ₂ are used for the controller to adaptively adjust the control input; Let the systematic error state η(t)=[η ₁ ^T (t),η ₂ ^T (t),...,η _i ^T (t),...] ^T , where η _i ^T (t) is the ith circuit the error state of the system; for a given initial value and

The comparator first judges the packet

Whether to reach the buffer, if so, put

Assign the current time point t _l of the time point sequence, send the signal (σ ₁ ,σ ₂ )=(1,0) and the data packet (t _l ,η(t _l )) to the controller, and use the value of t _l assign to

If it doesn't arrive, the siren is triggered, i.e. the packet

suffered a DoS attack,

is the attack initiation time; update the number of DoS attacks N ₀ =N ₀ +1, send signals (σ ₁ ,σ ₂ )=(0,1) to the controller, and wait for the sampling data packets (t _l ,η(t _{l )} )) reach the buffer, if the data packet (t _l , η(t _l )) reaches the buffer, the attack ends, and the update

in

Indicates the duration of the attack after it was detected,

is the detected time point; The comparator judges the maximum dwell time h _M and

size, if h _M is less than

then update

Send the signal (σ ₁ ,σ ₂ )=(1,0) and the data packet (t _l ,η(t _l )) to the controller and assign t _l to

That is, to obtain the key information of the DoS attack: the moment when the attack was launched

The total number of attacks N ₀ , the total attack dwell time D ₀ , the number of attacked samples and the maximum dwell time h _M . 3. the adaptive sampling switching control method of the complex circuit network system under the DoS attack according to claim 2, is characterized in that, the controller switches the control gain parameter according to the signal sent by the intelligent logic processor, and according to the intelligent logic processor The transmitted signal and the control gain to generate the second control signal are specifically: If the interval [t _l , t _l+1 ), l=1, 2, ... is not subject to DoS attack, then there is t _l+1 =t _l +T; then the controller is: u _i (t)=-k _1i η _i (t _l ),t∈[t _l ,t _l +T),i=1,2,…m Among them, m is the number of circuit systems; u _i (t) is the control input of the ith circuit system, k _1i is the control gain of the controller u _i (t); η _i (t _l ) is the ith circuit system Error state at time t _l ; If the interval [t _l ,t _l+1 ),l=1,2,... suffers from DoS attacks, then t _l +T<t _l+1 ≤t _l +h _M ; then the controller is: u _i (t)=-σ ₁ (t)k _1i η _i (t _l )-σ ₂ (t)k _2i η _i (t _l ),i=1,2,...m in

The values of σ ₁ (t) and σ ₂ (t) are respectively determined by the values of the first key parameter σ ₁ and the second key parameter σ ₂ output by the intelligent logic processor, and k _1i and k _2i are control gains.

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