CN114995158A - Self-adaptive sampling switching control method of complex circuit network system under DoS attack - Google Patents
Self-adaptive sampling switching control method of complex circuit network system under DoS attack Download PDFInfo
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Abstract
The invention discloses a self-adaptive sampling switching control method of a complex circuit network system under DoS attack, wherein a sensor samples the complex circuit network system in a period T, and a transmitter transmits a data packet consisting of an error sampling state and a sampling point sequence to a communication network; when a data packet arrives at the buffer, the buffer immediately generates a first control signal, the comparator captures DoS attack key information according to the data packet and a time point sequence, and the intelligent logic processor sends different signals to the controller according to the DoS attack key information; the controller controls the switching control gain parameter according to the signal sent by the intelligent logic processor, and the signal is fed back to the complex circuit network system through the zero-order retainer and the actuator, so that the complex circuit network system is driven. The invention combines the intelligent logic processor and the self-adaptive sampling switching control mechanism, adopts different controllers aiming at different DoS attack situations, and effectively enhances the robustness of the system against the DoS attack.
Description
Technical Field
The invention relates to the technical field of circuit system safety control, in particular to a self-adaptive sampling switching control method of a complex circuit network system under DoS attack.
Background
With the rapid development of networking and informatization, the complex circuit network system brings wealth and convenience to people and also increasingly highlights the safety problem. The complex circuit network system is a complex system formed by a plurality of circuit systems connected through a network. The interior of each circuit system is an organic whole formed by a sensor, a controller, an actuator, a network and the like, and the circuit systems are in information interaction through the network. Due to the high openness and sharing of the network, the network is easy to attack. The frequency of global cyber attack events has led to an increasing awareness of the importance of network security in recent years. Since the network security control can effectively resist various network attacks, the security control of the complex circuit network system becomes a key point of research. For a complex circuit network system, most of the current control methods are mainly designed based on continuous feedback information. In continuous feedback control, information of the state variables needs to be continuously transmitted to the controller and fed back to the system. This continuous feedback control mode is somewhat wasteful of computational and network communication resources. Compared with a continuous feedback control method, sampling control only needs to transmit signals at sampling points to a controller, so that the information transmission quantity can be greatly reduced, and network communication resources are effectively saved. At present, the sampling control of a complex circuit network system becomes a research focus. DoS attacks, a common type of network attacks, can seriously affect the synchronization performance and security of complex circuit network systems. Therefore, it is far-reaching to explore the safety sampling control of the complex circuit network system under the DoS attack, but at present, the related research is lacked. In addition, in order to effectively resist the influence of DoS attacks on the performance of the network system, the document "flexible control design of a type of networked control system based on a sampling model under DoS attacks", IEEE control journal, 2020 and 8 months "proposes a flexible security sampling control method under a sampling mode. In the method, in order to capture DoS attack information, an author embeds a logic processor in a sampling controller design, and the method is successfully applied to solve the problem of consistency of a multi-agent system under DoS attack. However, the method has three disadvantages: (1) the designed logic processor can not fully capture the key information of DoS attack, such as the total number of attacked sampling points and attack initiation time; (2) neglecting the relationship among the DoS attack frequency, the DoS attack dwell, the sampling period and the maximum dwell time; (3) the same control gain is used at all times regardless of whether DoS attack occurs, which may result in poor control robustness to some extent.
Disclosure of Invention
The invention aims to provide a self-adaptive sampling switching control method of a complex circuit network system under DoS attack, which is used for solving the problems that the key information of the DoS attack cannot be fully captured, the relation between the DoS attack frequency, the DoS attack dwell, the sampling period and the maximum dwell time is ignored and the control robustness is poor when the elastic safety sampling control method in the prior art resists the influence of the DoS attack on the network system performance.
The invention solves the problems through the following technical scheme:
a self-adaptive sampling switching control method of a complex circuit network system under DoS attack comprises the following steps:
s100, sampling a complex circuit network system by a sensor in a period T to obtain an error sampling state and a sampling point sequence of the circuit system;
the sensor samples the complex circuit network system with a period T to obtain a sampling point s of the ith circuit system l Error sampling state eta of i (s l ) And the sequence of sampling points S ═ S { (S) } 0 ,s 1 ,…,s l ,…,s L In which s is 0 ＝0，s l ＝lT，s l For the sampling time, L is the sampling number, L is 0,1,2, … …, L; 1,2, 3, … …, m; m is the number of circuit systems;
step S200, a data packet formed by the error sampling state and the sampling point sequence is sent to a communication network by a sender; i.e. data packet(s) l ,η i (s l ) ) is sampled by error i (s l ) And the sequence of sampling points S ═ S { (S) } 0 ,s 1 ,…,s l ,…,s L }；
Step S300, when the data packet arrives at a buffer of the intelligent logic processor, a first control signal is immediately generated when the data of the buffer is updated, and the first control signal is used for realizing the safety synchronous control of the system; when the intelligent logic processor sends data packet to the controllerPunctuation sequence
A comparator of the intelligent logic processor captures the DoS attack key information according to the data packet and the time point sequence, and the intelligent logic processor sends different signals to the controller according to the DoS attack key information;
and S400, controlling a switching control gain parameter according to a signal sent by the intelligent logic processor by the controller, generating a second control signal according to the signal sent by the intelligent logic processor and the control gain, converting the discretely sampled second control signal into a continuous signal by using a zero-order retainer, and feeding back the continuous signal to the complex circuit network system through the actuator so as to drive the complex circuit network system.
Capturing DoS attack key information specifically includes:
initializing sampling instants
Number of occurrences of DoS attack N 0 0, total attack dwell time D after detection 0 0, maximum residence time h M T, first key parameter σ 1 1 and a second critical parameter σ 2 0, wherein,
first key parameter σ 1 And a second critical parameter σ 2 For the controller to adaptively adjust the control input;
let system error state eta (t) be [ eta ] 1 T (t),η 2 T (t),…,η i T (t),…] T Wherein η i T (t) is the error state of the ith circuitry;
for a given initial value and
the comparator first determines the packet
Whether it arrives in the buffer, if so, will
Assigning to a current time t of a sequence of time points l Sending a signal (σ) 1 ,σ 2 ) ═ 1,0 and packet (t) l ,η(t l ) To the controller and will t l Is assigned to
If not, an alarm is triggered, i.e. a data packet
Has suffered a DoS attack at the moment
Initiating a moment for an attack; updating DoS attack occurrence number N 0 ＝N 0 +1, transmission signal (σ) 1 ,σ 2 ) To the controller and waits for a sample packet (t) l ,η(t l ) Arrives in the buffer if the packet (t) l ,η(t l ) When the cache is reached, the attack is ended and the update is performed
Wherein
Indicating the duration of the attack after detection,
is the detected time point;
the comparator judges the maximum residence time h M And
if h is greater than M Is less than
Then update
Transmission signal (sigma) 1 ,σ 2 ) ═ 1,0 and packet (t) l ,η(t l ) To the controller and will t l Is assigned to
Namely acquiring the key information of the DoS attack: attack launch time
Total number of attacks N 0 Total duration of attack stay D 0 The number of samples attacked and the maximum dwell time h M 。
The controller controls the switching control gain according to the signal sent by the intelligent logic processor, and generates a second control signal according to the signal sent by the intelligent logic processor and the control gain, specifically:
if the interval [ t l ,t l+1 ) If the DoS attack is not sustained, then there is t l+1 ＝t l + T; the controller is then:
u i (t)＝-k 1i η i (t l ),t∈[t l ,t l +T),i＝1,2,…m
wherein m is the number of circuit systems; u. of i (t) is the control input of the ith circuitry, k 1i Is a controller u i (t) a control gain; eta i (t l ) For the ith circuit system at time t l The error state of (2);
if the interval [ t l ,t l+1 ) When DoS attacks are encountered, there is t l +T＜t l+1 ≤t l +h M (ii) a The controller is then:
u i (t)＝-σ 1 (t)k 1i η i (t l )-σ 2 (t)k 2i η i (t l ),i＝1,2,…m
wherein
σ 1 (t)、σ 2 The values of (t) are respectively the first key parameter sigma output by the intelligent logic processor 1 Second key parameter σ 2 Is determined by the value of (a) 1i 、k 2i Is the control gain.
Compared with the prior art, the invention has the following advantages and beneficial effects:
(1) the invention combines the intelligent logic processor and the sampling control mechanism, adopts the self-adaptive sampling switching control method, adopts different controllers aiming at different DoS attack situations, and can effectively enhance the robustness of the system against the DoS attack on the premise of ensuring the safety performance of a complex circuit network system.
(2) The invention designs an alarm in the intelligent logic processor, which can automatically detect the time when the system is attacked; the total number of the attacked sampling points is obtained through the intelligent logic processor, and the relationship among the DoS attack frequency, the DoS attack dwell, the sampling period and the maximum dwell time can be established.
(3) The invention adaptively selects and controls the gain aiming at different attack situations, thereby effectively enhancing the robustness of the system against the DoS attack.
Drawings
FIG. 1 is a schematic diagram of a Chua circuit system;
FIG. 2 is a schematic diagram of a Chua circuit system;
FIG. 3 is a diagram of a topology for communication between circuitry;
FIG. 4 is a control flow chart of a complex circuit network system under DoS attack;
FIG. 5 is a flow chart of the logical operation of the comparator of the present invention;
FIG. 6 is a flow chart of a prior art comparator;
FIG. 7 is a sequence diagram of a DoS attack;
FIG. 8 is a node trace diagram of a complex circuit network system;
FIG. 9 is a synchronization error map;
FIG. 10 is a diagram of an adaptive sampling switch controller.
Detailed Description
The present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
Example (b):
a self-adaptive sampling switching control method of a complex circuit network system under DoS attack comprises the following steps:
1. setting system parameters: taking the circuit system as a Chua circuit as an example, the Chua circuit is shown in figure 1, wherein R, R 1 Is a resistance, C 1 ，C 2 Is a capacitance, L is an inductance; v 1 ，V 2 Are respectively a capacitance C 1 ，C 2 Voltage across, i 1 ，i R Respectively, the current flowing through the inductor L and the resistor R; g is a nonlinear resistance;
2. according to kirchhoff's current law, the dynamic characteristics of the circuit system are as follows:
wherein g (V) 2 ) The current flowing through the nonlinear resistor g is defined as:
wherein G a ，G b And E is the diode parameter.
By substitution of variables
(1) Can be changed into the following forms
Wherein
m 1 ＝RG b ，m 2 ＝RG a ，
Here, take γ 1 ＝-1.3018，γ 2 ＝-0.0135，γ 3 ＝-0.0297，m 1 ＝-0.5700，m 2 0.1091. At an initial value of [0.9, -1.1,0.05] T Next, the state trace diagram of the circuit system is shown in fig. 2, and it can be seen from fig. 2 that the system exhibits chaotic behavior.
3. Describing a network communication connection topological structure of a multi-circuit system: taking the communication connection topology of 5 circuit systems as an example, as shown in fig. 3, each circuit system and the target system are all Chua circuit systems. Setting a communication connection factor b ij If information of the j (j) th circuit system can be transferred to the i (i) th circuit system (1, 2, …,5), b ij > 0, otherwise b ij 0. Let b 12 ＝0.57，b 21 ＝6.65，b 45 ＝5.5，b 54 If 0.6, the Laplacian matrix L, the weighted adjacency matrix B, and the degree matrix D of the topology are:
D＝diag{0.57,6.65,0,5.5,0.6}。
4. let the state variables of the circuit system and the target system be theta i (t) (i ═ 1,2, … 5) and iota (t), the error state is η i (t)＝θ i (t) -iota (t) (i ═ 1,2, … 5). Fig. 4 shows a control flow chart of a complex circuit network system under DoS attack. In FIG. 4,. eta. i (T) (i ═ 1,2, … 5) is first sampled by the sensor at period T, with the sequence of sampling points S ═ S 0 ,s 1 ,…,s l … } in which s 0 ＝0，s l lT. Then from the sampling point s l And a sampling state η i (s l ) (i-1, 2, …,5) packet(s) l ,η i (s l ) Is sent to the communication network by the transmitter and is fed back to the complex circuit network system through the controller, the zero-order keeper and the actuator. If from the sensor to the controllerThe channel is subjected to DoS attack, then the data packet(s) l ,η i (s l ) Does not reach the controller. In order to analyze the influence of DoS attack, the invention designs a new intelligent logic processor. The intelligent logic processor is composed of a buffer and a comparator. The buffer is used for storing the latest sampling packet. When the data in the buffer is updated, the updated data is immediately used for generating a control signal to realize the safety synchronous control performance of the system, and the time point sequence of the data packets received by the controller is set as
The comparator captures DoS attack information by performing some logical operations, as shown in fig. 5, setting initial parameters,
is the sampling time and
N 0 representing the number of occurrences of a DoS attack, D 0 Represents the total duration of attack residency after detection, h M Indicating the maximum dwell time. Sigma 1 ,σ 2 Is a key parameter of the controller for adaptive adjustment of the control input. And assigning an initial value
N 0 ＝0，D 0 ＝0，h M ＝T，σ 1 ＝1，σ 2 ＝0。
Let eta (t) equal to [ eta 1 T (t),η 2 T (t),…,η 5 T (t)] T . For a given initial value and
the comparator will first determine the data packet
Whether or not to reach the buffer. If so, the device will
Is assigned to t l Sending a signal (σ) 1 ,σ 2 ) (1,0) and packet (t) l ,η(t l ) To the controller and will t l Is assigned to
If not, an alarm is triggered indicating a data packet
Has suffered a DoS attack at the moment
The moment of attack launch. At this time, the number N of occurrences of DoS attack is updated 0 ＝N 0 +1, transmission signal (σ) 1 ,σ 2 ) (0,1) to the controller and waits for a sample packet (t) l ,η(t l ) ) arrives at the buffer. If data packet (t) l ,η(t l ) When the cache is reached, the attack is ended and the update is performed
Wherein
Indicating the duration of the attack after detection,
is the detected time point. The comparator will then further determine the maximum dwell time h M And
if h is M Is less than
Then update
Transmission signal (sigma) 1 ,σ 2 ) ═ 1,0 and packet (t) l ,η(t l ) To the controller and will t l Assign to
Through the comparator, the DoS attack key information including attack initiation time, total attack times, total attack residence time, the number of attacked samples and maximum residence time can be obtained.
Since the energy of an attacker is usually limited, in this case, the DoS attack frequency and DoS attack dwell satisfy certain constraints. To better understand DoS attacks, the links between the insides of the key information of DoS attacks are revealed, for a given time interval t 0 And t), defining D (t) as the total residence time of all the detected DoS attacks, and N (t) as the total times of the attacks, and according to the operation principle of the intelligent logic processor, establishing the following relations among the DoS attack frequency, the DoS attack residence domain, the sampling period and the maximum residence time:
wherein: t is an element of [ t ] l ,t l+1 )，
Then the
Is the total number of samples that are attacked,
meaning that the rounding is done down,
represents t j Left limit of (d), h l ＝t l+1 -t l ∈(T,h M ]。
And (3) proving that: for t e [ t ∈ l ,t l+1 ) L is 0,1,2
It is noted that if
Then
According to the conclusion there are
From the formula (4), a
The expressions (2) and (3) are satisfied by the expressions (4) and (5).
FIG. 6 is a flow chart of a comparator in the prior art, wherein d k 、h m 、h M 、n 0 、T m Δ and
respectively representing the time of successfully receiving the data packet by the logic processor, the minimum attack dwell time, the maximum attack dwell time,Total number of attacks, attack dwell (sum of attack dwell times), time interval between two adjacent successfully transmitted packets, and the time of successfully received packets by the logical processor within a specified time. If the time interval delta between two adjacent successfully transmitted data packets is not greater than the sampling period T 0 Then d will be k Assign to
If the time interval delta between two adjacent successfully transmitted data packets is greater than the sampling period T 0 Then T will be m +Δ-T 0 Is assigned to T m Update n 0 ＝n 0 + 1; and further judging whether the time interval delta between the current two adjacent successfully transmitted data packets is greater than h M . If so, assign Δ to h M If not, whether or not further Delta is less than or equal to h m If so, will Δ -T 0 Is assigned to h m If not, d k Is assigned to
Compared with the comparator in the prior art, the comparator designed by the invention has the following advantages: firstly, an alarm is installed in the operation process, and the alarm can automatically detect the time when the system is attacked by the DoS; 2, obtaining total number of attacked sampling points
Thirdly, the DoS attack frequency N (T), the DoS attack residence domain D (T), the sampling period T and the maximum residence time h can be established M The relationship between
And fourthly, feeding back different control parameters according to different attack situations.
5. Design of the adaptive sampling switching controller. The controller is closely cooperated with the intelligent logic processor, when the intelligent logic processor receives a sampling data packet, the controller immediately uses the sampling data packet to generate a control signal, and then the discrete sampling control signal is converted into a continuous signal by using the zero-order retainer and then fed back to the system through the actuator, thereby driving the complex circuit network system. The adaptive sampling switching control protocol in the controller is designed as follows:
case i: if the interval [ t l ,t l+1 ) If the DoS attack is not sustained, then there is t l+1 ＝t l +T；
Case ii: if the interval [ t l ,t l+1 ) When DoS attacks are encountered, there is t l +T＜t l+1 ≤t l +h M 。
For case i, the following sampling controller is designed
u i (t)＝-k 1i η i (t l ),t∈[t l ,t l +T),i＝1,2,…5 (6)
Wherein u is i (t) is the control input of the ith circuitry, k 1i Is a controller u i (t) control gain.
For case ii, the following sampling controller is designed
u i (t)＝-σ 1 (t)k 1i η i (t l )-σ 2 (t)k 2i η i (t l ),i＝1,2,…5 (7)
Wherein
σ 1 (t)、σ 2 (t) is the value of σ output by the logic processor 1 、σ 2 Is determined by the value of (a) 1i 、k 2i (i ═ 1,2, …,5) is the control gain.
The prior art controller has a fixed and constant control gain regardless of whether a DoS attack has occurred. The invention designs the self-adaptive sampling switching control protocol according to different attack situations, namely formulas (6) and (7). In this protocol, for an arbitrary interval [ t ] l ,t l+1 ) According to different attack situations, on the premise of ensuring the safety synchronization performance of the complex circuit network system, different control gains k 1i 、k 2i (i ═ 1,2, …,5) will be selected. If in the interval [ t l ,t l+1 ) If DoS attack does not occur, the control gain k is adopted 1i . If in the interval [ t l ,t l+1 ) The DoS attack occurs, the data packet (t) l +T,η i (t l + T)) will not reach the register and the logical processor will immediately issue an alarm. In this case, at t ∈ [ t ] l ,t l + T), using control gain k 1i (ii) a At t ∈ [ t ] l +T,t l+1 ) While adopting a control gain k 2i 。k 1i And k 2i The adaptive switching selection is output by the logic processor 1 And σ 2 Is determined. Compared with the control method in the prior art, the self-adaptive sampling switching control method provided by the invention is more flexible, and can effectively enhance the robustness of the system against the DoS attack.
To verify the effectiveness of the present invention and the advantages of the method, the following simulation experiments were performed. Consider that the sensor-to-controller channel of the above complex circuit network system is subject to a DoS attack, the attack sequence of which is shown in fig. 7. According to the knowledge of graph theory, when nodes 1, 3 and 5 are contained, the graph 3 has a spanning tree. Under the DoS attack as shown in FIG. 7, the control gain is taken
k 11 ＝10.1742，k 12 ＝0，k 13 ＝7.9494，k 14 ＝0，k 15 ＝12.9165，
k 21 ＝4.9895，k 22 ＝0，k 23 ＝4.4786，k 24 ＝0，k 25 ＝5.0785。
Under the control of the adaptive sampling switching control protocol, equations (6) and (7), the node trajectory diagram, the synchronization error trajectory diagram and the adaptive sampling switching controller diagram of the complex circuit network system are respectively shown in fig. 8, fig. 9 and fig. 10. From fig. 8, it can be found that the state trajectories of all nodes reach synchronization, and from fig. 9, it can be found that the synchronization error tends to 0, thereby verifying that the adaptive sampling switching control method designed by the present invention can effectively resist DoS attack influence, and ensuring the safety synchronization performance of a complex circuit network system.
Under the same system parameters, the maximum attack can be obtained by the fixed control gain method in the prior artResidence time h M The maximum attack residence time h can be obtained by the self-adaptive sampling switching control method designed by the invention as 0.18 M 0.24. The larger the upper bound of attack residence time is, the stronger the robustness of the designed control method is. Therefore, the control method has stronger DoS attack resisting capability, thereby enhancing the robustness of the complex circuit network system against the DoS attack.
Although the present invention has been described herein with reference to the illustrated embodiments thereof, which are intended to be preferred embodiments of the present invention, it is to be understood that the invention is not limited thereto, and that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure.
Claims (3)
1. A self-adaptive sampling switching control method of a complex circuit network system under DoS attack is characterized by comprising the following steps:
s100, sampling a complex circuit network system by a sensor in a period T to obtain an error sampling state and a sampling point sequence of the circuit system;
step S200, a data packet formed by the error sampling state and the sampling point sequence is sent to a communication network by a sender;
step S300, when the data packet arrives at a buffer of the intelligent logic processor, a first control signal is immediately generated when the data of the buffer is updated, and the first control signal is used for realizing the safety synchronous control of the system; time point sequence for sending data packet to controller by intelligent logic processor
Sampling point sequences; a comparator of the intelligent logic processor captures the key information of the DoS attack according to the data packet and the time point sequence, and the intelligent logic processor sends different signals to the controller according to the key information of the DoS attack;
and S400, determining a key parameter of switching control gain by the controller according to a signal sent by the intelligent logic processor, generating a second control signal according to the signal sent by the intelligent logic processor and the control gain, converting the discretely sampled second control signal into a continuous signal by using a zero-order retainer, and feeding back the continuous signal to the complex circuit network system through the actuator so as to drive the complex circuit network system.
2. The method for controlling adaptive sampling switching of a complex circuit network system under DoS attack as claimed in claim 1, wherein capturing the DoS attack key information specifically includes:
initializing sampling instants
Number of occurrences of DoS attack N 0 0, total attack dwell time D after detection 0 0, maximum dwell time h M T, first key parameter σ 1 1 and a second critical parameter σ 2 0, wherein,
first key parameter σ 1 And a second critical parameter σ 2 For the controller to adaptively adjust the control input;
let system error state eta (t) be [ eta ] 1 T (t),η 2 T (t),…,η i T (t),…] T Wherein η i T (t) is the error state of the ith circuitry;
for a given initial value sum
The comparator first judges the data packet
Whether it arrives in the buffer, if so, will
Assigning values to sequences of time pointsCurrent point in time t l Sending a signal (σ) 1 ,σ 2 ) (1,0) and packet (t) l ,η(t l ) To the controller and will t l Is assigned to
If not, an alarm is triggered, i.e. a data packet
Has suffered a DoS attack at the moment
Initiating a moment for an attack; updating DoS attack occurrence number N 0 ＝N 0 +1, transmission signal (σ) 1 ,σ 2 ) (0,1) to the controller and waits for a sample packet (t) l ,η(t l ) If the packet (t) arrives in the buffer l ,η(t l ) When the cache is reached, the attack is ended and the update is performed
Wherein
Indicating the duration of the attack after detection,
is the detected time point;
the comparator judges the maximum residence time h M And
if h is M Is less than
Then update
Transmission signal (sigma) 1 ,σ 2 ) ═ 1,0 and packet (t) l ,η(t l ) To the controller and will t l Is assigned to
Namely acquiring the key information of the DoS attack: attack launch time
Total number of attacks N 0 Total duration of attack stay D 0 The number of samples attacked and the maximum dwell time h M 。
3. The adaptive sampling switching control method for the complex circuit network system under DoS attack as recited in claim 2, wherein the controller controls the switching control gain parameter according to the signal sent by the intelligent logic processor, and the generating of the second control signal according to the signal sent by the intelligent logic processor and the control gain specifically comprises:
if the interval [ t l ,t l+1 ) If the DoS attack is not sustained, then there is t l+1 ＝t l + T; the controller is then:
u i (t)＝-k 1i η i (t l ),t∈[t l ,t l +T),i＝1,2,…m
wherein m is the number of circuit systems; u. of i (t) is the control input of the ith circuitry, k 1i Is a controller u i (t) a control gain; eta i (t l ) At time t for the ith circuitry l The error state of (2);
if the interval [ t l ,t l+1 ) When DoS attacks are encountered, there is t l +T＜t l+1 ≤t l +h M (ii) a The controller is then:
u i (t)＝-σ 1 (t)k 1i η i (t l )-σ 2 (t)k 2i η i (t l ),i＝1,2,…m
wherein
σ 1 (t)、σ 2 The values of (t) are respectively the first key parameter sigma output by the intelligent logic processor 1 Second key parameter σ 2 Of a value of (c) determined 1i 、k 2i Is the control gain.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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