CN114994507A - Control circuit for controlling logic turnover rate through clock tree node switch - Google Patents
Control circuit for controlling logic turnover rate through clock tree node switch Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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Abstract
A control circuit for controlling logic slew rate through clock tree node switching, comprising: a clock tree including a root node and N leaf nodes coupled to the root node, where N ≧ 2; each leaf node comprises an input end and an output end, the input end of each leaf node is coupled with the following node, the output end of each leaf node is connected with a corresponding test endpoint of a chip to be tested, a switch unit is connected in series between the input end and the output end of each leaf node, and the switch unit is used for controlling the connection or disconnection between the corresponding leaf node and the corresponding test endpoint of the chip to be tested according to a test signal during testing. The control circuit can enable the lowest test voltage (Vmin) to meet the test requirement, and the test accuracy is improved.
Description
Technical Field
The application relates to the field of chip detection, in particular to a control circuit for controlling logic turnover rate through clock tree node switches.
Background
As the signal propagation Delay on the signal line of the logic circuit increases, a propagation-Delay fault (TDF, a Delay fault generated when a Transition Delay fault is switched to "1" or "0" in the logic circuit) occurs. The conversion delay fault test is a test of inputting a test vector having differently changed logic values to a chip to be tested or a target circuit to be tested to check whether a conversion delay fault has occurred in the chip to be tested or the target circuit to be tested.
However, in the conventional transition delay fault test, a capture flip ratio (capture flip ratio, which is a ratio of the number of registers capturing phase flips divided by the total number of registers designed in a circuit or a chip to be controlled) of a test vector may be much higher than a functional logic flip ratio (functional switching ratio), so that a voltage drop (IR-drop) of a local area of the chip or a target circuit to be tested is too large, and a minimum test voltage (Vmin) of the test vector is small and cannot meet a test requirement, thereby affecting test accuracy.
Disclosure of Invention
Some embodiments of the present application provide a control circuit for controlling a logic slew rate through a clock tree node switch, including:
a clock tree including a root node and N leaf nodes coupled to the root node, where N ≧ 2;
each leaf node comprises an input end and an output end, the input end of each leaf node is coupled with the following node, the output end of each leaf node is connected with a corresponding test endpoint of a chip to be tested, a switch unit is connected in series between the input end and the output end of each leaf node, and the switch unit is used for controlling the connection or disconnection between the corresponding leaf node and the corresponding test endpoint of the chip to be tested according to a test signal during testing.
In some embodiments, the process of the switch unit controlling the connection or disconnection between the corresponding leaf node and the corresponding test endpoint of the chip to be tested according to the test signal when the test is performed includes: when testing is carried out, the switch unit controls M (M is less than N) leaf nodes to be communicated with corresponding testing end points of the chip to be tested according to the testing signals, and controls the rest N-M leaf nodes to be disconnected with the corresponding testing end points of the chip to be tested.
In some embodiments, the clock tree is an H-tree clock tree comprising a heel node and 4 leaf nodes coupled to the root node, the 4 leaf nodes being equidistant from the heel node.
In some embodiments, a switch unit is connected in series between an input terminal and an output terminal of each of the 4 leaf nodes.
In some embodiments, the clock tree is a hierarchical clock tree, the hierarchical clock tree includes a root node and a plurality of leaf nodes coupled to the follower node, the plurality of leaf nodes includes at least two first-level leaf nodes coupled to the follower node, at least two second-level leaf nodes coupled to each of the first-level leaf nodes, and outputs of the second-level leaf nodes are connected to corresponding test endpoints of chips to be tested.
In some embodiments, the switching unit includes a first switching unit and a second switching unit, the first switching unit is connected in series between an input terminal and an output terminal of each of the first-stage leaf nodes, the second switching unit is connected in series between an input terminal and an output terminal of each of the second-stage leaf nodes, the first switch unit is used for controlling connection and disconnection between the first-stage leaf node and the second-stage leaf node according to the test signal when testing, the second switch unit is used for controlling the connection or disconnection between the second-stage leaf node and the corresponding test endpoint of the chip to be tested according to the test signal during testing, the switch unit controls the connection or disconnection between the corresponding leaf node and the corresponding test endpoint of the chip to be tested through the common control of the first switch unit and the second switch unit during testing.
In some embodiments, the test device further comprises a test signal generating unit, coupled to the switching unit, for generating a test signal when performing a test.
In some embodiments, the test signals include at least a test enable signal itest _ en, a scan enable signal scan _ en, a scan data signal scan _ in, and a scan clock signal scan _ clk.
In some embodiments, the number of the switch units is the same as the number of the leaf nodes, one switch unit is connected in series between the input terminal and the output terminal of each leaf node, each switch unit comprises a scan register, an and gate, an or gate, an inverter, a first buffer, a second buffer and an integrated clock gate, the scan register comprises a D terminal, a Q terminal, an SD terminal, an SE terminal and a CLK terminal, the and gate comprises a first input terminal, a second input terminal and an output terminal, the or gate comprises a first input terminal, a second input terminal and an output terminal, the inverter comprises an input terminal and an output terminal, the first buffer and the second buffer each comprise an input terminal and an output terminal, the integrated clock gate comprises a TE terminal, an E terminal, a Q terminal and a CLK terminal, the D terminal of the scan register is connected with the Q terminal of the scan register, the SD terminal of the scan register is connected with the scan data signal scan _ in, the SE end of the scan register is connected with the scan enable signal scan _ en, the CLK end of the scan register is connected with the scan clock signal scan _ CLK, the D end of the scan register is also connected with the first input end of the AND gate, the second output end of the AND gate is connected with the test enable signal itest _ en, the output end of the AND gate is connected with the first input end of the OR gate, the second input end of the OR gate is connected with the scan enable signal scan _ en, the output end of the OR gate is connected with the input end of the first buffer, the output end of the first buffer is connected with the TE end of the integrated clock gate, the input end of the inverter is connected with the test enable signal itest _ en, the output end of the inverter is connected with the input end of the second buffer, and the output end of the second buffer is connected with the E end of the integrated clock gate, the CLK terminal of the integrated clock gate is connected to the input terminal of a corresponding one of the leaf nodes, and the Q terminal of the integrated clock gate is used as the output terminal of a corresponding one of the leaf nodes.
In some embodiments, one of the switch units includes a scan register, an and gate, an or gate, an inverter, a first buffer, a second buffer, a first integrated clock gate, a second integrated clock gate … …, an L (L ═ N) integrated clock gate, the scan register includes a D terminal, a Q terminal, an SD terminal, an SE terminal, and a CLK terminal, the and gate includes a first input terminal, a second input terminal, and an output terminal, the or gate includes a first input terminal, a second input terminal, and an output terminal, the inverter includes an input terminal and an output terminal, the first buffer and the second buffer each include an input terminal and an output terminal, the first integrated clock gate, the second integrated clock gate … …, the L (L ═ N) integrated clock gate each includes a TE terminal, an E terminal, a Q terminal, and a CLK terminal, the D terminal of the scan register is connected to the Q terminal of the scan register, the SD end of the scan register is connected with the scan data signal scan _ in, the SE end of the scan register is connected with the scan enable signal scan _ en, the CLK end of the scan register is connected with the scan clock signal scan _ CLK, the D end of the scan register is also connected with the first input end of the AND gate, the second output end of the AND gate is connected with the test enable signal itest _ en, the output end of the AND gate is connected with the first input end of the OR gate, the second input end of the OR gate is connected with the scan enable signal scan _ en, the output end of the OR gate is connected with the input end of the first buffer, the output end of the first buffer is connected with the TE ends of the first integrated clock gate and the second integrated clock gate … …, the L (L is N) integrated clock gate, and the input end of the inverter is connected with the test enable signal itest _ en, an output end of the inverter is connected to an input end of the second buffer, an output end of the second buffer is connected to both ends E of the first integrated clock gate and the second integrated clock gate … …, a CLK end of the first integrated clock gate is connected to an input end of a first leaf node, a Q end of the first integrated clock gate is used as an output end of the first leaf node, a CLK end of the second integrated clock gate is connected to an input end of a second leaf node, a Q end of the second integrated clock gate is used as an output end of the second leaf node, … …, a CLK end of the L integrated clock gate is connected to an input end of an nth leaf node, and a Q end of the L integrated clock gate is used as an output end of the nth leaf node.
The control circuit for controlling logic slew rate through clock tree node switches in some of the foregoing embodiments of the present application includes:
a clock tree including a root node and N leaf nodes coupled to the root node, where N ≧ 2; each leaf node comprises an input end and an output end, the input end of each leaf node is coupled with the following node, the output end of each leaf node is connected with a corresponding test endpoint of a chip to be tested, a switch unit is connected in series between the input end and the output end of each leaf node, and the switch unit is used for controlling the connection or disconnection between the corresponding leaf node and the corresponding test endpoint of the chip to be tested according to a test signal during testing. Through the control circuit, on and off between all leaf nodes and corresponding test terminals of the chip to be tested can be simply and selectively controlled, so that the capture switching ratio (capture switching ratio) of the control circuit can be reduced and is smaller than or equal to the functional logic switching ratio (functional switching ratio), and therefore, the voltage drop (IR-drop) of the chip to be tested or a local area of a target circuit to be tested can be prevented from being overlarge, the lowest test voltage (Vmin) of a test vector output on a leaf node of the control circuit or the chip test voltage meets the test requirement, and the test accuracy is improved.
Drawings
FIG. 1 is a schematic diagram of a control circuit for controlling logic slew rate via clock tree node switching according to some embodiments of the present disclosure;
FIG. 2 is a schematic diagram of a control circuit for controlling logic slew rate via clock tree node switches according to another embodiment of the present application;
FIG. 3 is a schematic diagram of a switch unit according to some embodiments of the present disclosure;
FIG. 4 is a schematic diagram illustrating a control circuit for controlling logic slew rate via clock tree node switches in accordance with yet another embodiment of the present application;
fig. 5 is a schematic structural diagram of a switch unit in another embodiment of the present application.
Detailed Description
The following detailed description of embodiments of the present application refers to the accompanying drawings. In describing the embodiments of the present application in detail, the drawings are not necessarily to scale, and the drawings are merely exemplary and should not be construed as limiting the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Some embodiments of the present application provide a control circuit for controlling a logic slew rate through a clock tree node switch, referring to fig. 1, including:
a clock tree comprising a root node 201 and N leaf nodes 202 coupled to the root node 201, N ≧ 2;
each leaf node 202 includes an input end 21 and an output end 22, the input end 21 of each leaf node 202 is coupled to the heel node 201, the output end 22 of each leaf node 202 is connected to a corresponding test endpoint of the chip 301 to be tested, and a switch unit CU is connected in series between the input end 21 and the output end 22 of each leaf node 202, and the switch unit CU is used for controlling the connection or disconnection between the corresponding leaf node 202 and the corresponding test endpoint of the chip 302 to be tested according to a test signal during testing.
Specifically, the starting point of the clock tree is used as a Root node (Root pin), the Root node inputs an initial clock signal, the initial clock signal passes through a series of distributed nodes to reach the end point of the clock tree, and the end point is used as a Leaf node (Leaf pin). The N leaf nodes 202 are coupled to the root node 201, and specifically, an initial clock signal starts from the root node 201 and finally reaches the N leaf nodes 202 through N rows of drivers (buffers, inverters) inserted in a cascade.
The number N of leaf nodes 202 in the clock tree is at least 2, and may specifically be 2, 3, 4, 5, 6, 7, 8, 9, 10, or another suitable number.
When the conversion delay fault is tested, the output end 22 of each leaf node 202 is connected to a corresponding test end point of one chip 301 to be tested, and the test end points are partial registers inside the chip 301 to be tested.
A switch unit CU is connected in series between the input end 21 and the output end 22 of each leaf node 202, and the switch unit CU is used for controlling the connection or disconnection between the corresponding leaf node 202 and the corresponding test endpoint of the chip to be tested 302 according to the test signal during the test. In some embodiments, the process of the switch unit CU controlling the connection or disconnection between the corresponding leaf node 202 and the corresponding test endpoint of the chip under test 301 according to the test signal when performing the test includes: when testing, the switch unit CU controls, according to a test signal, M (M < N) leaf nodes 202 to communicate with corresponding test terminals of the chip to be tested 301, and controls remaining N-M leaf nodes 202 to disconnect from corresponding test terminals of the chip to be tested 301. In a specific embodiment, when the clock tree includes 4 leaf nodes 202 coupled to the node 201 and the root node 201, a switch unit CU is connected in series between the input terminal 21 and the output terminal 22 of each of the 4 leaf nodes 202, and communication between 2 leaf nodes 202 and corresponding test terminals of the chip 301 to be tested can be controlled by the control of the switch unit CU, and disconnection between the remaining 2 leaf nodes 202 and corresponding test terminals of the chip 301 to be tested can be controlled. Therefore, the control circuit for controlling the logic turn-over rate through the clock tree node switch according to the present application can simply and selectively control on and off between all leaf nodes 202 and corresponding test terminals of the chip 301 to be tested, so that the capture turn-over ratio (capture switching ratio) of the control circuit can be reduced to be less than or equal to the functional turn-over ratio (functional switching ratio), thereby preventing the voltage drop (IR-drop) of the chip to be tested or a local area of a target circuit to be tested from being too large, enabling the lowest test voltage (Vmin) of the test vector output on the leaf node 202 of the control circuit or the chip test voltage to meet the test requirement, and improving the test accuracy.
In some embodiments, with continued reference to FIG. 1, the clock tree is an H-tree clock tree that includes a heel node 201 and 4 leaf nodes 202 coupled to the root node 201, the 4 leaf nodes 202 being equidistant from the heel node 201. A switching unit CU is connected in series between the input terminal 21 and the output terminal 22 of each of the 4 leaf nodes 202.
In another embodiment, referring to fig. 2, the clock tree is a hierarchical clock tree, the hierarchical clock tree includes a root node 201 and a plurality of leaf nodes coupled to the root node 201, the plurality of leaf nodes includes at least two first-level leaf nodes 202-1 coupled to the root node 201, at least two second-level leaf nodes 202-2 coupled to each of the first-level leaf nodes 202-1, and the output terminals 22 of the second-level leaf nodes 202-2 are connected to corresponding testing terminals of the chip 301 to be tested. And the switch unit comprises a first switch unit CU1 and a second switch unit CU2, a first switch unit CU1 is connected in series between the input end 21 and the output end 22 of each first-stage leaf node 202-1, a second switch unit CU2 is connected in series between the input end 21 and the output end 22 of each second-stage leaf node 202-2, the first switch unit CU1 is used for controlling the connection and disconnection between the first-stage leaf node 202-1 and the second-stage leaf node 202-2 according to a test signal during testing, the second switch unit CU2 is used for controlling the connection and disconnection between the second-stage leaf node 202-2 and the corresponding test endpoint of the chip 301 to be tested according to the test signal during testing, namely, the switch units control the connection and disconnection between the corresponding leaf node and the corresponding test endpoint of the chip to be tested 301 during testing through the common control of the first switch unit CU1 and the second switch unit CU2 Connected or disconnected.
In some embodiments, the control circuit further comprises a test signal generating unit (not shown in the figure), which is coupled to the switching unit, for generating a test signal when performing the test. In an embodiment, the Test signal generating unit includes an Automatic Test Pattern Generation (ATPG) unit, and the control circuit of the present application performs a Test by using a Scan Chain (Scan Chain) method when performing a Test of a translation delay fault. In some embodiments, the test signals include at least a test enable signal itest _ en, a scan enable signal scan _ en, a scan data signal scan _ in, and a scan clock signal scan _ clk.
In some embodiments, referring to fig. 1 and fig. 3 in combination, referring to fig. 1, the number of the switching units CU is the same as the number of the leaf nodes 202, one switching unit CU is connected in series between the input terminal 21 and the output terminal 22 of each of the leaf nodes 202, and referring to fig. 3, each of the switching units CU includes a scan register 101, an and gate 102, an or gate 103, an inverter 105, a first buffer 104, a second buffer 106, and an integrated clock gate 107, the scan register 101 includes a D terminal, a Q terminal, an SD terminal, an SE terminal, and a CLK terminal, the and gate 102 includes a first input terminal, a second input terminal, and an output terminal, the or gate 103 includes a first input terminal, a second input terminal, and an output terminal, the inverter 105 includes an input terminal and an output terminal, the first buffer 104 and the second buffer 106 include an input terminal and an output terminal, and the integrated clock gate 107 includes a TE terminal, An E terminal, a Q terminal and a CLK terminal, the D terminal of the scan register 101 is connected to the Q terminal of the scan register 101, the SD terminal of the scan register 101 is connected to the scan data signal scan _ in, the SE terminal of the scan register 101 is connected to the scan enable signal scan _ en, the CLK terminal of the scan register 101 is connected to the scan clock signal scan _ CLK, the D terminal of the scan register 101 is further connected to the first input terminal of the and gate 102, the second output terminal of the and gate 101 is connected to the test enable signal itest _ en, the output terminal of the and gate 101 is connected to the first input terminal of the or gate 103, the second input terminal of the or gate 103 is connected to the scan enable signal scan _ en, the output terminal of the or gate 103 is connected to the input terminal of the first buffer 104, and the output terminal of the first buffer 104 is connected to the TE terminal of the integrated clock gate 107, the input terminal of the inverter 105 is connected to the test enable signal itest _ en, the output terminal of the inverter 105 is connected to the input terminal of the second buffer 106, the output terminal of the second buffer 106 is connected to the E terminal of the integrated clock gate 107, the CLK terminal of the integrated clock gate 107 is connected to the input terminal 21 of a corresponding one of the leaf nodes 202, and the Q terminal of the integrated clock gate 107 serves as the output terminal 22 of a corresponding one of the leaf nodes 202.
In the switching unit CU, the functional model of the integrated clock gating 107 is described as that the E-terminal signal is — the test enable signal lte _ en, which indicates that the E-terminal signal is inverted with respect to the test enable signal lte _ en, the TE-terminal signal is (Q-terminal output value of the scan register 101 & the test enable signal lte _ en) | the scan enable signal scan _ en, and indicates that the TE-terminal signal is obtained by summing the Q-terminal output value of the scan register 101 with the test enable signal lte _ en and then summing the sum with the scan enable signal scan _ en.
The test enable signal ltest _ en is generated by the test signal generation unit, and the value of the test enable signal ltest _ en may be "0" or "1" in different modes.
The scan enable signal scan _ en is generated by a test signal generation unit. The scan enable signal scan _ en may have a value of "0" or "1" in different modes.
When the scan register 101 works, scan chains (scan chains) need to be connected in series, a test signal generation unit (such as ATPG) specifically generates scan vectors (including a scan data signal scan _ in and a scan clock signal scan _ CLK) to be input to the SD terminal and the CLK terminal of the scan register 101, and an output value of the Q terminal of the scan register 101 is controlled by the scan data signal scan _ in and the scan clock signal scan _ CLK.
In one embodiment, when the control circuit is in operation, when the test signal generating unit (e.g. ATPG) controls the output value of the Q terminal of the scan register 101 to be 0, and the scan enable signal scan _ en is 0, and the test enable signal lte _ en is 1, the signal values of the inputs of the TE terminal and the E terminal of the integrated clock gate 107 are both 0, and the integrated clock gate 107 is in a closed state, so that the clock signal at the leaf node input terminal 21 cannot be output from the output terminal 22, that is, the Q terminal of the integrated clock gate 107 or the output terminal 22 of the leaf node has no clock signal output, and the state of the corresponding test terminal (e.g. driven register) of the chip to be tested connected to the output terminal 22 of the leaf node is not converted;
when the test signal generation unit (e.g., ATPG) controls the Q terminal output value of the scan register 101 to be 1, and at the same time, the scan enable signal scan _ en is 0, and the test enable signal lte _ en is 1, the signal values input to the TE terminal and the E terminal of the integrated clock gate 107 are both 1, the integrated clock gate 107 is in an open state, so that the clock signal at the leaf node input terminal 21 can be output from the output terminal 22, and the clock signal output from the output terminal is applied to the corresponding test endpoint of the chip to be tested, so that the state of the corresponding test endpoint (e.g., driven register) of the chip to be tested connected to the output terminal 22 of the leaf node is converted.
With continued reference to fig. 1 and fig. 3, the clock circuit has 4 leaf nodes 202, the output terminals 22 of the 4 leaf nodes 202 are respectively connected to four test terminals of the chip 301 to be tested, and the four test terminals of the chip 301 to be tested respectively and equivalently have different numbers of registers, that is, when the test of the conversion delay fault is performed, the output terminals 22 of the 4 leaf nodes 202 need to respectively load the registers with different numbers, for example, the numbers of the registers where the output terminals of the 4 leaf nodes 202 need to be loaded are 100K, 200K, 150K, and 150K, respectively. The total load number at the following node of the control circuit is 600K.
Assuming that the conventional function switching ratio (functional switching ratio) is 10%, the capture switching ratio (capture switching ratio) of the output test vector is 15%. Therefore, the capture switching ratio (capture switching ratio) is larger than the functional switching ratio (functional switching ratio), so that the lowest test voltage (Vmin) of the test vector is smaller and cannot meet the test requirement.
In the present application, assuming that the functional switching ratio (functional switching ratio) is 10%, the capture switching ratio (capture switching ratio) of the output 22 of each leaf node 202 (for example, the aforementioned 4 leaf nodes 202) is also 15%, but due to the existence of the switching unit CU in the present application, when the test of the conversion delay fault is performed, the leaf node 202 is connected to the corresponding test terminal of the chip to be tested 301 through the switching unit CU control part, and the remaining leaf nodes 202 are disconnected from the corresponding test terminals of the chip to be tested 301, for example, the switching unit CU controls the connection between 2 leaf nodes 202 (for example, two leaf nodes of 100K and 200K respectively) of the 4 leaf nodes and the corresponding test terminals of the chip to be tested 301, and controls the remaining 2 leaf nodes 202 (for example, 150K respectively, two leaf nodes of 150K) and the corresponding test terminals of the chip to be tested 301, the capture switching ratio (capture switching ratio) of the 2 leaf nodes 202 connected to the corresponding test terminals of the chip to be tested 301 is: (100K 15% +200K 15%)/600K 7.5%. For another example, if the switch unit CU controls the most loaded leaf node (e.g., the leaf node loaded with 200K) of the 4 leaf nodes 202 to communicate with the corresponding test endpoint of the chip to be tested 301, and controls the remaining 3 leaf nodes 202 (e.g., the three leaf nodes loaded with 100K, 150K, and 150K, respectively) to disconnect from the corresponding test endpoint of the chip to be tested 301, the capture switching ratio (capture switching ratio) of the most loaded leaf node communicating with the corresponding test endpoint of the chip to be tested is: (200K 15%)/600K 5%. That is, by the control circuit for controlling the logic turning rate by the clock tree node switch according to the present application, on and off between all leaf nodes 202 and corresponding test terminals of the chip 301 to be tested can be easily and selectively controlled, so that the capture turning ratio (capture turning ratio) of the control circuit can be reduced and made smaller than or equal to the functional turning ratio (functional turning ratio), thereby preventing the voltage drop (IR-drop) of the chip to be tested or the local area of the target circuit to be tested from being too large, making the lowest test voltage (Vmin) of the test vector output on the leaf node 202 of the control circuit meet the test requirement, and improving the test accuracy.
In other embodiments, referring to fig. 4 and fig. 5, the number of the switch units CU is one, and specifically, the N leaf nodes are coupled to the following node 201 (for example, N is equal to 4, that is, 4 leaf nodes are coupled to the root node 201, the 4 leaf nodes include a first leaf node 202a, a second leaf node 202b, a third leaf node 202c and a fourth leaf node 202d as shown in fig. 4), a switch unit is connected in series between an input end and an output end of the leaf nodes, and one of the switch units CU includes the scan register 101, the and gate 102, the or gate 103, the inverter 105, the first buffer 104, the second buffer 106, and the first integrated clock gate 107a, the second integrated clock gate 107b … …, and the L (L ═ N) integrated clock gate (for example, L is equal to 4, that is, that includes four integrated clock gates, that is, respectively, the first integrated clock gate 107a, the second integrated clock gate 107b, the first integrated clock gate 107b, and the fourth integrated clock gate 107b, Third and fourth integrated clock gates 107c and 107D), the scan register including D, Q, SD, SE and CLK terminals, the scan register 101 including D, Q, SD, SE and CLK terminals, the and gate 102 including first, second and output terminals, the or gate 103 including first, second and output terminals, the inverter 105 including input and output terminals, the first and second buffers 104 and 106 including input and output terminals, the first and second integrated clock gates 107a and 107b … …, the L (L ═ N) integrated clock gates including TE, E, Q and CLK terminals, the D terminal of the scan register 101 being connected to the Q terminal of the scan register 101, the SD terminal of the scan register 101 being connected to the scan data signal scan _ in, the SE end of the scan register 101 is connected to the scan enable signal scan _ en, the CLK end of the scan register 101 is connected to the scan clock signal scan _ CLK, the D end of the scan register 101 is further connected to the first input end of the and gate 102, the second output end of the and gate 101 is connected to the test enable signal itest _ en, the output end of the and gate 101 is connected to the first input end of the or gate 103, the second input end of the or gate 103 is connected to the scan enable signal scan _ en, the output end of the or gate 103 is connected to the input end of the first buffer 104, the output end of the first buffer 104 is connected to both the TE ends of the first integrated clock gate 107a and the second integrated clock gate 107b … …, the L (L ═ N) integrated clock gate, the input end of the inverter 105 is connected to the test enable signal itest _ en, an output of the inverter 105 is connected to an input of the second buffer 106, an output of the second buffer 106 is connected to E-terminals of the first and second integrated clock gates 107a, 107b … …, the CLK terminal of the first integrated clock gate 107a is connected to the input terminals 202a-21 of the first leaf node 202a, the Q terminal of the first integrated clock gate 107a is used as the output terminals 202a-22 of the first leaf node 202a, the CLK terminal of the second integrated clock gate 107b is connected to the input terminals 202b-21 of the second leaf node 202b, the Q terminal of the second integrated clock gate 107b is used as the output terminals 202b-22, … … of the second leaf node 202b, the CLK terminal of the L integrated clock gate is connected to the input terminal of the nth leaf node, the Q terminal of the L-th integrated clock gate is used as the output terminal of the N-th leaf node (for example, when four integrated clock gates are included, the CLK terminal of the third integrated clock gate 107c is connected to the input terminals 202c-21 of the third leaf node 202c, the Q terminal of the third integrated clock gate 107c is used as the output terminals 202c-22 of the third leaf node 202c, the CLK terminal of the fourth integrated clock gate 107d is connected to the input terminals 202d-21 of the fourth leaf node 202d, and the Q terminal of the fourth integrated clock gate 107d is used as the output terminals 202d-22 of the fourth leaf node 202 d).
Although the present application has been described with reference to the preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible variations and modifications of the present application using the methods and technical content disclosed above without departing from the spirit and scope of the present application, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application shall fall within the scope of the present application.
Claims (10)
1. A control circuit for controlling logic slew rate through clock tree node switching, comprising: a clock tree comprising a root node and N leaf nodes coupled to the root node, wherein N is greater than or equal to 2;
each leaf node comprises an input end and an output end, the input end of each leaf node is coupled with the following node, the output end of each leaf node is connected with a corresponding test endpoint of a chip to be tested, a switch unit is connected in series between the input end and the output end of each leaf node, and the switch unit is used for controlling the connection or disconnection between the corresponding leaf node and the corresponding test endpoint of the chip to be tested according to a test signal during testing.
2. The control circuit for controlling logic slew rate through clock tree node switching as claimed in claim 1, wherein the process of the switching unit for controlling the connection or disconnection between the corresponding leaf node and the corresponding test terminal of the chip to be tested according to the test signal when performing the test comprises: when testing, the switch unit controls M (M is less than N) leaf nodes to be communicated with corresponding testing end points of the chip to be tested according to the testing signals, and controls the rest N-M leaf nodes to be disconnected with the corresponding testing end points of the chip to be tested.
3. The control circuit for controlling logic slew rate through clock tree node switching according to claim 1, wherein said clock tree is an H-tree clock tree comprising a heel node and 4 leaf nodes coupled to said root node, said 4 leaf nodes being equidistant from said heel node.
4. The control circuit for controlling logic slew rate through clock tree node switching according to claim 3, wherein a switching unit is connected in series between an input terminal and an output terminal of each of the 4 leaf nodes.
5. The control circuit of claim 1 wherein the clock tree is a hierarchical clock tree, the hierarchical clock tree including a root node and a plurality of leaf nodes coupled to the follower node, the plurality of leaf nodes including at least two first-level leaf nodes coupled to the follower node, at least two second-level leaf nodes coupled to each of the first-level leaf nodes, the second-level leaf nodes having outputs connected to respective test terminals of a chip to be tested.
6. The circuit of claim 5, wherein the switch unit comprises a first switch unit and a second switch unit, a first switch unit is connected in series between an input end and an output end of each first-stage leaf node, a second switch unit is connected in series between an input end and an output end of each second-stage leaf node, the first switch unit is used for controlling connection and disconnection between the first-stage leaf node and the second-stage leaf node according to a test signal during testing, the second switch unit is used for controlling connection and disconnection between the second-stage leaf node and a corresponding test endpoint of the chip to be tested according to the test signal during testing, and the switch unit controls connection or disconnection between the corresponding leaf node and the corresponding test endpoint of the chip to be tested during testing through common control of the first switch unit and the second switch unit And opening.
7. The control circuit for controlling logic slew rate through clock tree node switches of claim 1, further comprising a test signal generation unit coupled to the switch unit for generating a test signal when performing a test.
8. The control circuit for controlling a logic slew rate through a clock tree node switch of claim 8, wherein the test signals comprise at least a test enable signal ltest _ en, a scan enable signal scan _ en, a scan data signal scan _ in, and a scan clock signal scan _ clk.
9. The control circuit of claim 7, wherein the number of the switch units is the same as the number of leaf nodes, one switch unit is connected in series between the input and output terminals of each leaf node, each switch unit comprises a scan register, an AND gate, an OR gate, an inverter, a first buffer, a second buffer, and an integrated clock gate, the scan register comprises a D terminal, a Q terminal, an SD terminal, an SE terminal, and a CLK terminal, the AND gate comprises a first input terminal, a second input terminal, and an output terminal, the OR gate comprises a first input terminal, a second input terminal, and an output terminal, the inverter comprises an input terminal and an output terminal, the first buffer and the second buffer each comprise an input terminal and an output terminal, the integrated clock gate comprises a TE terminal, an E terminal, a Q terminal, and a CLK terminal, the D end of the scan register is connected with the Q end of the scan register, the SD end of the scan register is connected with the scan data signal scan _ in, the SE end of the scan register is connected with the scan enable signal scan _ en, the CLK end of the scan register is connected with the scan clock signal scan _ CLK, the D end of the scan register is further connected with the first input end of the AND gate, the second output end of the AND gate is connected with the test enable signal itest _ en, the output end of the AND gate is connected with the first input end of the OR gate, the second input end of the OR gate is connected with the scan enable signal scan _ en, the output end of the OR gate is connected with the input end of the first buffer, the output end of the first buffer is connected with the TE end of the integrated clock gate, and the input end of the phase inverter is connected with the test enable signal itest _ en, the output end of the phase inverter is connected with the input end of the second buffer, the output end of the second buffer is connected with the E end of the integrated clock gate, the CLK end of the integrated clock gate is connected with the input end of a corresponding leaf node, and the Q end of the integrated clock gate is used as the output end of a corresponding leaf node.
10. The control circuit of claim 7 wherein the number of switch cells is one, one of the switch cells comprises a scan register comprising a D terminal, a Q terminal, a SD terminal, a SE terminal, and a CLK terminal, an AND gate comprising a first input terminal, a second input terminal, and an output terminal, a first buffer, a second buffer, and a first integrated clock gate, a second integrated clock gate … … a L (L-N) integrated clock gate, the scan register comprising a D terminal, a Q terminal, a SD terminal, a SE terminal, and a CLK terminal, the AND gate comprising a first input terminal, a second input terminal, and an output terminal, the OR gate comprising a first input terminal, a second input terminal, and an output terminal, the inverter comprising an input terminal and an output terminal, the first integrated clock gate, the second integrated clock gate … … an L (L-N) integrated clock gate comprising a TE terminal, a first gate, a second integrated clock gate, and a second integrated clock gate, The D end of the scanning register is connected with the Q end of the scanning register, the SD end of the scanning register is connected with the scanning data signal scan _ in, the SE end of the scanning register is connected with the scanning enabling signal scan _ en, the CLK end of the scanning register is connected with the scanning clock signal scan _ CLK, the D end of the scanning register is further connected with the first input end of the AND gate, the second output end of the AND gate is connected with the testing enabling signal test _ en, the output end of the AND gate is connected with the first input end of the OR gate, the second input end of the OR gate is connected with the scanning enabling signal scan _ en, the output end of the OR gate is connected with the input end of the first buffer, and the output end of the first buffer is connected with the TE ends of the first integrated clock gate and the second integrated clock gate … …, the L (L is N) integrated clock gate, an input terminal of the inverter is connected to the test enable signal itest _ en, an output terminal of the inverter is connected to an input terminal of the second buffer, the output end of the second buffer is connected with the E ends of the first integrated clock gate and the second integrated clock gate … …, the L (L is N) th integrated clock gate, the CLK terminal of the first integrated clock gate is coupled to an input of a first leaf node, the Q terminal of the first integrated clock gate is an output of the first leaf node, the CLK terminal of the second integrated clock gate is connected to the input of a second leaf node, and the Q terminal of the second integrated clock gate is used as the output of the second leaf node, … …, the CLK end of the L-th integrated clock gate is connected with the input end of an N-th leaf node, and the Q end of the L-th integrated clock gate is used as the output end of the N-th leaf node.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210607454.XA CN114994507A (en) | 2022-05-31 | 2022-05-31 | Control circuit for controlling logic turnover rate through clock tree node switch |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210607454.XA CN114994507A (en) | 2022-05-31 | 2022-05-31 | Control circuit for controlling logic turnover rate through clock tree node switch |
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| CN114994507A true CN114994507A (en) | 2022-09-02 |
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