CN114978997A - Radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection algorithm - Google Patents
Radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection algorithm Download PDFInfo
- Publication number
- CN114978997A CN114978997A CN202210894342.7A CN202210894342A CN114978997A CN 114978997 A CN114978997 A CN 114978997A CN 202210894342 A CN202210894342 A CN 202210894342A CN 114978997 A CN114978997 A CN 114978997A
- Authority
- CN
- China
- Prior art keywords
- routing
- matrix
- stage
- memory table
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1515—Non-blocking multistage, e.g. Clos
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection algorithm, which comprises the following steps: s1 establishing a routing table; s2 creating a memory table; s3: selecting response port number groups in the routing table according to the output port number; s4 searching in the grouped memory list, if the searching is successful, jumping to S6, if the searching is failed, proceeding to S5; s5, determining the search query direction according to the current routing state; s6, controlling the on-off of each switch according to the inquired routing control parameters; s7 updates the memory table. The invention establishes a routing state table and a short-time memory table, uses the current connection state as prior knowledge, adopts a memory search and update method to realize the quick selection of the routing, reduces the average calculation amount of table lookup search to 1/2N, consumes little calculation amount and realizes the quick selection of the switching matrix routing.
Description
Technical Field
The invention relates to the technical field of data communication, in particular to a rapid routing selection algorithm for a radio frequency intermediate frequency three-level CLOS non-blocking switching matrix.
Background
In satellite earth stations, short-wave and ultrashort-wave communication hubs, radio signal detection stations and radio monitoring stations with larger scale, in order to realize large-scale communication link distribution management and signal detection and control link distribution management, a radio frequency intermediate frequency switching matrix is widely applied to complete distribution and exchange among a transmitting-receiving antenna, a communication terminal, a detection post and a monitoring station, and a routing algorithm is an important basis for developing high-efficiency communication link distribution management and signal receiving link distribution management. Because the radio frequency intermediate frequency switching matrix is used for power distribution and switching of high frequency analog signals, each level of distribution and switching brings insertion loss, low noise amplifiers are needed to be adopted for compensation, and in order to reduce electromagnetic radiation and interference of a calculation control unit to an analog high frequency channel, a simple operation and control device is usually adopted in engineering to complete route selection control except for electromagnetic shielding measures.
In the fields of radio communication, radio detection and radio monitoring, two methods are generally adopted for a routing algorithm of a radio frequency intermediate frequency switching matrix in engineering implementation: firstly, a sequential search algorithm is used for establishing a routing table in all states and obtaining the on-off states of all switches through sequential search; secondly, various parallel routing algorithms proposed by using Graph Edge Coloring (Graph Edge-Coloring) problem in Graph theory are usually used, and an n-Degree binary multiple Graph Edge Coloring algorithm (Edge Coloring of binary multiple of Degree n) is usually used. The sequential search algorithm method is simple, but has large calculation amount and high cost, and a control computer or a routing resolving function is usually required to be added in upper computer software in engineering realization; and the quantity of control information between the radio frequency intermediate frequency switching matrix and the control computer or the upper computer is large, the transmission timeliness of control instructions is low, and the route switching speed is low. The parallel routing algorithm reduces the operation amount, but the algorithm is still more complex and has higher cost, and a single board computer or a DSP board or an FPGA board with an ARM core needs to be integrated in a switching matrix; and a special electromagnetic shielding design is needed, so that the electromagnetic compatibility interference caused by high-speed digital signal processing of a single-board computer or a DSP board or an FPGA board with an ARM core is reduced.
Is currently largerIn satellite earth station, short wave and ultrashort wave communication hub, radio signal detecting station and radio monitoring station, according to the change of service, target and object the route of radio frequency intermediate frequency exchange matrix equipment can be dynamically controlled so as to quickly establish proper communication receiving-transmitting channel and signal detecting-controlling channel
However, for the rf intermediate frequency three-stage CLOS non-blocking switching matrix, it is still more complicated to use a low-cost single chip to solve the routing algorithm.
Disclosure of Invention
Aiming at the problems, the invention provides a low-cost and rapid method for realizing the routing of the radio frequency intermediate frequency non-blocking switching matrix by utilizing the routing priori knowledge and the memory search table look-up, the short-time memory is simulated, firstly, the memory list is inquired, the table look-up search calculation amount is averagely reduced to 1/2N, and the single chip microcomputer is used for completing the routing selection and control.
The invention adopts the following technical scheme: a radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection algorithm comprises the following steps:
s1: establishing a routing table: the routing tables are grouped according to the output port numbers, the input port numbers in the group are arranged from small to large, the routing tables define control parameters of the module switch required to be configured in the input stage S1, the intermediate stage S2 and the output stage S3, the control parameters of the routing tables are arranged according to a matrix, and a routing table control parameter matrix of a C (n, m, r) non-blocking switching matrix is as follows:
wherein
For output port j, the routing list for all input ports is as follows:
wherein
When the output port is the output port of the number j and is connected to the input port of the number i, the control parameters of the input stage, the intermediate stage and the output stage are as follows:
wherein
Wherein
Respectively representing control parameters of an input stage number a sub-matrix, control parameters of a middle stage number b sub-matrix and control parameters of an output stage number c sub-matrix;
s2: establishing a memory table:
the depth of the memory table is selected to be 2 or 4 or 8 or 16, the depth of the memory table is selected to be 2 bit depth at the shallowest, the depth of the memory table is selected to be 16 bit depth at the deepest, the memory table is configured according to the scale of the switching matrix, the scale is less than 32 x 32, the scale is selected to be 2, 32 x 32 to 64 x 64, the scale is selected to be 4, 64 x 64 to 128 x 128, the scale is selected to be 8, the scale is greater than 128 x 128, and the depth of the memory table is selected to be 16;
s3: selecting a response port number packet in the routing table according to the output port number j
；
S4: in a packet
Memory watch
Searching, if the searching is successful, jumping to the step S6, and if the searching is failed, performing the step S5;
s5: according to the current routing state, if the new input port number i is smaller than the input port number h of the current routing state, the search query direction is developed upwards, and if the new input port number i is larger than the input port number h of the current routing state, the search query direction is developed downwards;
s6: according to the inquired routing control parameter
Respectively controlling the on-off of each switch in the input stage matrix a, the intermediate stage matrix b and the output stage matrix c;
s7: and updating the memory table, adopting a first-in first-out mode, arranging the routing state used last time at the first position, arranging the routing state used last time at the second position, and so on, forgetting the routing state of the deepest position, and exiting the memory table.
The routing selection and control are completed by a simple low-cost singlechip.
The invention has the beneficial effects that: establishing a routing state table and a short-time memory table, using the current connection state as prior knowledge, adopting a memory search and update method to realize the quick selection of the routing, reducing the average calculation amount of table search to 1/2N, spending little calculation amount and realizing the quick selection of the switching matrix routing.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description only relate to some embodiments of the present invention and are not limiting on the present invention.
FIG. 1 is a logic diagram of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of the word "comprising" or "comprises", and the like, in this disclosure is intended to mean that the elements or items listed before that word, include the elements or items listed after that word, and their equivalents, without excluding other elements or items. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The invention is further illustrated with reference to the following figures and examples.
A radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection algorithm comprises the following steps:
s1: establishing a routing table: the routing tables are grouped according to the output port numbers, the input port numbers in the groups are arranged from small to large, the routing tables define control parameters of the module switches which need to be configured in the input stage S1, the intermediate stage S2 and the output stage S3, the control parameters of the routing tables are arranged according to a matrix, and a routing table control parameter matrix of the C (n, m, r) non-blocking switching matrix is as follows:
wherein
For output port j, routing columns for all input portsTable, as follows:
wherein
When the output port is the output port of the j number and is connected to the input port of the i number, the control parameters of the input stage, the intermediate stage and the output stage are as follows:
wherein
Wherein
Respectively representing control parameters of an input stage number a sub-matrix, control parameters of a middle stage number b sub-matrix and control parameters of an output stage number c sub-matrix;
s2: establishing a memory table:
the depth of the memory table is selected to be 2 or 4 or 8 or 16, the depth of the memory table is selected to be 2 bit depth at the shallowest, the depth of the memory table is selected to be 16 bit depth at the deepest, the memory table is configured according to the scale of the switching matrix, the scale is less than 32 x 32, the scale is selected to be 2, 32 x 32 to 64 x 64, the scale is selected to be 4, 64 x 64 to 128 x 128, the scale is selected to be 8, the scale is greater than 128 x 128, and the depth of the memory table is selected to be 16;
s3: selecting a response port number packet in the routing table according to the output port number j
；
S4: in a packet
Memory watch
Searching, if the searching is successful, jumping to the step S6, and if the searching is failed, performing the step S5;
s5: according to the current routing state, if the new input port number i is smaller than the input port number h of the current routing state, the search query direction is developed upwards, and if the new input port number is larger than the input port number h of the current routing state, the search query direction is developed downwards;
s6: according to the inquired routing control parameter
Respectively controlling the on-off of each switch in the input stage matrix a, the intermediate stage matrix b and the output stage matrix c;
s7: and updating the memory table, adopting a first-in first-out mode, arranging the routing state used last time at the first position, arranging the routing state used last time at the second position, and so on, forgetting the routing state of the deepest position, and exiting the memory table.
The routing selection and control are completed by a simple low-cost singlechip.
The invention utilizes the state that the radio frequency intermediate frequency three-level CLOS non-blocking switching matrix is not completely disconnected in actual use to establish routing tables from all input ports to output ports, and the routing tables are divided into 2 levels, wherein the routing tables comprise 2 routes which are selected most recently for 2 times and are taken as a first-level routing table, and the rest routes are taken as a second-level routing table; when the route is changed, firstly, inquiring in the memory list, and simultaneously, automatically updating the memory list, if the inquiry is successful, obtaining the route configuration of the input stage, the intermediate stage and the output stage switching module; if the query fails, switching to a second-level routing table for searching, and utilizing the port number and the current routing state to perform branch query to finally obtain the routing configuration of the input-level switching module, the intermediate-level switching module and the output-level switching module; and transmitting the routing of the three modules to the corresponding modules to realize the routing of the radio frequency intermediate frequency three-stage CLOS non-blocking switching matrix, as shown in FIG. 1.
Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present invention.
Claims (2)
1. A radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection algorithm is characterized by comprising the following steps:
s1: establishing a routing table: the routing tables are grouped according to the output port numbers, the input port numbers in the groups are arranged from small to large, the routing tables define control parameters of the module switches which need to be configured in the input stage S1, the intermediate stage S2 and the output stage S3, the control parameters of the routing tables are arranged according to a matrix, and a routing table control parameter matrix of the C (n, m, r) non-blocking switching matrix is as follows:
wherein
For output port j, the routing list for all input ports is as follows:
wherein
When the output port is the output port of the j number and is connected to the input port of the i number, the control parameters of the input stage, the intermediate stage and the output stage are as follows:
wherein
Wherein
Respectively representing control parameters of an input stage number a sub-matrix, control parameters of a middle stage number b sub-matrix and control parameters of an output stage number c sub-matrix;
s2: establishing a memory table:
the depth of the memory table is selected to be 2 or 4 or 8 or 16, the shallowest is selected to be 2 bit depth, the deepest is selected to be 16 bit depth, the memory table is configured according to the scale of the switching matrix, the scale is less than 32 multiplied by 32, the scale of the memory table is selected to be 2, 32 multiplied by 32 to 64 multiplied by 64, the scale of the memory table is selected to be 4, 64 multiplied by 64 to 128 multiplied by 128, the scale of the memory table is selected to be 8, the scale of the memory table is greater than 128 multiplied by 128, and the depth of the memory table is selected to be 16;
s3: selecting a response port number packet in the routing table according to the output port number j
；
S4: in a packet
Memory watch
Searching, if the searching is successful, jumping to the step S6, and if the searching is failed, performing the step S5;
s5: according to the current routing state, if the new input port number i is smaller than the input port number h of the current routing state, the search query direction is developed upwards, and if the new input port number is larger than the input port number h of the current routing state, the search query direction is developed downwards;
s6: according to the inquired routing control parameter
Respectively controlling the on-off of each switch in the input stage matrix a, the intermediate stage matrix b and the output stage matrix c;
s7: and updating the memory table, adopting a first-in first-out mode, arranging the routing state used last time at the first position, arranging the routing state used last time at the second position, and so on, forgetting the routing state of the deepest position, and exiting the memory table.
2. The routing rapid selection algorithm of the radio frequency intermediate frequency three-stage CLOS non-blocking switching matrix as claimed in claim 1, wherein the routing selection and control are accomplished by a single chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210894342.7A CN114978997B (en) | 2022-07-28 | 2022-07-28 | Radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210894342.7A CN114978997B (en) | 2022-07-28 | 2022-07-28 | Radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114978997A true CN114978997A (en) | 2022-08-30 |
| CN114978997B CN114978997B (en) | 2022-10-21 |
Family
ID=82968550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210894342.7A Active CN114978997B (en) | 2022-07-28 | 2022-07-28 | Radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114978997B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101119503A (en) * | 2007-09-10 | 2008-02-06 | 华为技术有限公司 | Method for selecting routing in CLOS switch network and routing select device |
| CN101227394A (en) * | 2008-02-18 | 2008-07-23 | 中兴通讯股份有限公司 | High-capacity non-jam route matrix |
| CN101277547A (en) * | 2008-03-18 | 2008-10-01 | 天津光电通信技术有限公司 | Large-scale strict non-blockage light-crossing connection matrix structure and control method thereof |
| CN101309222A (en) * | 2008-06-19 | 2008-11-19 | 华为技术有限公司 | Method, apparatus and system for regulating network routing |
| CN101778044A (en) * | 2010-01-20 | 2010-07-14 | 中国人民解放军国防科学技术大学 | Switched network system structure with adjustable throughput rate |
| CN102185772A (en) * | 2011-05-05 | 2011-09-14 | 北京交通大学 | Method for routing data centre network system |
| CN102740177A (en) * | 2012-07-17 | 2012-10-17 | 上海汇珏网络通信设备有限公司 | Non-blocking expandable multistage photoswitch array and working method thereof |
| US20130322879A1 (en) * | 2012-05-30 | 2013-12-05 | Thinklogical, Llc | Matrix router and method of switching |
| US20140321324A1 (en) * | 2006-12-14 | 2014-10-30 | Maged E. Beshai | Petabits-per-second Packet Switch Employing Cyclically Interconnected Switch Units |
| CN204681483U (en) * | 2015-05-29 | 2015-09-30 | 成都爱科特科技发展有限公司 | A kind of L frequency range 128 × 64 matrix switch system |
| CN109510786A (en) * | 2019-01-22 | 2019-03-22 | 伍星霖 | A kind of route control method and switching equipment |
| CN112350962A (en) * | 2020-11-25 | 2021-02-09 | 中国电子科技集团公司第五十四研究所 | Plane full-switching matrix |
-
2022
- 2022-07-28 CN CN202210894342.7A patent/CN114978997B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140321324A1 (en) * | 2006-12-14 | 2014-10-30 | Maged E. Beshai | Petabits-per-second Packet Switch Employing Cyclically Interconnected Switch Units |
| CN101119503A (en) * | 2007-09-10 | 2008-02-06 | 华为技术有限公司 | Method for selecting routing in CLOS switch network and routing select device |
| CN101227394A (en) * | 2008-02-18 | 2008-07-23 | 中兴通讯股份有限公司 | High-capacity non-jam route matrix |
| CN101277547A (en) * | 2008-03-18 | 2008-10-01 | 天津光电通信技术有限公司 | Large-scale strict non-blockage light-crossing connection matrix structure and control method thereof |
| CN101309222A (en) * | 2008-06-19 | 2008-11-19 | 华为技术有限公司 | Method, apparatus and system for regulating network routing |
| CN101778044A (en) * | 2010-01-20 | 2010-07-14 | 中国人民解放军国防科学技术大学 | Switched network system structure with adjustable throughput rate |
| CN102185772A (en) * | 2011-05-05 | 2011-09-14 | 北京交通大学 | Method for routing data centre network system |
| US20130322879A1 (en) * | 2012-05-30 | 2013-12-05 | Thinklogical, Llc | Matrix router and method of switching |
| CN102740177A (en) * | 2012-07-17 | 2012-10-17 | 上海汇珏网络通信设备有限公司 | Non-blocking expandable multistage photoswitch array and working method thereof |
| CN204681483U (en) * | 2015-05-29 | 2015-09-30 | 成都爱科特科技发展有限公司 | A kind of L frequency range 128 × 64 matrix switch system |
| CN109510786A (en) * | 2019-01-22 | 2019-03-22 | 伍星霖 | A kind of route control method and switching equipment |
| CN112350962A (en) * | 2020-11-25 | 2021-02-09 | 中国电子科技集团公司第五十四研究所 | Plane full-switching matrix |
Non-Patent Citations (4)
| Title |
|---|
| W. KABACINSKI: "Non-blocking asymmetrical three-stage multirate switching networks", 《IEEE XPLORE》 * |
| 曾峰: "可重排非阻塞三级 Clos 网络控制算法", 《百度学术》 * |
| 韩周安: "基于CPCI结构变频器的电源设计", 《CNKI中国知网》 * |
| 黄勇: "硅基Ka波段全射频相控阵发射机研究与设计", 《CNKI中国知网》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114978997B (en) | 2022-10-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110495144B (en) | Network topology structure mapping method and device, terminal and storage medium | |
| CN106656099B (en) | Digital phase shifter | |
| JP2006270430A (en) | Mimo multiplex communication apparatus and signal separation method | |
| US7890103B2 (en) | Wireless base station and mobile station | |
| CN113315569A (en) | Satellite reliability routing method and system with weighted link survival time | |
| CN102281192B (en) | The cell processing method and processing device of exchange network chip | |
| RU2174286C1 (en) | Transmitter with switched time diversity for transmission to limit transmission power of antenna and process of control over it at base station of communication system with mobile objects | |
| CN114978997B (en) | Radio frequency intermediate frequency three-level CLOS non-blocking switching matrix route rapid selection method | |
| US4748660A (en) | Process for determination of the last intermediate node in a network of numerous interconnected nodes | |
| CN109510681B (en) | Reference node selection method with minimum time synchronization series of communication network | |
| CN109709851B (en) | High-speed generation device and method for complex modulation signal | |
| WO2021105728A1 (en) | Efficient parallelized computation of a benes network configuration | |
| CN100514888C (en) | Method and device for simulating radio channel | |
| CN107528132A (en) | Inductor-adjustable apparatus, electronic equipment and the adjustable method of inductance | |
| CN106656879B (en) | A kind of high-speed and High-order variable-step self-adaptive equalization methods | |
| CN112672300A (en) | Power consumption data vine type transmission optimization method for medium and low voltage switch cabinet | |
| CN103986670A (en) | Method for obtaining performance of optical switch chip | |
| CN109660473B (en) | Spherical decoding detection method and device and computer readable storage medium | |
| CN115379318A (en) | BENES network route speculative solution method and device | |
| CN101562468A (en) | Balancing device and balancing method based on iteration elimination and maximum ratio combining | |
| Chien et al. | High performance concentrators and superconcentrators using multiplexing schemes | |
| CN103516620A (en) | VM migration method, VM migration system and server | |
| US6657979B1 (en) | Reduced power consumption multiplexer using self-decoding power down logic | |
| CN101635938B (en) | Features window detecting device and method capable of working under rapid AGC mechanism | |
| CN113163433B (en) | Self-organizing quantum network protocol and routing scheduling method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |