CN114978346A - Digital signal linear equalization method and system, electronic equipment and storage medium - Google Patents
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Abstract
A digital signal linear equalization method, system, electronic device and storage medium, the method comprising: according to the adaptive equalization with tap delay of T/2, determining the total number L of taps of the equalizer reaching the threshold of the error rate; dividing N taps with the tap delay of T and M taps with the tap delay of T/2 from the L taps; the value of N, M is brought into the tap time delay self-adaptive adjusting equalizer, whether the error rate threshold can be reached is judged, if the error rate threshold is reached, the value of N, M is stored and substituted into the tap time delay self-adaptive adjusting equalizer, otherwise, the value of N is reduced and then the value is brought into the tap time delay self-adaptive adjusting equalizer to repeatedly carry out judgment under the condition that the total number L of taps of the equalizer is not changed; digital signal processing is performed using a tap delay adaptive adjustment equalizer substituted for the value N, M. The tap delay of the linear equalizer can be flexibly adjusted between T and T/2, and the power consumption and the delay of the system are reduced.
Description
Technical Field
The invention belongs to the technical field of digital signal processing, and particularly relates to a digital signal linear equalization method, a digital signal linear equalization system, electronic equipment and a storage medium.
Background
With the emergence of a plurality of novel internet applications such as internet of things and 5G mobile forward transmission, higher requirements are put forward on the bandwidth of a high-speed short-distance optical fiber communication system. The intensity modulation/direct detection (IM/DD) transmission scheme has become a preferred scheme for short-distance optical transmission systems due to its advantages of simple structure, small delay, and low power consumption. In order to improve the transmission capacity of an intensity modulation/direct detection (IM/DD) system, various high-order modulation schemes such as Pulse Amplitude Modulation (PAM), discrete multitone modulation (DMT), and carrierless amplitude-phase modulation (CAP) are widely used. Among them, quaternary pulse amplitude modulation (PAM4) is preferred due to its simple structure, low cost, and low power consumption, and IEEE 400GbE p802.3bs working group adopts quaternary pulse amplitude modulation (PAM4) as a modulation scheme for data center interconnection. Meanwhile, intensity modulation/direct detection (IM/DD) also faces many challenges under new bandwidth requirements, such as bandwidth limitation caused by low-cost transceivers, damage caused by nonlinear modulation characteristics, and influence of Chromatic Dispersion (CD) in fiber channels. Digital Signal Processing (DSP) in the electrical domain has been widely studied as a flexible compensation method for improving the performance of optical systems, and the overall algorithm flow of the DSP is shown in fig. 1.
In which, an adaptive equalization module is provided at the receiving end, and a forward equalizer (FFE) is usually used to effectively eliminate various impairments of the transceiver and channel, especially the effects of inter-symbol interference (ISI). In bandwidth limited intensity modulation/direct detection (IM/DD) systems, low cost components and dispersion effects can cause severe intersymbol interference. In this case, a large-tap-count forward equalizer (FFE) can be used as a compensation scheme, but it causes a significant increase in system cost and power consumption.
Disclosure of Invention
The present invention aims to solve the above problems in the prior art, and provide a digital signal linear equalization method, system, electronic device and storage medium, wherein the tap delay of the linear equalizer can be flexibly adjusted between T and T/2, and the calculation complexity of the algorithm can be significantly reduced while the system performance is ensured, so as to reduce the power consumption and delay of the system.
In order to achieve the purpose, the invention has the following technical scheme:
in a first aspect, a digital signal linearity equalizing method is provided, including:
according to the adaptive equalization with tap delay of T/2, determining the total number L of taps of the equalizer reaching the threshold of the error rate;
dividing N taps with the tap delay of T and M taps with the tap delay of T/2 from L taps;
the value of N, M is brought into the tap time delay self-adaptive adjusting equalizer, whether the error rate threshold can be reached is judged, if the error rate threshold is reached, the value of N, M is stored and substituted into the tap time delay self-adaptive adjusting equalizer, otherwise, the value of N is reduced and then the value is brought into the tap time delay self-adaptive adjusting equalizer to repeatedly carry out judgment under the condition that the total number L of taps of the equalizer is not changed;
digital signal processing is performed using a tap delay adaptive adjustment equalizer substituted for the value N, M.
Further, the step of bringing N, M into the tap delay adaptive equalizer has the following expression:
in the formula, z [ k ]]To output a signal, omega j As a weight coefficient, E r For an input signal, k is the sampling time, i is the number of taps with a tap delay of T, j is the number of taps with a delay, and N and M are the number of taps with a tap delay of T and T/2, respectively.
Preferably, the weight coefficients of the tap delay adaptive adjustment equalizer are adaptively updated by using a least mean square algorithm.
Furthermore, the input signal of the tap time delay adaptive adjustment equalizer is a digital signal with damage, and the output signal is a digital signal after linear equalization.
In a second aspect, a digital signal linearity equalizing system is provided, comprising:
the total tap number determining module is used for determining the total tap number L of the equalizer reaching the error rate threshold according to the adaptive equalization with the tap delay of T/2;
the tap dividing module is used for dividing N taps with the tap delay of T and M taps with the tap delay of T/2 from the L taps;
an N, M value screening module, which is used for bringing the value of N, M into the tap time delay self-adaptive adjusting equalizer, judging whether the error rate threshold can be reached, if the error rate threshold is reached, storing the value of N, M and substituting the value into the tap time delay self-adaptive adjusting equalizer, otherwise, reducing the value of N and then bringing the value into the tap time delay self-adaptive adjusting equalizer to repeatedly execute the judgment under the condition that the total number of taps of the equalizer is not changed;
and the equalizer processing module is used for carrying out digital signal processing by utilizing the tap delay adaptive adjustment equalizer substituted with N, M values.
Further, the expression of the tap delay adaptive adjustment equalizer of the equalizer processing module is as follows:
in the formula, z [ k ]]To output a signal, omega j As a weight coefficient, E r For an input signal, k is the sampling time, i is the number of taps with a tap delay of T, j is the number of taps with a delay, and N and M are the number of taps with a tap delay of T and T/2, respectively.
As a preferred scheme, the equalizer processing module adaptively updates the weight coefficients of the tap delay adaptive adjustment equalizer by using a least mean square algorithm.
Furthermore, the equalizer processing module provides the tap delay adaptive adjustment equalizer with an input signal of a damaged digital signal and an output signal of a linear equalized digital signal.
In a third aspect, an electronic device is provided, including:
a memory storing at least one instruction; and
a processor executing the instructions stored in the memory to implement the digital signal linear equalization method of the first aspect.
In a fourth aspect, a computer-readable storage medium is provided, which stores a computer program, which when executed by a processor implements the digital signal linear equalization method of the first aspect.
Compared with the prior art, the first aspect of the invention has at least the following beneficial effects:
in an optical fiber transmission system, due to the requirement of high-speed transmission, intersymbol interference often exists in a channel, and an FFE algorithm is often used for compensating the intersymbol interference in a high-speed short-distance optical fiber communication system by virtue of the characteristics of simple structure, easy realization and low algorithm complexity, and the more taps are, the better the equalization effect is. However, when intersymbol interference is severe, the use of a large number of taps FFE increases the complexity, power consumption, and delay of the system. The intersymbol interference is caused by the fact that the waveform of a code element is widened due to non-ideal channel transmission characteristics, and mutual interference occurs between front and rear code elements. The invention is a channel damage equalization scheme of forward equalizer of relatively low complexity, adjust flexibly between T and T/2 through changing the tap delay, in the traditional equalizer, through adjusting the time interval of the interpolation filter in the equalizer, realize the change of the tap delay of the equalizer, in the multi-tap equalizer that the system is seriously limited, on the fixed position, increase the time interval of the interpolation filter, adjust from half symbol cycle time to the time of a symbol cycle, therefore the invention can reduce the computational complexity of the algorithm apparently while guaranteeing the system performance.
It is understood that the beneficial effects of the second to fourth aspects can be seen from the description of the first aspect, and are not described herein again.
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In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a block flow diagram of an existing DSP algorithm as a whole;
FIG. 2 is a flow chart of a prior art FFE algorithm;
FIG. 3 is a schematic diagram of an internal structure of an equalizer of the digital signal linear equalization method according to the present invention;
FIG. 4 is a flow chart of a digital signal linear equalization method of the present invention;
fig. 5 is a graph showing the variation of the total operation times of the digital signal linear equalization method according to the present invention with the number of taps and the tap ratio.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Referring to fig. 4, a digital signal linearity equalizing method according to an embodiment of the present invention includes the following steps:
s1, determining the total number L of equalizer taps reaching the threshold of bit error rate according to the adaptive equalization with tap delay of T/2;
s2, dividing N taps with the tap delay of T and M taps with the tap delay of T/2 from the L taps;
s3, bringing the value of N, M into a tap time delay adaptive adjustment equalizer, and judging whether the error rate threshold can be reached: if the bit error rate threshold is reached, the stored N, M value is substituted into the tap time-delay self-adaptive adjustment equalizer, otherwise, the value of N is reduced and then substituted into the tap time-delay self-adaptive adjustment equalizer to repeatedly perform judgment under the condition that the total number L of taps of the equalizer is not changed;
and S4, carrying out digital signal processing by using the tap delay self-adaptive adjusting equalizer substituted into N, M value.
In an alternative of the digital signal linear equalization method of the present invention, in step S3, when the value of N, M is substituted into the tap delay adaptive equalizer, the expression of the tap delay adaptive equalizer is as follows:
in the formula, z [ k ]]To output a signal, omega j As a weight coefficient, E r For an input signal, k is the sampling time, i is the number of taps with a tap delay of T, j is the number of taps with a delay, and N and M are the number of taps with a tap delay of T and T/2, respectively. The tap delay adaptive equalizer weight coefficients are adaptively updated using a least mean square algorithm (LMS). The input signal of the tap time delay self-adaptive adjusting equalizer is a digital signal with damage, and the output signal is a digital signal after linear equalization.
Referring to fig. 3, in the optical fiber transmission system, due to the requirement of high-speed transmission, ISI often exists in a channel, and due to the simple structure, easy implementation, and low algorithm complexity, FFE is often used to compensate ISI in a high-speed short-distance optical fiber communication system, and the more taps are, the better the equalization effect is. However, when ISI is severe, the use of a large number of taps FFE will increase the complexity, power consumption, and delay of the system. ISI is caused by the spreading of the symbol waveform due to non-ideal channel transmission characteristics, resulting in mutual interference between preceding and following symbols. Based on the characteristic, the digital signal linear equalization method provided by the invention designs an equalizer structure with flexibly adjustable tap delay, effectively reduces the number of taps and reduces the complexity of a system.
When the IM/DD system suffers severe ISI, neglecting the non-linear impairments, the signal interfered by the postamble and postamble at the receiving end can be represented as follows:
in the formula, a n Representing the original signal, h (t-nT) s ) For system response, t is at sample timeN is a positive integer, T s N (t) is additive noise for symbol intervals;
after analog-to-digital conversion, the discrete sampled signal can be expressed as follows:
in the formula, a k h(t 0 ) Indicates the desired received symbol, a k For the current symbol, t 0 Is the sampling time;
representing the value of intersymbol interference, associated with the response of the channel and the device, a n Is other than the k-th symbol; n (kT) s +t 0 ) Representing additive gaussian noise;
therefore, the invention provides an H-FFE algorithm, and the expression based on the equalizer is obtained as follows:
in the formula, z [ k ]]To output a signal, omega j As a weight coefficient, E r For an input signal, k is the sampling time, i is the number of taps with a tap delay of T, j is the number of taps with a delay, and N and M are the number of taps with a tap delay of T and T/2, respectively.
The tap time delay of the H-FFE structure can be flexibly adjusted, and the tap coefficient is adaptively updated by using a least mean square algorithm (LMS).
As shown in fig. 2, FFE is an equalizer widely used for linear impairment compensation. The output of the FFE can be expressed as:
where z [ k ] is the equalizer output, N is the number of taps, w is the tap coefficient, and can be written as:
w＝[w 0 w 1 w 2 … w N-1 ]
E r [k]＝[E r (kT) E r ((k-1)T) … E r ((k-N+1)T)]
the taps of the equalizer may be adaptively updated according to different requirements.
Here, one of the most commonly used algorithms is DD-LMS. In the DD-LMS algorithm, the error function is defined as:
ε[k]represents z [ k ]]And decision symbols
The error between. The cost function is defined as:
the cost function is minimized by using an iterative algorithm with gradient descent.
If from the k-th 0 T symbols start, then the filter n +1 th The tap weight is:
where μ is the step size.
Notably, the FFE algorithm can operate at a 1 x sample rate or higher for the signal. If the FFE equalizer is operated at 1 times the sampling rate, matched filtering of the channel needs to be added before the FFE equalizer.
If the FFE works at a 2-fold sampling rate of the signal, the FFE algorithm can be carried out by itselfAnd (4) matched filtering. In this case, T is equal to T S And 2, the tap weight value is updated only at intervals of 2T, 4T, 6T and the like.
In contrast, DFE is another linear equalizer that compensates for channel impairments.
Unlike the FFE algorithm, the input to the DFE algorithm is a decision signal
The DFE algorithm is often used in the case of a signal that is 1 times sampled. In this case, the output of the DFE before signal decision can be expressed as:
if a DD-LMS based iterative procedure is used, the signal is at k 0 At time T, filter n +1 th The tap weight is:
w (n+1) ＝w (n) +με[k 0 +n]Z[k 0 +n]
wherein the content of the first and second substances,
Z[n]＝[z[n]z[n-1]…z[n-(N-1)]]
it is noted that the FFE algorithm is simple and has no decision feedback delay, but FFE has no effect when equalizing spectral nulls. The DFE algorithm can equalize the spectral nulls to some extent, but the DFE algorithm becomes unstable and is subject to bit error spreading. It is noteworthy that the damage introduced by CD has an effect on both the front and back symbols. In this case, the best alternative would be to use joint equalization of FFE and DFE.
The above equalizer designs all use twice sampling, which brings higher computational complexity and is not beneficial to DSP implementation.
For short-haul fiber optic systems, computational complexity is an important consideration in system design. Thus, the following analysis compares the computational complexity of the conventional FFE algorithm and the H-FFE algorithm of the present invention.
The number of Real Multiplication (RM) and Real Addition (RA) operations required per symbol is calculated.
The FFE algorithm belongs to a finite impulse response Filter (FIR), and for an FIR with tap delay of N orders of T, N real multiplication and N-1 real addition are required for each output of one symbol. When FFE with tap delay T based on LMS outputs one symbol, tap coefficient updating, error calculation and equalization are needed once, and therefore, N +1 times of multiplication and N times of addition are needed for each self-adaptive iteration. For an FIR with M tap delays of T/2, each symbol number needs to be sampled twice, so the computational complexity is twice that of an equalizer with a tap delay of T. FFE with a tap delay of T/2 based on LMS requires 2M +1 multiplications and 2M additions per adaptation iteration.
The calculation complexity of the H-FFE algorithm of the present invention with different tap numbers is shown in fig. 5, and the contour line represents the number of operations required for each symbol number, which varies with the total tap number and the ratio of the two taps (taps with delay T and T/2). The calculation result shows that along with the increase of the number of taps, the calculation complexity can be obviously reduced by increasing the tap proportion with the delay of T, and when the ISI in the system is serious, the H-FFE structure provided by the invention can effectively reduce the calculation complexity.
In summary, the invention provides a channel impairment equalization scheme for a forward equalizer with relatively low complexity, which can significantly reduce the computational complexity of the algorithm while ensuring the system performance by flexibly adjusting the tap delay between T and T/2.
Another embodiment of the present invention provides a digital signal linearity equalizing system, including:
the total tap number determining module is used for determining the total tap number L of the equalizer reaching the error rate threshold according to the adaptive equalization with the tap delay of T/2;
the tap dividing module is used for dividing N taps with the tap delay of T and M taps with the tap delay of T/2 from the L taps;
an N, M value screening module, which is used for bringing the value of N, M into the tap time delay self-adaptive adjusting equalizer, judging whether the error rate threshold can be reached, if the error rate threshold is reached, storing the value of N, M and substituting the value into the tap time delay self-adaptive adjusting equalizer, otherwise, reducing the value of N and then bringing the value into the tap time delay self-adaptive adjusting equalizer to repeatedly execute the judgment under the condition that the total number of taps of the equalizer is not changed;
and the equalizer processing module is used for carrying out digital signal processing by utilizing the tap delay adaptive adjustment equalizer substituted with N, M values.
Further, the expression of the tap delay adaptive adjustment equalizer of the equalizer processing module is as follows:
in the formula, z [ k ]]To output a signal, ω j As a weight coefficient, E r For an input signal, k is the sampling time, i is the number of taps with a tap delay of T, j is the number of taps with a delay, and N and M are the number of taps with a tap delay of T and T/2, respectively.
Furthermore, the equalizer processing module according to this embodiment adaptively updates the weight coefficients of the tap delay adaptive equalizer by using a least mean square algorithm.
Furthermore, the equalizer processing module provides the tap delay adaptive adjustment equalizer with an input signal of a damaged digital signal and an output signal of a linear equalized digital signal.
Another embodiment also provides an electronic device, including:
a memory storing at least one instruction; and
and the processor executes the instructions stored in the memory to realize the digital signal linear equalization method.
Another embodiment further proposes a computer-readable storage medium, in which a computer program is stored, which computer program, when being executed by a processor, implements the method for linear equalization of a digital signal.
The computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable storage medium may include: any entity or device capable of carrying said computer program code, media, usb disk, removable hard disk, magnetic diskette, optical disk, computer memory, read-only memory, random access memory, electrical carrier wave signals, telecommunication signals, software distribution media, etc. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice. For convenience of explanation, the above description only shows the relevant parts of the embodiments of the present invention, and the detailed technical details are not disclosed, please refer to the method parts of the embodiments of the present invention. The computer-readable storage medium is non-transitory, and may be stored in a storage device formed by various electronic devices, so as to implement the implementation process described in the method of the embodiment of the present invention.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (10)
1. A method of digital signal linear equalization, comprising:
according to the adaptive equalization with tap delay of T/2, determining the total number L of taps of the equalizer reaching the threshold of the error rate;
dividing N taps with the tap delay of T and M taps with the tap delay of T/2 from the L taps;
the value of N, M is brought into the tap time delay self-adaptive adjusting equalizer, whether the error rate threshold can be reached is judged, if the error rate threshold is reached, the value of N, M is stored and substituted into the tap time delay self-adaptive adjusting equalizer, otherwise, the value of N is reduced and then the value is brought into the tap time delay self-adaptive adjusting equalizer to repeatedly carry out judgment under the condition that the total number L of taps of the equalizer is not changed;
digital signal processing is performed using a tap delay adaptive adjustment equalizer substituted for the value N, M.
2. The method for linear equalization of a digital signal according to claim 1, wherein said step of introducing a value of N, M into the tap delay adaptive equalizer is expressed as follows:
in the formula, z [ k ]]To output a signal, ω j As a weight coefficient, E r For an input signal, k is the sampling time, i is the number of taps with a tap delay of T, j is the number of taps with a delay, and N and M are the number of taps with a tap delay of T and T/2, respectively.
3. The method for linear equalization of a digital signal according to claim 2, wherein the weight coefficients of the tap delay adaptive equalizer are adaptively updated using a least mean square algorithm.
4. The method for linearly equalizing digital signals according to claim 2, wherein the input signal of the tap delay adaptive equalizer is a digital signal with impairments, and the output signal is a digital signal after linear equalization.
5. A digital signal linear equalization system, comprising:
the total tap number determining module is used for determining the total tap number L of the equalizer reaching the error rate threshold according to the adaptive equalization with the tap delay of T/2;
the tap dividing module is used for dividing N taps with the tap delay of T and M taps with the tap delay of T/2 from L taps;
an N, M value screening module, which is used for bringing the value of N, M into the tap time delay self-adaptive adjusting equalizer, judging whether the error rate threshold can be reached, if the error rate threshold is reached, storing the value of N, M and substituting the value into the tap time delay self-adaptive adjusting equalizer, otherwise, reducing the value of N and then bringing the value into the tap time delay self-adaptive adjusting equalizer to repeatedly execute the judgment under the condition that the total number of taps of the equalizer is not changed;
and the equalizer processing module is used for carrying out digital signal processing by utilizing the tap delay adaptive adjustment equalizer substituted with N, M values.
6. The digital signal linear equalization system of claim 5, wherein the tap delay adaptive adjustment equalizer of the equalizer processing module is expressed as follows:
in the formula, z [ k ]]To output a signal, omega j As a weight coefficient, E r For an input signal, k is the sampling time, i is the number of taps with a tap delay of T, j is the number of taps with a delay, and N and M are the number of taps with a tap delay of T and T/2, respectively.
7. The system according to claim 6, wherein the equalizer processing module adaptively updates the weight coefficients of the tap delay adaptive equalizer using a least mean square algorithm.
8. The system for linear equalization of a digital signal according to claim 6, wherein the equalizer processing module provides the tap delay adaptive equalizer with an input signal of a damaged digital signal and an output signal of a linearly equalized digital signal.
9. An electronic device, comprising:
a memory storing at least one instruction; and
a processor executing instructions stored in the memory to implement the digital signal linear equalization method of any one of claims 1 to 4.
10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, implements the digital signal linear equalization method according to any one of claims 1 to 4.
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