CN114978159A - CDR control loop frequency correction method, device, loop and receiver - Google Patents

Abstract

The application relates to a CDR control loop frequency correction method, a device, a loop and a receiver, wherein the method comprises the following steps: after a receiver chip is powered on to work, control words prestored in a register are obtained; a PLL loop for adjusting the internal oscillator to output a target reference frequency to the CDR control loop using the control word; after the PLL loop is locked, sending the multi-path multi-phase clock output by the voltage-controlled oscillator into an FD/PD loop of the CDR control loop; after the FD/PD loop is stable, carrying out error code detection on data output by the serial-parallel converter; and if no error code is detected, finishing the frequency correction of the FD/PD loop. The ring oscillator in the chip is adopted to provide the reference clock, the defect that the FD/PD loop cannot be normally locked due to the frequency offset of the reference clock is overcome, the FD/PD loop can be quickly locked in the chip, and the purpose of efficient frequency deviation correction is achieved.

Description

CDR control loop frequency correction method, device, loop and receiver

Technical Field

The invention belongs to the technical field of interface circuits, and relates to a CDR control loop frequency correction method, a device, a loop and a receiver.

Background

The high-speed interface circuit comprises a transmitter part and a receiver part and is widely applied to various data transmission scenes. In the chip design of the receiver, the high-precision quartz crystal oscillator, the high-precision RC type oscillator and the LC-tank type oscillator commonly used in the industry generate the reference clock. In the receiver chip using the on-chip reference clock, the on-chip reference clock is greatly affected by environmental factors such as process, voltage, temperature, and the like, and usually has a frequency deviation of more than ± 20%. Such a large deviation exceeds the acceptable working range of the FD/PD (Frequency Detector/Phase Detector) loop in the Clock Data Recovery (CDR), and the Frequency used in the FD/PD loop may cause the loop to be unlocked, and thus the Clock Recovery and Data retiming cannot be completed.

In contrast, conventional receiver chip design techniques include conventional calibration methods, such as using an off-chip reference frequency, adding off-chip components, and providing on-chip memory to calibrate the clock, to correct the frequency offset. However, in the process of implementing the present invention, the inventors found that in an actual application environment where the above-described conventional calibration method cannot be used, there is a technical problem that the frequency offset correction cannot be directly performed based on the on-chip condition.

Disclosure of Invention

In view of the above problems in the conventional methods, the present invention provides a CDR control loop frequency correction method, a CDR control loop frequency correction apparatus, a CDR control loop, and a receiver, which are capable of achieving efficient frequency offset correction.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in one aspect, a CDR control loop frequency correction method is provided, including:

after a receiver chip is powered on to work, control words prestored in a register are obtained;

a PLL loop for adjusting the internal oscillator to output a target reference frequency to the CDR control loop using the control word;

after the PLL loop is locked, sending the multi-path multi-phase clock output by the voltage-controlled oscillator into an FD/PD loop of the CDR control loop;

after the FD/PD loop is stable, carrying out error code detection on data output by the serial-parallel converter;

and if no error code is detected, finishing the frequency correction of the FD/PD loop.

In one embodiment, the pre-stored control words comprise at least two control words, and each control word corresponds to a different target reference frequency;

the above method further comprises the steps of:

if the error code is detected, sending the next control word prestored in the register into an internal oscillator;

returning to the step of adjusting the internal oscillator output target reference frequency to the PLL loop of the CDR control loop using the control word.

In one embodiment, the method further comprises the steps of:

after traversing all the control words, detecting all the control words corresponding to undetected error codes as candidate control words;

selecting a corresponding control word with a central target reference frequency from all candidate control words as an optimal control word; the optimal control word is used to frequency correct the CDR control loop.

In one embodiment, the method for determining that no error is detected is as follows:

and detecting a synchronous code in the data output by the serial-parallel converter, and determining that an error code is not detected in the data output by the serial-parallel converter within a set time period after the synchronous code.

In another aspect, an apparatus for frequency correction of a CDR control loop is provided, including:

the register module is used for outputting a prestored control word to an internal oscillator of the CDR control loop after the receiver chip is electrified and works; the control word is used for instructing the internal oscillator to output the target reference frequency to a PLL loop of the CDR control loop;

the error code detection module is used for carrying out error code detection on the data output by the serial-parallel converter after the FD/PD loop of the CDR control loop is stable and finishing the frequency correction of the FD/PD loop when the error code is not detected; the FD/PD loop enters the loop for stabilization under the action of a multi-path multi-phase clock output after the PLL loop finishes locking.

In yet another aspect, a CDR control loop is also provided, including an internal oscillator, a PLL loop, an FD/PD loop, an error detection circuit, and a register;

the internal oscillator is used for reading a control word prestored in the register and adjusting the frequency by using the control word after the chip is electrified and works so as to output a target reference frequency to the PLL loop;

the PLL loop is used for sending the multi-path multi-phase clock output by the voltage-controlled oscillator into the FD/PD loop after locking is finished;

the error code detection circuit is used for carrying out error code detection on the data output by the serial-parallel converter after the FD/PD loop is stable, and finishing the frequency correction on the FD/PD loop if the error code is not detected.

In one embodiment, the registers for pre-storing the control words comprise at least two registers, each register is used for pre-storing one control word, and each control word respectively corresponds to different target reference frequencies;

the internal oscillator is also used for reading the control word prestored in the next register and carrying out the output frequency adjustment of the next round when the error code detection circuit detects the error code.

In one embodiment, the error code detection circuit is further configured to, after traversing all the control words, detect all the control words corresponding to undetected error codes as candidate control words, and select a control word with a corresponding target reference frequency centered from the candidate control words as an optimal control word; the optimal control word is used to frequency correct the CDR control loop via an internal oscillator.

In one embodiment, the error detection circuit determines that the error detection result is an undetected error by detecting a sync code in data output from the serial-to-parallel converter and detecting no error in the data output from the serial-to-parallel converter within a set period of time after the sync code.

In still another aspect, a receiver is provided, which includes the CDR control loop.

One of the above technical solutions has the following advantages and beneficial effects:

according to the CDR control loop frequency correction method, device and receiver, the control word is pre-stored in the register in the chip and sent to the internal oscillator to set the output frequency of the internal oscillator, the target reference frequency output after adjustment is further used as the reference frequency of the PLL loop, and after the PLL loop is locked, the FD/PD loop works. After the FD/PD loop works stably, carrying out error code detection on the data output by the serial-parallel converter so as to detect whether error codes are generated in the data output by the CDR; when no error is detected, the frequency correction of the FD/PD loop is completed.

Compared with a frequency offset correction method in the chip design technology of a traditional receiver, under the condition that design requirements such as no off-chip reference frequency, no increase of off-chip elements, no calibration of an on-chip memory to a clock, as small as possible chip power consumption and area and the like are met, the reference clock is provided by adopting the on-chip ring oscillator, the defect that an FD/PD loop cannot be normally locked due to the frequency offset of the reference clock is overcome by a correction loop, the locking of the FD/PD loop is rapidly carried out on the chip, and the purpose of efficient frequency offset correction is achieved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional CDR control loop;

FIG. 2 is a schematic diagram of a receiver circuit according to one embodiment;

FIG. 3 is a flowchart illustrating a CDR control loop frequency calibration method according to an embodiment;

FIG. 4 is a flowchart illustrating a frequency calibration method for a CDR control loop according to another embodiment;

fig. 5 is a schematic block diagram of a CDR control loop frequency correction apparatus according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It should be appreciated that reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

One skilled in the art will appreciate that the embodiments described herein can be combined with other embodiments. The term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

The high-speed interface circuit comprises a transmitter part and a receiver part, and the design scheme provided by the application is applied to a receiver chip. In the chip design of the receiver, the high-precision quartz crystal oscillator, the high-precision RC type oscillator and the LC-tank type oscillator commonly used in the industry generate the reference clock. For a receiver chip using an on-chip reference clock, the on-chip reference clock is greatly affected by environmental factors such as process, voltage, and temperature, and usually has a large frequency deviation. Under the design requirements that an off-chip reference frequency cannot be used, off-chip components cannot be increased, an on-chip memory is not provided for calibrating a clock, the power consumption and the area of a chip are as small as possible, and the like, the conventional calibration method cannot be applied to frequency calibration of a receiver chip using an on-chip reference clock.

In summary, the design scheme provided by the application adopts the ring oscillator in the chip to provide the reference clock, and provides a new frequency correction scheme, when the FD/PD loop does not work normally, the correction process is started, and the reference frequency is corrected to be within the working range of the FD/PD, so that the CDR can be ensured to work normally under various process, temperature and voltage conditions.

As shown in fig. 1, which is a schematic diagram of a part of a circuit main body of a conventional receiver (chip), a conventional Phase Lock Loop (PLL) CDR with an on-chip reference clock includes two loops, a PLL and an FD/PD. After the system is powered on, the PLL firstly establishes and outputs a plurality of paths of multiphase clocks. The FD/PD loop then begins, initially operating the FD master loop, sampling the serial data with a clock generated by the PLL, and recovering a clock from the serial data that is approximately equal to the PLL frequency. Thereafter, the PD dominates the loop operation, and the recovered clock is aligned with the data edge, and the edge of the other clock, which is orthogonal to the clock, is aligned with the data center position, and retimes the data. The retimed serial data is converted into parallel data by a serial-to-parallel conversion circuit and sent to a digital unit circuit.

In order to meet design requirements and overcome the defect that an FD/PD loop cannot be normally locked due to frequency offset of a reference clock, a novel frequency correction method is added on the basis of the common design in the design scheme provided by the application.

The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.

Referring to fig. 2, in one embodiment, the present application provides a CDR control loop 100, which includes an internal oscillator 12, a PLL loop, an FD/PD loop, an error detection circuit 14, and a register 16. The register 16 is used to pre-store a control word. The internal oscillator 12 is used to read the control word pre-stored in the register 16 and adjust the frequency using the control word after the chip is powered on to output the target reference frequency to the PLL loop. The PLL loop is used for sending the multi-path multi-phase clock output by the voltage-controlled oscillator into the FD/PD loop after the locking is finished. The error code detection circuit 14 is configured to perform error code detection on the data output by the serial-to-parallel converter after the FD/PD loop is stable, and complete frequency correction on the FD/PD loop if an error code is not detected.

It is understood that, as shown in fig. 1 and 2, within the receiver chip, the internal oscillator 12, the PLL loop and FD/PD loop of the CDR control loop, and the digital unit circuit of the loop data output terminal, etc. may be divided, and the internal oscillator 12 may be used to provide the internal reference clock to the PLL loop. The PLL loop and the FD/PD loop may specifically include a phase frequency detector, a charge pump 1, a frequency detector, a charge pump 2, a phase detector/decision device, a charge pump 3, a loop filter, a voltage controlled oscillator, a frequency divider, and a serial-to-parallel converter, where connection relationships and data flow direction relationships between the components are as shown in fig. 1 and fig. 2, and functions implemented by the components may be understood by referring to the same functional principle of the corresponding components in the existing CDR control loop in the art.

The present embodiment may implement the error detection circuit 14 in the chip by using digital circuit elements in the chip, and may provide the register 16 for pre-storing the control word by using the register(s) in the chip, and the internal oscillator 12 may call the value (corresponding to the pre-stored control word) of the corresponding register 16 to implement the adjustment of the output frequency for implementing the frequency offset calibration.

Specifically, when the chip starts to operate after being powered on, the internal oscillator 12 reads the control word in the register 16, and the control word is used to reset the frequency adjustment switch of the internal oscillator 12, so that the internal oscillator 12 oscillates a new frequency, which may be referred to as a target reference frequency. This frequency is fed into the PLL loop to be used as a new reference frequency. And the PLL loop completes loop locking under the new reference frequency, and the multi-path multi-phase clock output by the locked voltage-controlled oscillator is sent to the FD/PD loop. Then the FD/PD loop is started, after the loop is stable, the error code detection circuit 14 detects whether the error code is output in the data output by the serial-parallel converter, if no error code is output, the frequency offset correction of the FD/PD loop is finished; if there is error code output, another pre-stored control word can be read to perform the correction processing again until the error code detection circuit 14 detects that there is no error code output in the data output by the serial-parallel converter, thereby completing the frequency offset correction of the FD/PD loop.

The CDR control loop 100, by pre-storing a control word in the on-chip register 16, sends the control word to the internal oscillator 12 to set the output frequency of the internal oscillator 12, and further uses the target reference frequency output after adjustment as the reference frequency of the PLL loop, after the PLL loop is locked, the FD/PD loop operates. After the FD/PD loop works stably, carrying out error code detection on the data output by the serial-parallel converter so as to detect whether error codes are generated in the data output by the CDR; when no error is detected, the frequency correction of the FD/PD loop is completed.

Compared with a frequency offset correction method in the chip design technology of a traditional receiver, under the condition that design requirements such as no off-chip reference frequency, no increase of off-chip elements, no calibration of an on-chip memory to a clock, as small as possible chip power consumption and area and the like are met, a ring oscillator in the chip is directly adopted to provide a reference clock, a correction loop overcomes the defect that an FD/PD loop cannot be normally locked due to the frequency offset of the reference clock, the locking of the FD/PD loop is rapidly carried out in the chip, and the purpose of efficient frequency offset correction is achieved.

In one embodiment, the registers 16 for pre-storing the control words include at least two registers, each register 16 is used for pre-storing one control word, and each control word corresponds to a different target reference frequency. The internal oscillator 12 is also used to read the control word pre-stored in the next register 16 and for the next round of output frequency adjustment when an error is detected by the error detection circuit 14.

It will be appreciated that the pre-stored control words may comprise more than two, each for setting a frequency adjustment switch in the internal oscillator 12 to cause the internal oscillator 12 to oscillate a new frequency. The target reference frequencies corresponding to the control words are different, and the control words are respectively used for regulating and outputting the target reference frequencies corresponding to the control words.

Specifically, when the chip starts to operate after being powered on, the frequency offset correction process is started, and the internal oscillator 12 reads the control word in the first register 16, where the first control word is used to reset the frequency adjustment switch of the internal oscillator 12, so that the internal oscillator 12 oscillates a new frequency, which may be referred to as a target reference frequency. This frequency is fed into the PLL loop to be used as a new reference frequency. And the PLL loop finishes loop locking under the new reference frequency, and the multi-path multi-phase clock output by the voltage-controlled oscillator after locking is sent to the FD/PD loop. Then, the FD/PD loop is started, and after the loop is stabilized, the error detection circuit 14 detects whether there is an error output in the data output from the serial-parallel converter. If so, the internal oscillator 12 reads the control word in the next register 16 and performs a frequency correction process using the next control word. If not, the frequency offset correction of the FD/PD loop is complete.

By setting a plurality of control words for frequency offset correction of the FD/PD loop, the reliability of correction can be effectively improved.

In one embodiment, the error detection circuit 14 is further configured to, after traversing all the control words, detect all the control words corresponding to undetected errors as candidate control words, and select a control word with a centered target reference frequency from the candidate control words as an optimal control word. The optimal control word is used for fast frequency correction of CDR control loop 100 by internal oscillator 12.

It is understood that in this embodiment, a round of frequency offset correction processing may be performed on each control word, for example, after the chip is powered on, the correction procedure is started, and the control word stored in the previous register 16 is sent to the internal oscillator 12 to reset the oscillation frequency of the internal oscillator 12, so as to output a new reference frequency. The new reference frequency is used as the reference frequency of the PLL loop, after the PLL loop is locked, the FD/PD loop operates, and the error detection circuit 14 detects whether there is an error output in the data output from the serial-to-parallel converter. Next, the next register 16 sends the next control word it holds to the internal oscillator 12, and the correction process described above is repeated. Until all control words have been traversed. In the above-mentioned correction process of each round, the error detection circuit 14 detects whether there is an error in the data output by the loop after each round of reference frequency adjustment.

Thereafter, the error detection circuit 14 may list all the detected control words without error as candidate control words, and then select the control word with the intermediate frequency corresponding to the control word as the optimal control word, and the correction is completed.

As such, in the calibration mode using the on-chip reference clock, the on-chip reference clock is greatly affected by the application environment, such as but not limited to the operating temperature, the manufacturing process, or the operating voltage. The application environment changes, which causes a corresponding frequency deviation. Therefore, by detecting the optimal control word, the optimal control word corresponding to each application environment can be selected for the CDR control loop 100 in different application environments, so that in practical application, the optimal control word in the current application environment can be directly called to perform the most efficient frequency offset correction of the FD/PD loop, thereby achieving the optimal correction effect.

In one embodiment, the error detection circuit 14 determines that the error detection result is an undetected error by detecting a sync code in the data output from the serial-to-parallel converter and when an error is not detected in the data output from the serial-to-parallel converter within a set period of time after the sync code.

Specifically, in the above embodiment, it is possible to determine whether an error is detected by directly detecting a sync code in the data output from the serial-to-parallel converter. In this embodiment, the error detection circuit 14 may detect whether the data output by the loop contains the sync code after the FD/PD loop is started and stabilized, and if the sync code is found and the data within a fixed time period (i.e. a set time period) after the sync code has no error, it indicates that no error is detected; otherwise, it means that an error is detected.

By the error code judging processing, the judging accuracy of whether the error code is detected can be further improved, so that the reliability and the accuracy of frequency offset correction of the FD/PD loop are further improved.

Referring to fig. 3, in an embodiment, the present application provides a CDR control loop frequency correction method, which may be applied to frequency offset correction of a non-reference clock type CDR control loop, and the method may include the following processing steps S12 to S20:

s12, after the receiver chip is powered on to work, the control word prestored in the register is obtained;

s14, adjusting the output target reference frequency of the internal oscillator to the PLL loop of the CDR control loop by using the control word;

s16, after the PLL loop is locked, the multi-path multi-phase clock output by the voltage-controlled oscillator is sent to the FD/PD loop of the CDR control loop;

s18, after the FD/PD loop is stable, error code detection is carried out on the data output by the serial-parallel converter;

and S20, if no error is detected, finishing the frequency correction of the FD/PD loop.

It is understood that the explanation of the clock-type CDR control loop and the feature terms can be understood by referring to the corresponding explanation of the embodiments of the CDR control loop 100, and the description is not repeated here.

Specifically, when the receiver chip starts to operate after being powered on, the internal oscillator may read a control word in the register, and the control word is used to reset the frequency adjustment switch of the internal oscillator, so that the internal oscillator oscillates a new frequency, which may be referred to as a target reference frequency. This frequency is fed into the PLL loop to be used as a new reference frequency. And the PLL loop completes loop locking under the new reference frequency, and the multi-path multi-phase clock output by the locked voltage-controlled oscillator is sent to the FD/PD loop. Then the FD/PD loop is started, after the loop is stable, the error code detection circuit detects whether the error code is output in the data output by the serial-parallel converter, if no error code is output, the frequency offset correction of the FD/PD loop is finished; if the error code is output, another pre-stored control word can be read to carry out correction processing again until the error code detection circuit detects that no error code is output in the data output by the serial-parallel converter, thereby completing the frequency offset correction of the FD/PD loop.

According to the CDR control loop frequency correction method, the control word is pre-stored in the register in the chip and sent to the internal oscillator to set the output frequency of the internal oscillator, the target reference frequency output after adjustment is further used as the reference frequency of the PLL loop, and after the PLL loop is locked, the FD/PD loop works. After the FD/PD loop works stably, carrying out error code detection on the data output by the serial-parallel converter so as to detect whether error codes are generated in the data output by the CDR; when no error is detected, the frequency correction of the FD/PD loop is completed.

Compared with a frequency offset correction method in the chip design technology of a traditional receiver, under the condition that design requirements of not using an off-chip reference frequency, not increasing an off-chip element, not providing an on-chip memory to calibrate a clock, having the smallest chip power consumption and area are met, the on-chip ring oscillator is directly adopted to provide the reference clock, a correction loop overcomes the defect that an FD/PD loop cannot be normally locked due to the frequency offset of the reference clock, the FD/PD loop is quickly locked in the chip, and the purpose of efficiently correcting the frequency offset is achieved.

In one embodiment, the pre-stored control words include at least two control words, and each control word corresponds to a different target reference frequency. The above method may further comprise:

when the error code is detected, sending the next control word prestored in the register into an internal oscillator; return is made to step S14 described above.

It will be appreciated that the pre-stored control words may comprise more than two, each for setting the frequency adjustment switch in the internal oscillator to cause the internal oscillator to oscillate to a new frequency. The target reference frequencies corresponding to the control words are different, and the control words are respectively used for regulating and outputting the target reference frequencies corresponding to the control words.

Specifically, after the receiver chip is powered on, the frequency offset correction process is started, and the internal oscillator reads the control word in the first register, where the first control word is used to reset the frequency adjustment switch of the internal oscillator, so that the internal oscillator oscillates a new frequency, which may be referred to as a target reference frequency. This frequency is fed into the PLL loop to be used as a new reference frequency. And completing PLL loop locking at the new reference frequency, and sending the multi-path multi-phase clock output by the locked voltage-controlled oscillator into the FD/PD loop. And then the FD/PD loop is started, and after the loop is stabilized, the error code detection circuit detects whether the error code is output in the data output by the serial-parallel converter or not. If so, the internal oscillator reads the control word in the next register and performs the frequency correction process using the next control word. If not, the frequency offset correction of the FD/PD loop is complete.

By setting a plurality of control words for frequency offset correction of the FD/PD loop, the reliability of correction can be effectively improved.

In one embodiment, as shown in fig. 4, the method may further include the following processing steps:

after traversing all the control words, detecting all the control words corresponding to undetected error codes as candidate control words;

selecting a corresponding control word with a central target reference frequency from the candidate control words as an optimal control word; the optimal control word is used to frequency correct the CDR control loop.

It is understood that, in this embodiment, a round of frequency offset correction processing may be performed on each control word, for example, after the chip is powered on, the correction procedure is started, and the control word stored in the previous register is sent to the internal oscillator to reset the oscillation frequency of the internal oscillator, so as to output a new reference frequency. The new reference frequency is used as the reference frequency of the PLL loop, after the PLL loop is locked, the FD/PD loop works, and the error code detection circuit detects whether the error code is output in the data output by the serial-parallel converter. Next, the next register sends the next control word it holds to the internal oscillator, and the correction process is repeated. Until all control words have been traversed. In the correction process of each round, the error code detection circuit detects whether error codes are generated in the data output by the loop after the reference frequency of each round is adjusted.

After that, the error detection circuit can list out all the detected control words under the condition of no error as candidate control words, then selects the control word with the intermediate frequency corresponding to the control word as the optimal control word, and the correction is finished.

In this way, in the on-chip reference clock calibration mode, the on-chip reference clock is greatly influenced by the application environment, such as but not limited to the operating temperature, the manufacturing process, or the operating voltage. The application environment changes, which causes a corresponding frequency deviation. Therefore, by detecting the optimal control word, the optimal control word corresponding to each application environment can be selected for the CDR control loop under different application environments, so that in practical application, the optimal control word under the current application environment can be directly called to carry out the most efficient frequency offset correction of the FD/PD loop, and the optimal correction effect is achieved.

In one embodiment, the way to determine that no error is detected is:

and detecting a synchronous code in the data output by the serial-parallel converter, and determining that an error code is not detected in the data output by the serial-parallel converter within a set time period after the synchronous code.

Specifically, in the above embodiment, it is possible to determine whether an error is detected by directly detecting a sync code in the data output from the serial-parallel converter. In this embodiment, after the FD/PD loop is started and stabilized, the error detection circuit may detect whether the data output by the CDR control loop contains a synchronization code, and if the synchronization code is found and the data within a fixed time period (i.e., a set time period) after the synchronization code has no error, it indicates that an error is not detected; otherwise, it means that an error is detected.

By the error code judging processing, the judging accuracy of whether the error code is detected can be further improved, so that the reliability and the accuracy of frequency offset correction of the FD/PD loop are further improved.

It should be understood that although the various steps in the flowcharts of fig. 3 and 4 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps of fig. 3 and 4 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

Referring to fig. 5, in an embodiment, a CDR control loop frequency correction apparatus 200 is provided, which can be applied to frequency correction of a CDR control loop on a receiver chip using an on-chip reference clock, where the CDR control loop frequency correction apparatus 200 includes a register module 201 and an error code detection module 203. The register module 201 is configured to output a pre-stored control word to an internal oscillator of the CDR control loop after the receiver chip is powered on; the control word is used to instruct the internal oscillator to output the target reference frequency to the PLL loop of the CDR control loop. The error code detection module 203 is used for performing error code detection on data output by the serial-parallel converter after an FD/PD loop of the CDR control loop is stable, and completing frequency correction on the FD/PD loop when an error code is not detected; the FD/PD loop enters the loop for stabilization under the action of a multi-path multi-phase clock output after the PLL loop finishes locking.

The CDR control loop frequency correction apparatus 200 pre-stores a control word in the on-chip register module 201, and sends the control word to the internal oscillator to set the output frequency of the internal oscillator, and further uses the target reference frequency output after adjustment as the reference frequency of the PLL loop, and after the PLL loop is locked, the FD/PD loop operates. After the FD/PD loop works stably, the error code detection module 203 performs error code detection on the data output by the serial-parallel converter to detect whether an error code is generated in the data output by the CDR; when no error is detected, the frequency correction of the FD/PD loop is finished.

Compared with a frequency offset correction method in the chip design technology of a traditional receiver, under the condition that design requirements such as no use of an off-chip reference frequency, no increase of off-chip elements, no calibration of an on-chip memory to a clock, as small as possible chip power consumption and area and the like are met, a reference clock is provided by using an on-chip ring oscillator, a correction loop overcomes the defect that an FD/PD loop cannot be normally locked due to the frequency offset of the reference clock, the FD/PD loop locking is rapidly carried out on the FD/PD loop in the chip, and the purpose of efficient frequency offset correction is achieved.

In one embodiment, the pre-stored control words include at least two control words, and each control word corresponds to a different target reference frequency. The register module 201 may be further configured to send a pre-stored next control word to the internal oscillator when an error code is detected, so as to perform output frequency adjustment again.

In an embodiment, the error code detecting module 203 may be further configured to detect, after traversing all the control words, all the control words corresponding to undetected error codes as candidate control words; selecting a control word corresponding to the target reference frequency in the middle from all the candidate control words as an optimal control word; the optimal control word is used for fast frequency correction of the CDR control loop.

In an embodiment, the method for determining that no error is detected is as follows: and detecting a synchronous code in the data output by the serial-parallel converter, and determining that an error code is not detected in the data output by the serial-parallel converter within a set time period after the synchronous code.

For specific limitations of the CDR control loop frequency correction apparatus 200, reference may be made to the corresponding limitations of the CDR control loop frequency correction method, which is not described herein again. The various modules in the CDR control loop frequency correction apparatus 200 described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a receiver chip, and can also be stored in a memory on a chip in a software form, so that the controller can call and execute the corresponding operations of the modules.

In one embodiment, a receiver is also provided that includes the CDR control loop 100 described above.

It is understood that, regarding the specific explanation of the CDR control loop 100 in the present embodiment, the same can be understood by referring to the corresponding explanation of each embodiment of the CDR control loop 100, and the description is not repeated here. It should be noted that the receiver in this embodiment may include other existing components not described in this specification, in addition to the above-mentioned improved CDR control loop 100, and it can be understood by referring to the structure of the receiver chip existing in the art, and the detailed description is not listed herein.

In the receiver, the CDR control loop 100 is applied, and the ring oscillator in the chip is used to provide the reference clock, so that the frequency correction loop overcomes the defect that the FD/PD loop cannot be normally locked due to the frequency offset of the reference clock, and the FD/PD loop is quickly locked in the chip, thereby achieving the purpose of efficiently correcting the frequency offset in the receiver chip.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the spirit of the present application, and all of them fall within the scope of the present application. Therefore, the protection scope of the present patent should be subject to the appended claims.

Claims (10)

1. A CDR control loop frequency correction method, comprising the steps of:

after a receiver chip is powered on to work, a control word prestored in a register is obtained;

utilizing the control word to adjust an internal oscillator to output a target reference frequency to a PLL loop of a CDR control loop;

after the PLL loop is locked, sending the multi-path multi-phase clock output by the voltage-controlled oscillator into an FD/PD loop of the CDR control loop;

after the FD/PD loop is stable, carrying out error code detection on data output by the serial-parallel converter;

and if no error code is detected, finishing the frequency correction of the FD/PD loop.

2. The CDR control loop frequency correction method of claim 1, wherein the pre-stored control words comprise at least two control words, each control word corresponding to a different target reference frequency;

the method further comprises the steps of:

if the error code is detected, sending the next control word prestored in the register into the internal oscillator;

returning to the step of adjusting the internal oscillator output target reference frequency to the PLL loop of the CDR control loop using the control word.

3. The CDR control loop frequency correction method of claim 2, further comprising the steps of:

after traversing all the control words, detecting all the control words corresponding to undetected error codes as candidate control words;

selecting a corresponding control word with a central target reference frequency from the candidate control words as an optimal control word; the optimal control word is used for frequency correction of the CDR control loop.

4. The method according to any of claims 1 to 3, wherein the determination that no bit error is detected is performed by:

and detecting a synchronous code in the data output by the serial-parallel converter, and determining that an error code is not detected in the data output by the serial-parallel converter within a set time period after the synchronous code.

5. An apparatus for CDR control loop frequency correction, comprising:

the register module is used for outputting a prestored control word to an internal oscillator of the CDR control loop after the receiver chip is electrified and works; the control word is used for instructing the internal oscillator to output a target reference frequency to a PLL loop of the CDR control loop;

the error code detection module is used for carrying out error code detection on data output by the serial-parallel converter after an FD/PD loop of the CDR control loop is stable, and finishing frequency correction on the FD/PD loop when the error code is not detected; and the FD/PD loop enters the loop for stabilization under the action of a multi-path multi-phase clock output after the PLL loop finishes locking.

6. A CDR control loop circuit is characterized by comprising an internal oscillator, a PLL loop circuit, an FD/PD loop circuit, an error code detection circuit and a register;

the internal oscillator is used for reading a control word prestored in the register and adjusting the frequency by using the control word after the chip is electrified and works so as to output a target reference frequency to the PLL loop;

the PLL loop is used for sending the multi-path multi-phase clock output by the voltage-controlled oscillator to the FD/PD loop after locking is finished;

the error code detection circuit is used for carrying out error code detection on the data output by the serial-parallel converter after the FD/PD loop is stable, and finishing the frequency correction on the FD/PD loop if the error code is not detected.

7. The CDR control loop of claim 6, wherein the registers for pre-storing control words comprise at least two registers, each of the registers is used for pre-storing one of the control words, and each of the control words corresponds to a different target reference frequency;

and the internal oscillator is also used for reading a control word prestored in the next register when the error code detection circuit detects an error code and is used for carrying out output frequency adjustment of the next round.

8. The CDR control loop of claim 7, wherein the error detection circuit is further configured to, after traversing all the control words, detect all the control words corresponding to undetected errors as candidate control words, and select a corresponding control word with a centered target reference frequency from the candidate control words as an optimal control word; the optimal control word is used for frequency correction of the CDR control loop by the internal oscillator.

9. The CDR control loop of any of claims 6 to 8, wherein the error detection circuit determines that an error is not detected by detecting a sync code in the data output from the serial to parallel converter and when an error is not detected in the data output from the serial to parallel converter within a set period of time after the sync code.

10. A receiver comprising a CDR control loop according to any one of claims 6 to 9.

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