CN114975329A - Fan-out type packaging structure of heterogeneous chip high-density interconnection and packaging method thereof - Google Patents

Fan-out type packaging structure of heterogeneous chip high-density interconnection and packaging method thereof Download PDF

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CN114975329A
CN114975329A CN202210696084.1A CN202210696084A CN114975329A CN 114975329 A CN114975329 A CN 114975329A CN 202210696084 A CN202210696084 A CN 202210696084A CN 114975329 A CN114975329 A CN 114975329A
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heterogeneous chip
fan
wafer
heterogeneous
density interconnection
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柯峥
朱家昌
章国涛
高艳
李聪
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Wuxi Zhongwei High Tech Electronic Co ltd
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Wuxi Zhongwei High Tech Electronic Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

Abstract

The invention relates to the technical field of integrated circuit packaging, and particularly discloses a fan-out type packaging structure for high-density interconnection of heterogeneous chips, which comprises a first heterogeneous chip, a high-density interconnection unit, a second heterogeneous chip, a wafer-level plastic package body, a rewiring layer and solder balls, wherein the first heterogeneous chip, the high-density interconnection unit and the second heterogeneous chip are respectively and plastically packaged in the wafer-level plastic package body, the rewiring layer is formed on the lower surface of the wafer-level plastic package body, a plurality of solder balls are arranged at UBM positions on the lower surface of the rewiring layer, and the solder balls are used for leading out signals. The invention also discloses a fan-out type packaging method for the high-density interconnection of the heterogeneous chips. The fan-out type packaging structure for the high-density interconnection of the heterogeneous chips breaks through the limitation of the traditional RDL technology on the number of rewiring layers, realizes the wafer-level packaging of the high-density interconnection of the heterogeneous chips, and is safe and reliable.

Description

Fan-out type packaging structure for high-density interconnection of heterogeneous chips and packaging method thereof
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a fan-out type packaging structure for high-density interconnection of heterogeneous chips and a fan-out type packaging method for high-density interconnection of heterogeneous chips.
Background
With the development of electronic products toward miniaturization, high performance, high reliability, and the like, the system integration level is also increasing, and the feature size of the transistor is reduced to below 10 nm. In this case, the leakage caused by the quantum tunneling effect is very serious, and the way to improve the performance by further reducing the feature size of the integrated circuit and the line width of the interconnection line is limited by the physical characteristics of the material and the device process, and the conventional moore's law is difficult to continue to develop.
The fan-out package can effectively improve the performance in transmission, power consumption, reliability and the like, and therefore, the fan-out package is considered to be one of the important means for continuing and surpassing the moore's law. Fan-out packages connect different chips together using re-Routing (RDL) technology, which is a very important interconnect technology. With the improvement of the performance of integrated circuit chips and the development of miniaturization, the interconnection density between the chips is increased sharply, and the number of layers of the RDL is forced to increase continuously. However, due to the limitations of equipment, materials and process level, the preparation of multilayer RDL layers (4 layers and above) is very difficult and costly, and the development requirement of high interconnection density cannot be met. Therefore, in order to meet the development requirements of high performance and high interconnection density of the present microelectronic system, it is urgently needed to develop a fan-out package structure for heterogeneous chip high-density interconnection.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides a heterogeneous chip high-density interconnection fan-out type packaging structure and a heterogeneous chip high-density interconnection fan-out type packaging method, can effectively break through the limitation of the number of wiring layers in the traditional RDL technology, realizes high-density interconnection fan-out type packaging and system packaging, saves cost, and is safe and reliable.
The invention provides a fan-out type packaging structure for high-density interconnection of heterogeneous chips, which comprises a first heterogeneous chip, a high-density interconnection unit, a second heterogeneous chip, a wafer-level plastic package body, a rewiring layer and solder balls, wherein the first heterogeneous chip, the high-density interconnection unit and the second heterogeneous chip are respectively and plastically packaged in the wafer-level plastic package body, the rewiring layer is formed on the lower surface of the wafer-level plastic package body, a plurality of solder balls are arranged at UBM positions on the lower surface of the rewiring layer, and the solder balls are used for leading out signals.
Further, the substrate materials of the first heterogeneous chip and the second heterogeneous chip respectively comprise Si, GaAs, GaN or SiC.
Further, the number of the high-density interconnection units is at least 1.
Further, the substrate material of the high-density interconnection unit includes Si or glass.
Further, the material of the solder ball comprises SnPb, SnAg or SnAgCu.
As another aspect of the present invention, a fan-out packaging method for heterogeneous chip high-density interconnection is provided, wherein the fan-out packaging method for heterogeneous chip high-density interconnection comprises the following steps:
step S1: providing a metal carrier plate and a temporary bonding film, and coating the temporary bonding film on the metal carrier plate;
step S2: respectively attaching a first heterogeneous chip, a high-density interconnection unit and a second heterogeneous chip to the metal carrier plate through the temporary bonding film;
step S3: encapsulating the first heterogeneous chip, the high-density interconnection unit and the second heterogeneous chip by using a wafer-level plastic package body to obtain a secondary reconstructed resin wafer;
step S4: stripping the temporary bonding film and the metal carrier plate;
step S5: forming a rewiring layer on the lower surface of the secondary reconstituted resin wafer;
step S6: and a plurality of solder balls are arranged at the UBM position on the lower surface of the rewiring layer.
Further, the thickness of the metal carrier plate is not less than 1mm, and the thickness of the temporary bonding film is not less than 100 μm.
Further, the method also comprises the following steps: and forming a rewiring layer on the lower surface of the secondary reconstituted resin wafer by using PI glue and a wafer-level multilayer rewiring process.
Furthermore, the wafer-level multilayer rewiring process is a wiring process in which a metal layer and a passivation layer are overlapped; the rewiring layer at least comprises 1 metal layer; the thickness of the passivation layer is larger than that of the formed metal layer, and the passivation layer wraps the metal layer; the thicknesses of the metal layers are not less than 2 μm, and the thicknesses of the passivation layers are not less than 5 μm.
Further, the process of ball mounting at the UBM comprises wafer-level ball mounting or solder paste brushing.
The fan-out type packaging structure and the packaging method for the heterogeneous chip high-density interconnection provided by the invention have the following advantages:
(1) the high-density interconnection units and the heterogeneous chips are interconnected through fan-out packaging, so that the defect of limitation of the number of layers of RDL wiring is overcome, and the application requirements of high-performance and high-integration-density micro-system packaging can be met;
(2) because the mold sealing resin of the fan-out package is too thin and has a large difference with the CTE of the chip, the alignment precision in the photoetching process can be caused by small deformation and temperature change, and the production yield is further reduced; the invention can reduce the number of RDL wiring layers, thereby reducing the alignment precision deviation caused by excessive RDL wiring layers and improving the production yield;
(3) from the cost perspective, the cost ratio of the RDL in the fan-out package is very high, and especially the cost ratio of more than 2 and 3 layers is very high; the invention can effectively reduce the number of layers of RDL, thereby obviously saving the cost, and therefore, the invention has higher economic value and practical value.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic view of the temporary bonding film pressed to a metal carrier plate according to the present invention.
Fig. 2 is a schematic diagram of the present invention for mounting heterogeneous chips and high-density interconnection units to a metal carrier.
Fig. 3 is a schematic diagram of a wafer in which a wafer-level plastic package process is used to encapsulate a heterogeneous chip and a high-density interconnection unit to obtain a reconstituted wafer.
Fig. 4 is a schematic diagram of the metal carrier and the temporary build-up film stripped off in the present invention.
FIG. 5 is a schematic diagram of rewiring and UBM fabrication using a wafer level fan-out process in accordance with the present invention.
FIG. 6 is a schematic diagram of the invention after wafer level bumping at UBM of the redistribution layer.
Description of reference numerals: 101-a temporary bonding film; 102-a metal carrier plate; 103-a first heterogeneous chip; 104-high density interconnect cells; 105-a second heterogeneous chip; 106-wafer level plastic package body; 107-rewiring layer; 108-solder balls.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The fan-out package structure of heterogeneous chip high-density interconnection provided in the embodiment of the present invention is a final structure schematic diagram of the fan-out package structure of heterogeneous chip high-density interconnection provided in the present invention, as shown in fig. 6, the fan-out package structure includes a first heterogeneous chip 103, a high-density interconnection unit 104, a second heterogeneous chip 105, a wafer-level plastic package body 106, a redistribution layer 107, and solder balls 108, the first heterogeneous chip 103, the high-density interconnection unit 104, and the second heterogeneous chip 105 are respectively plastic-packaged inside the wafer-level plastic package body 106, the redistribution layer 107 is formed on a lower surface of the wafer-level plastic package body 106, a plurality of solder balls 108 are disposed at a UBM on a lower surface of the redistribution layer 107, and the solder balls 108 are used for leading out signals.
Preferably, the substrate materials of the first heterogeneous chip 103 and the second heterogeneous chip 105 both comprise Si, GaAs, GaN or SiC.
Preferably, the number of the high-density interconnection units 104 is at least 1.
Preferably, the substrate material of the high-density interconnection unit 104 comprises Si or glass, and is an interconnection unit with extremely small line width and line distance, which is manufactured by a conventional CMOS process.
Preferably, the material of the solder ball 108 includes SnPb, SnAg, or SnAgCu.
It should be noted that the UBM is an under bump metallization.
The embodiment of the invention provides a fan-out type packaging method for heterogeneous chip high-density interconnection, as shown in fig. 1-6, the fan-out type packaging structure for heterogeneous chip high-density interconnection can be prepared by the following specific packaging method, and the fan-out type packaging method for heterogeneous chip high-density interconnection comprises the following steps:
as shown in fig. 1, step S1: providing a metal carrier 102 and a temporary bonding film 101, and coating the temporary bonding film 101 on the metal carrier 102;
as shown in fig. 2, step S2: attaching a first heterogeneous chip 103, a high-density interconnection unit 104 and a second heterogeneous chip 105 to the metal carrier plate 102 through the temporary bonding film 101 by using a high-precision chip mounter respectively;
it should be noted that the heterogeneous chip and the high-density interconnection unit are mounted on the metal carrier by a face down process.
As shown in fig. 3, step S3: based on a wafer-level plastic package process, encapsulating the first heterogeneous chip 103, the high-density interconnection unit 104 and the second heterogeneous chip 105 by using a wafer-level plastic package body 106 to obtain a secondary reconstituted resin wafer;
as shown in fig. 4, step S4: stripping the temporary bonding film 101 and the metal carrier plate 102 by adopting a bonding release technology;
as shown in fig. 5, step S5: forming a rewiring layer 107 on the lower surface of the secondary reconstituted resin wafer to realize high-density interconnection of heterogeneous chips;
as shown in fig. 6, step S6: a plurality of solder balls 108 are arranged at the UBM position on the lower surface of the rewiring layer 107, and the leading-out of signals is realized through the solder balls 108.
The secondary reconstituted resin wafer is subjected to a dicing process to obtain a final package structure.
Preferably, the thickness of the metal carrier 102 is not less than 1mm, and the thickness of the temporary bonding film 101 is not less than 100 μm.
Preferably, the method further comprises the following steps: a rewiring layer 107 is formed on the lower surface of the secondary reconstituted resin wafer using PI glue and a wafer level multilayer rewiring process.
Preferably, the wafer-level multilayer rewiring process is a wiring process in which a metal layer and a passivation layer are overlapped; the redistribution layer 107 includes at least 1 metal layer; the thickness of the passivation layer is larger than that of the formed metal layer, and the passivation layer wraps the metal layer; the thicknesses of the metal layers are not less than 2 μm, and the thicknesses of the passivation layers are not less than 5 μm.
Preferably, the process of ball mounting at the UBM comprises wafer-level ball mounting or solder paste brushing.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (10)

1. The fan-out type packaging structure is characterized by comprising a first heterogeneous chip (103), a high-density interconnection unit (104), a second heterogeneous chip (105), a wafer-level plastic package body (106), a rewiring layer (107) and solder balls (108), wherein the first heterogeneous chip (103), the high-density interconnection unit (104) and the second heterogeneous chip (105) are respectively and plastically packaged in the wafer-level plastic package body (106), the rewiring layer (107) is formed on the lower surface of the wafer-level plastic package body (106), a plurality of solder balls (108) are arranged at UBM positions of the lower surface of the rewiring layer (107), and the solder balls (108) are used for leading out signals.
2. The heterogeneous chip high density interconnect fan-out package structure of claim 1, wherein the substrate material of the first heterogeneous chip (103) and the second heterogeneous chip (105) each comprise Si, GaAs, GaN, or SiC.
3. The fan-out package structure of heterogeneous chip high density interconnects of claim 1, wherein the number of high density interconnect units (104) is at least 1.
4. The fan-out package structure of heterogeneous chip high density interconnects of claim 1, wherein the substrate material of the high density interconnect units (104) comprises Si or glass.
5. The fan-out package structure of heterogeneous chip high density interconnect of claim 1, in which a material of the solder balls (108) comprises SnPb, SnAg or SnAgCu.
6. A fan-out type packaging method for heterogeneous chip high-density interconnection is characterized by comprising the following steps:
step S1: providing a metal carrier (102) and a temporary bonding film (101), and coating the temporary bonding film (101) on the metal carrier (102);
step S2: attaching a first heterogeneous chip (103), a high-density interconnection unit (104) and a second heterogeneous chip (105) on the metal carrier plate (102) through the temporary bonding film (101) respectively;
step S3: encapsulating the first heterogeneous chip (103), the high-density interconnection unit (104) and the second heterogeneous chip (105) by using a wafer-level plastic package body (106) to obtain a secondary reconstituted resin wafer;
step S4: stripping the temporary bonding film (101) and the metal carrier plate (102);
step S5: forming a rewiring layer (107) on the lower surface of the secondary reconstituted resin wafer;
step S6: and a plurality of solder balls (108) are arranged on the UBM position on the lower surface of the rewiring layer (107).
7. The fan-out packaging method for heterogeneous chip high-density interconnection according to claim 6, wherein the thickness of the metal carrier (102) is not less than 1mm, and the thickness of the temporary bonding film (101) is not less than 100 μm.
8. The fan-out packaging method for heterogeneous chip high-density interconnect of claim 6, further comprising the steps of: and forming a rewiring layer (107) on the lower surface of the secondary reconstituted resin wafer by using PI glue and a wafer-level multilayer rewiring process.
9. The fan-out packaging method for high-density interconnection of heterogeneous chips according to claim 8, wherein the wafer-level multilayer rewiring process is a wiring process in which a metal layer and a passivation layer are overlapped; the rewiring layer (107) comprises at least 1 metal layer; the thickness of the passivation layer is larger than that of the formed metal layer, and the passivation layer wraps the metal layer; the thicknesses of the metal layers are not less than 2 μm, and the thicknesses of the passivation layers are not less than 5 μm.
10. The fan-out packaging method for heterogeneous chip high density interconnect according to claim 6, wherein the ball-mounting process at the UBM comprises wafer-level ball-mounting or solder paste-brushing.
CN202210696084.1A 2022-06-20 2022-06-20 Fan-out type packaging structure of heterogeneous chip high-density interconnection and packaging method thereof Pending CN114975329A (en)

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