CN114972308A - Chip positioning method, system, computer and readable storage medium - Google Patents
Chip positioning method, system, computer and readable storage medium Download PDFInfo
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Abstract
The invention provides a chip positioning method, a system, a computer and a readable storage medium, wherein the method comprises the steps of carrying out local scanning on a current wafer through a lens to obtain local positioning coordinates of chips and position data among the chips; calculating a reference distance value corresponding to the chip, and calculating lens parameters corresponding to the current lens according to the local positioning coordinates and the reference distance value; acquiring integral positioning coordinates of the chip, and eliminating distortion coordinates in the integral positioning coordinates according to lens internal parameters and lens distortion parameters to generate linear positioning coordinates; and carrying out standardization processing on the linear positioning coordinates to generate theoretical positioning coordinates, and replacing the theoretical chip coordinate values in the theoretical positioning coordinates with actual chip coordinate values in the overall positioning coordinates. After the lens parameters are calculated by the method, different wafers of the same product can be scanned repeatedly, the generated detection result is accurate and stable, and the positioning deviation is eliminated.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a chip positioning method, system, computer, and readable storage medium.
Background
Wafer refers to the chip used to fabricate silicon semiconductor circuits, and the starting material is usually silicon. The manufacturing process comprises dissolving high-purity polysilicon, doping into silicon crystal, and slowly pulling out to obtain cylindrical single crystal silicon. After being ground, polished and sliced, the silicon crystal bar is formed into a silicon wafer, namely a wafer. In the prior art, a plurality of LED chips are arranged on a manufactured wafer, and the positions of the arranged LED chips need to be accurately positioned, so as to ensure the yield of products.
Most of the prior art positions the LED chip by pattern edge matching and image similarity matching, however, due to the influence of factors such as external environment and equipment accuracy, the prior art has a certain deviation in positioning the LED chip, thereby reducing the yield of the product.
Disclosure of Invention
Based on this, the present invention provides a chip positioning method, a chip positioning system, a computer and a readable storage medium, so as to solve the problem that in the prior art, due to the influence of factors such as external environment and equipment precision, a certain deviation exists in the positioning of an LED chip, thereby reducing the product yield.
The first aspect of the embodiments of the present invention provides a chip positioning method, which is applied to a wafer, where a plurality of chips are arranged on a surface of the wafer, and the method includes:
the method comprises the steps that a current wafer is locally scanned through a lens to obtain local positioning coordinates of a plurality of chips on the surface of the current wafer and position data among the chips, wherein the position data comprise line intervals and column intervals among the chips;
calculating reference distance values corresponding to a plurality of chips according to the line distances and the column distances, and calculating lens parameters corresponding to the current lens according to the local positioning coordinates and the reference distance values based on a preset algorithm, wherein the lens parameters comprise lens internal parameters and lens distortion parameters;
carrying out full-disc scanning on the wafer through the current lens to obtain integral positioning coordinates of a plurality of chips on the surface of the wafer, and eliminating distortion coordinates in the integral positioning coordinates according to the lens internal parameters and the lens distortion parameters to generate corresponding linear positioning coordinates;
and carrying out standardization processing on the linear positioning coordinate based on a preset single mapping matrix to generate a corresponding theoretical positioning coordinate, and replacing a theoretical chip coordinate value in the theoretical positioning coordinate with an actual chip coordinate value in the overall positioning coordinate.
The beneficial effects of the invention are: the method comprises the steps of firstly, carrying out local scanning on a current wafer through a lens to obtain local positioning coordinates of a plurality of chips on the surface of the current wafer and position data among the chips, then calculating reference distance values corresponding to the chips according to the obtained position data, and further calculating lens parameters corresponding to the lens according to the position data and the reference distance values. On the basis, full-disc scanning is performed on the current wafer through the lens so as to correspondingly obtain the overall positioning coordinates of the plurality of chips, distortion coordinates in the current overall positioning coordinates are eliminated according to the lens parameters so as to generate corresponding linear positioning coordinates, and finally, the generated linear positioning coordinates are standardized only on the basis of a preset single mapping matrix so as to generate corresponding theoretical positioning coordinates, and the actual chip coordinate values in the overall positioning coordinates are replaced by the theoretical chip coordinate values in the theoretical positioning coordinates, so that the positioning of the plurality of chips on the surface of the current wafer can be simply and quickly completed. By means of the method, different wafers of the same product can be scanned repeatedly after the lens parameters are calculated for the first time, meanwhile, the generated detection result is accurate and stable, positioning deviation is eliminated, the yield of the product is improved, and the method is suitable for large-scale popularization and use.
Preferably, the step of calculating the reference pitch values corresponding to the plurality of chips according to the row pitch and the column pitch includes:
when the line spacing and the column spacing between a plurality of chips are obtained, screening out the maximum value and the minimum value in the line spacing and the column spacing, and calculating the average value corresponding to the remaining intermediate values of the line spacing and the column spacing so as to set the average value as the reference spacing value.
Preferably, the step of normalizing the linear positioning coordinates based on a preset single mapping matrix to generate corresponding theoretical positioning coordinates includes:
inputting theoretical positioning coordinates of a plurality of chips into a blank mapping matrix, and fitting the mapping matrix based on a RANSAC algorithm to generate a single mapping matrix;
and mapping the linear positioning coordinates onto a standard rectangular grid through the single mapping matrix to generate corresponding theoretical positioning coordinates.
Preferably, the step of replacing the theoretical chip coordinate value in the theoretical positioning coordinate with the actual chip coordinate value in the overall positioning coordinate includes:
calculating theoretical positioning coordinates on the image corresponding to the standard rectangular grid through the single mapping matrix, and comparing theoretical chip coordinate values in the theoretical positioning coordinates with actual chip coordinate values in the overall positioning coordinates to obtain positioning errors between the theoretical chip coordinate values and the actual chip coordinate values;
judging whether the positioning error between the theoretical chip coordinate value and the actual chip coordinate value corresponding to each chip is larger than a preset threshold value or not;
and replacing the theoretical chip coordinate value in the theoretical positioning coordinate with the actual chip coordinate value in the overall positioning coordinate if the positioning error between the theoretical chip coordinate value corresponding to the chip and the actual chip coordinate value is judged to be larger than a preset threshold.
Preferably, the step of replacing the theoretical chip coordinate value in the theoretical positioning coordinate with the actual chip coordinate value in the overall positioning coordinate further includes:
when the theoretical positioning coordinate is obtained, calculating a theoretical chip coordinate value in the theoretical positioning coordinate to the overall positioning coordinate in a reverse direction according to the lens intrinsic parameters and the lens distortion parameters, so as to replace the actual chip coordinate value with the theoretical chip coordinate value in the overall positioning coordinate.
A second aspect of the embodiments of the present invention provides a chip positioning system, which is applied to a wafer, wherein a plurality of chips are arranged on a surface of the wafer, and the system includes:
the first acquisition module is used for acquiring a detection image of a current wafer through a lens so as to acquire local positioning coordinates of a plurality of chips on the surface of the current wafer and position data among the chips, wherein the position data comprises row intervals and column intervals among the chips;
the calculation module is used for calculating reference spacing values corresponding to the chips according to the line spacing and the column spacing, and calculating lens parameters corresponding to the current lens according to the local positioning coordinates and the reference spacing values based on a preset algorithm, wherein the lens parameters comprise lens internal parameters and lens distortion parameters;
the second acquisition module is used for carrying out full-disc scanning on the wafer through the current lens so as to acquire the integral positioning coordinates of the chips on the surface of the current wafer, and eliminating distortion coordinates in the integral positioning coordinates according to the lens intrinsic parameters and the lens distortion parameters so as to generate corresponding linear positioning coordinates;
and the processing module is used for carrying out standardization processing on the linear positioning coordinate based on a preset single mapping matrix so as to generate a corresponding theoretical positioning coordinate, and replacing a theoretical chip coordinate value in the theoretical positioning coordinate with an actual chip coordinate value in the overall positioning coordinate.
In the chip positioning system, the calculation module is specifically configured to:
when the line spacing and the column spacing between a plurality of chips are obtained, screening out the maximum value and the minimum value in the line spacing and the column spacing, and calculating the average value corresponding to the remaining intermediate values of the line spacing and the column spacing so as to set the average value as the reference spacing value.
In the chip positioning system, the processing module is specifically configured to:
inputting theoretical positioning coordinates of a plurality of chips into a blank mapping matrix, and fitting the mapping matrix based on a RANSAC algorithm to generate a single mapping matrix;
and mapping the linear positioning coordinates onto a standard rectangular grid through the single mapping matrix to generate corresponding theoretical positioning coordinates.
In the chip positioning system, the processing module is specifically configured to:
calculating theoretical positioning coordinates on the image corresponding to the standard rectangular grid through the single mapping matrix, and comparing theoretical chip coordinate values in the theoretical positioning coordinates with actual chip coordinate values in the overall positioning coordinates to obtain positioning errors between the theoretical chip coordinate values and the actual chip coordinate values;
judging whether the positioning error between the theoretical chip coordinate value and the actual chip coordinate value corresponding to each chip is larger than a preset threshold value or not;
and replacing the theoretical chip coordinate value in the theoretical positioning coordinate with the actual chip coordinate value in the overall positioning coordinate if the positioning error between the theoretical chip coordinate value corresponding to the chip and the actual chip coordinate value is judged to be larger than a preset threshold.
In the chip positioning system, the processing module is further specifically configured to:
when the theoretical positioning coordinate is obtained, calculating a theoretical chip coordinate value in the theoretical positioning coordinate to the overall positioning coordinate in a reverse direction according to the lens intrinsic parameters and the lens distortion parameters, so as to replace the actual chip coordinate value with the theoretical chip coordinate value in the overall positioning coordinate.
A third aspect of the embodiments of the present invention provides a computer, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the chip positioning method as described above when executing the computer program.
A fourth aspect of the embodiments of the present invention provides a readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the chip positioning method as described above.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a flowchart of a chip positioning method according to a first embodiment of the invention;
fig. 2 is a partial schematic view of a wafer in a chip positioning method according to a second embodiment of the invention;
fig. 3 is a schematic diagram of eliminating distorted coordinates in overall positioning coordinates in a chip positioning method according to a second embodiment of the present invention;
fig. 4 is a block diagram of a chip positioning system according to a third embodiment of the present invention.
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Several embodiments of the invention are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Most of the prior art positions the LED chip by pattern edge matching and image similarity matching, however, due to the influence of factors such as external environment and equipment accuracy, the prior art has a certain deviation in positioning the LED chip, thereby reducing the yield of the product.
Referring to fig. 1, a chip positioning method according to a first embodiment of the present invention is shown, in which different wafers of a same product can be repeatedly scanned after lens parameters are first calculated, and meanwhile, a generated detection result is accurate and stable, a positioning deviation is eliminated, a yield of the product is improved, and the chip positioning method is suitable for wide popularization and use.
Specifically, the chip positioning method provided by this embodiment is applied to a wafer, where a plurality of chips are arranged on a surface of the wafer, and the method specifically includes the following steps:
step S10, locally scanning a current wafer through a lens to obtain local positioning coordinates of a plurality of chips on the surface of the current wafer and position data among the chips, wherein the position data comprises row intervals and column intervals among the chips;
first, in this embodiment, it should be noted that the chip positioning method provided in this embodiment is specifically applied to a wafer, and is used to position chips arranged on the surface of each wafer so as to facilitate subsequent production of the wafer.
Specifically, in this step, it should be noted that the chip positioning method provided in this embodiment is implemented based on a wafer positioning device, where a lens is installed on the wafer positioning device, and the lens is used for scanning a chip on a surface of a wafer.
Therefore, in this step, in order to improve the positioning accuracy of the chip on the surface of the wafer, the current wafer is pre-scanned in advance in this step, and specifically, in this step, the surface of the current wafer is locally scanned through the lens, that is, a partial region of the surface of the current wafer is scanned. Further, local positioning coordinates of a plurality of chips on the surface of the current wafer and position data between the plurality of chips can be acquired through local scanning, and specifically, the position data includes a row spacing and a column spacing between two adjacent chips.
Step S20, calculating reference spacing values corresponding to a plurality of chips according to the line spacing and the column spacing, and calculating lens parameters corresponding to the current lens according to the local positioning coordinates and the reference spacing values based on a preset algorithm, wherein the lens parameters comprise lens internal parameters and lens distortion parameters;
further, in this step, it should be noted that, after the data of the line spacing and the column spacing between the chips on the surface of the current wafer is obtained through the pre-scanning, the step correspondingly calculates the reference spacing values corresponding to the chips according to the current line spacing and the column spacing, and further, the step correspondingly calculates the lens parameters corresponding to the current lens according to a preset algorithm based on the obtained local positioning coordinates and the reference spacing values, specifically, the lens parameters include lens internal parameters and lens distortion parameters.
Step S30, full-disc scanning is carried out on the wafer through the current lens to obtain the integral positioning coordinates of a plurality of chips on the surface of the wafer, and the distortion coordinates in the integral positioning coordinates are eliminated according to the lens internal parameters and the lens distortion parameters to generate corresponding linear positioning coordinates;
specifically, in this step, after the lens internal parameters and the lens distortion parameters corresponding to the current lens are obtained through the pre-scanning, the current wafer is fully scanned through the lens again in this step, that is, all images of the surface of the current wafer are scanned, so as to correspondingly obtain the overall positioning coordinates corresponding to the chips on the surface of the current wafer.
Further, after the global positioning coordinates are acquired, the step may further eliminate the distorted coordinates appearing in the current global positioning coordinates according to the lens internal parameters and the lens distortion parameters acquired in the step S20, so as to generate corresponding linear positioning coordinates.
Step S40, standardizing the linear positioning coordinates based on a preset single mapping matrix to generate corresponding theoretical positioning coordinates, and replacing actual chip coordinate values in the overall positioning coordinates with theoretical chip coordinate values in the theoretical positioning coordinates.
Finally, in this step, it should be noted that, after the linear positioning coordinates corresponding to the plurality of chips are obtained, the linear positioning coordinates are further standardized based on the created single mapping matrix to generate corresponding theoretical positioning coordinates, and finally, the theoretical chip coordinate values in the theoretical positioning coordinates are only replaced by actual chip coordinate values in the overall positioning coordinates, so that the positioning of the plurality of chips can be simply and quickly completed.
When the wafer scanning device is used, a current wafer is firstly locally scanned through a lens to obtain local positioning coordinates of a plurality of chips on the surface of the current wafer and position data among the chips, then reference spacing values corresponding to the current chips are calculated according to the obtained position data, and further, lens parameters corresponding to the lens are calculated according to the position data and the reference spacing values. On the basis, the current wafer is scanned in a full-disc mode through the lens so as to correspondingly obtain integral positioning coordinates of the chips, distortion coordinates in the integral positioning coordinates are eliminated according to the lens parameters so as to generate corresponding linear positioning coordinates, and finally the generated linear positioning coordinates are standardized on the basis of a preset single mapping matrix so as to generate corresponding theoretical positioning coordinates, and actual chip coordinate values in the integral positioning coordinates are replaced by the theoretical chip coordinate values in the theoretical positioning coordinates, so that the chips on the surface of the current wafer can be simply and quickly positioned. By means of the method, different wafers of the same product can be scanned repeatedly after the lens parameters are calculated for the first time, meanwhile, the generated detection result is accurate and stable, positioning deviation is eliminated, the yield of the product is improved, and the method is suitable for large-scale popularization and use.
It should be noted that the above implementation process is only for illustrating the applicability of the present application, but this does not represent that the chip positioning method of the present application has only the above-mentioned one implementation flow, and on the contrary, the chip positioning method of the present application can be incorporated into the feasible embodiments of the present application as long as the chip positioning method of the present application can be implemented.
In summary, the chip positioning method provided by the embodiment of the invention can repeatedly scan different wafers of the same product after the lens parameters are calculated for the first time, and meanwhile, the generated detection result is accurate and stable, the positioning deviation is eliminated, the yield of the product is improved, and the chip positioning method is suitable for large-scale popularization and use.
A second embodiment of the present invention also provides a chip positioning method, where the chip positioning method provided in this embodiment specifically includes the following steps:
step S11, local scanning is carried out on the current wafer through a lens so as to obtain local positioning coordinates of a plurality of chips on the surface of the current wafer and position data among the chips;
similarly, in the present embodiment, it is preferable that the chip positioning method provided in the present embodiment is specifically applied to a wafer, and is used to position the chips arranged on the surface of each wafer, so as to facilitate subsequent production of the wafer.
Specifically, as shown in fig. 2, in this step, a current wafer is also pre-scanned in advance, specifically, under the condition of a determined chip product, a machine table, and an illumination light source, a plurality of pictures are pre-scanned on the current wafer, and local positioning coordinates of a plurality of chips on the surface of the current wafer and position data between the plurality of chips are correspondingly obtained according to the plurality of scanned pictures, specifically, the position data includes a row spacing and a column spacing between two adjacent chips.
Step S21, when the row spacing and the column spacing between the chips are obtained, a maximum value and a minimum value in the row spacing and the column spacing are screened out, and an average value corresponding to remaining intermediate values in the row spacing and the column spacing is calculated, so as to set the average value as the reference spacing value.
Further, in this step, it should be noted that, after the row spacing and the column spacing between the chips are obtained in the above step S11, it can be understood that the currently obtained row spacing and column spacing are a series of specific numerical values, and the sizes thereof are different. Therefore, in this step, in order to improve the accuracy of positioning, the maximum value and the minimum value among the values of the current row spacing and the current column spacing are selected, that is, a plurality of large values and a plurality of small values are selected to extract a plurality of intermediate values.
Further, a corresponding average value is calculated based on the screened intermediate values, and the average value is set as a reference pitch value.
Step S31, calculating the lens parameters corresponding to the current lens according to the local positioning coordinates and the reference spacing value based on a preset algorithm;
specifically, in this step, after the local positioning coordinates and the reference distance values of the current chips are obtained, the step calculates corresponding lens parameters according to the local positioning coordinates and the reference distance values by a preset correction method, specifically, the lens parameters include lens internal parameters and lens distortion parameters.
It should be noted that, in this step, the internal reference matrix and the external reference matrix are first solvedWhen the product fixes the world coordinate system on the checkerboard, the physical coordinate Z of any point on the checkerboard is 0, and therefore, the imaging model without distortion of the original single point can be expressed as the following expression. Wherein R is 1 And R 2 To rotate the first two columns of matrix R, the internal reference matrix is denoted as a for simplicity, i.e.:
the above equation is explained in some detail.
For different pictures, the internal reference matrix A is a constant value;
for the same picture, the internal reference matrix A and the external reference matrix (R) 1 ，R 2 T) is a constant value;
for a single point on the same picture, the internal reference matrix A and the external reference matrix (R) 1 ，R 2 T), the scaling factor Z ZZ is constant. A (R) 1 ，R 2 T) is recorded as a matrix H, H is the product of the internal reference matrix and the external reference matrix, and three columns of the matrix H are recorded as (H) 1 ，H 2 ，H 3 ) Then, there are:
using the above formula, eliminating the scale factor Z, one obtains:
at this time, the scale factor Z has been eliminated, and thus the above equation holds for all corner points on the same picture. And (U, V) are coordinates of the calibration plate corner point in the pixel coordinate system, and (U, V) are coordinates of the calibration plate corner point in the world coordinate system. Through an image recognition algorithm, pixel coordinates (U, V) of the corner points of the calibration plate can be obtained, and because the world coordinate system of the calibration plate is artificially defined, the size of each grid on the calibration plate is known, and (U, V) under the world coordinate system can be obtained through calculation.
Where H is a homogeneous matrix with 8 independent unknown elements. Each calibration plate corner point can provide a corresponding relation of two constraint equations (U, V), and a corresponding relation of U, V provides two constraint equations), so that when the number of calibration plate corner points on a picture is equal to 4, a matrix H corresponding to the picture can be obtained.
And when the number of the corner points of the calibration board on one picture is more than 4, regressing the optimal matrix H by using a least square method.
At this time, if the H matrix is known, the internal reference matrix is further solved:
the matrix H ═ a (R) is known 1 ，R 2 T), then the camera's internal reference matrix a needs to be solved.
Then matrix a is used to represent matrix B:
at this point, we only need to solve the vector B to obtain the matrix B. Each calibration board picture may provide a constraint relationship with vb ═ 0, which contains two constraint equations. However, vector b has 6 unknown elements. Thus, the two constraint equations provided by a single picture are not sufficient to solve for the vector b. Therefore, we can solve the vector b by taking 3 calibration plate photos and obtaining 3 constraint relations of vb equal to 0, namely 6 equations. When the number of calibration plate pictures is more than 3 (in fact, 15 to 20 calibration plate pictures are generally needed), least square fitting can be adopted to obtain the optimal vector B, and the matrix B is obtained. (B is only related to internal reference)
And solving the external parameter matrix.
It should be noted that, for the same camera, the internal reference matrix of the camera depends on the internal parameters of the camera, and the internal reference matrix of the camera is not changed no matter what the positional relationship between the calibration board and the camera is. This is why the camera internal reference matrix a can be solved together by using the matrix H obtained from different pictures (different positional relationships between the calibration board and the camera) in the "solving the internal reference matrix".
However, the external reference matrix reflects the positional relationship of the calibration plate and the camera. The position relation between the calibration board and the camera is changed for different pictures, and the external reference matrix corresponding to each picture is different at the moment.
Finally, calibrating the distortion parameters of the camera, and obtaining the distortion parameters through the steps:
so that ideal, distortion-free pixel coordinates (u, v) can be obtained.
Step S41, full-disc scanning is carried out on the wafer through the current lens to obtain the integral positioning coordinates of a plurality of chips on the surface of the wafer, and the distortion coordinates in the integral positioning coordinates are eliminated according to the lens internal parameters and the lens distortion parameters to generate corresponding linear positioning coordinates;
further, in this step, it should be noted that, after the lens internal parameters and the lens distortion parameters corresponding to the current lens are obtained through the pre-scanning, the step may perform full-disc scanning on the current wafer through the lens again, that is, scan all images of the surface of the current wafer, so as to correspondingly obtain the overall positioning coordinates corresponding to the chips on the surface of the current wafer.
Further, in this step, after the global positioning coordinates are acquired, it is understood that the global positioning coordinates include a series of coordinate values corresponding to the positions of each chip, wherein the magnitude of each coordinate value may also be different, so that this step may eliminate the distorted coordinates in the current global positioning coordinates through the lens internal reference and the lens distortion parameter acquired in the above step S31, i.e. correct the distorted coordinates, and it is understood that, as shown in fig. 3, the "arc" relationship between the coordinate positions of two adjacent chips is converted into the "straight line" relationship, so that the corresponding linear positioning coordinates can be generated.
Step S51, inputting the theoretical positioning coordinates of a plurality of chips into a blank mapping matrix, and fitting the mapping matrix based on RANSAC algorithm to generate the single mapping matrix; and mapping the linear positioning coordinates onto a standard rectangular grid through the single mapping matrix to generate corresponding theoretical positioning coordinates.
Specifically, in this step, it should be noted that a blank mapping matrix is created in advance, and further, theoretical positioning coordinates of the chips are input into the current blank mapping matrix, and the current mapping matrix is fitted through the RANSAC algorithm to generate a corresponding single mapping matrix.
On the basis, the linear positioning coordinates are mapped to the standard rectangular grid through the calculated single mapping matrix so as to finally generate corresponding theoretical positioning coordinates.
Wherein, the expression of the mapping matrix is:
wherein ∈ indicates that the symbol is proportional to, and the final calculation formula of the single mapping matrix is:
wherein the homography matrix H ba The method comprises two-phase machine rotation and translation information (R, t), a two-phase machine parameter matrix K and plane parameters (n, d).
Step S61, calculating theoretical positioning coordinates on the image corresponding to the standard rectangular grid through the single mapping matrix, and comparing theoretical chip coordinate values in the theoretical positioning coordinates with actual chip coordinate values in the overall positioning coordinates to obtain positioning errors between the theoretical chip coordinate values and the actual chip coordinate values; judging whether the positioning error between the theoretical chip coordinate value and the actual chip coordinate value corresponding to each chip is larger than a preset threshold value or not; and replacing the theoretical chip coordinate value in the theoretical positioning coordinate with the actual chip coordinate value in the overall positioning coordinate if the positioning error between the theoretical chip coordinate value corresponding to the chip and the actual chip coordinate value is judged to be larger than a preset threshold.
Furthermore, in this step, it should be noted that, after the theoretical positioning coordinates on the image corresponding to the standard rectangular grid are calculated through the single mapping matrix, the step also compares the theoretical chip coordinate values in the current theoretical positioning coordinates with the actual chip coordinate values in the overall positioning coordinates, that is, calculates a difference between the theoretical chip coordinate values and the actual chip coordinate values, so as to correspondingly obtain a positioning error between each theoretical chip coordinate value and each actual chip coordinate value.
Further, whether the positioning error between the theoretical chip coordinate value and the actual chip coordinate value corresponding to each chip is larger than a preset threshold value, for example, whether the positioning error is larger than 0.1 pixel is judged; specifically, if it is determined that the positioning error between the theoretical chip coordinate value and the actual chip coordinate value corresponding to the chip is greater than the preset threshold, the theoretical chip coordinate value in the current theoretical positioning coordinate is replaced with the actual chip coordinate value in the current overall positioning coordinate.
Step S71, when the theoretical positioning coordinate is obtained, calculating a theoretical chip coordinate value in the theoretical positioning coordinate back to the overall positioning coordinate according to the lens intrinsic parameters and the lens distortion parameters, so as to replace the actual chip coordinate value with the theoretical chip coordinate value in the overall positioning coordinate.
Finally, in this step, it should be noted that after the theoretical positioning coordinates are obtained, the theoretical chip coordinate values in the current theoretical positioning coordinates are calculated in a reverse direction into the overall positioning coordinates according to the lens intrinsic parameters and the lens distortion parameters obtained in the above step, so as to replace the current actual chip coordinate values with the theoretical chip coordinate values in the overall positioning coordinates, thereby simply and quickly completing the positioning of the chips on the current wafer surface.
It should be noted that the method provided by the second embodiment of the present invention, which implements the same principle and produces some technical effects as the first embodiment, can be referred to the first embodiment for providing corresponding contents for the sake of brief description, where this embodiment is not mentioned.
In summary, the chip positioning method provided by the embodiments of the present invention can repeatedly scan different wafers of the same product after the lens parameters are calculated for the first time, and meanwhile, the generated detection result is accurate and stable, the positioning deviation is eliminated, the yield of the product is improved, and the method is suitable for wide popularization and use.
Referring to fig. 4, a chip positioning system according to a third embodiment of the present invention is applied to a wafer, wherein a plurality of chips are arranged on a surface of the wafer, and the system includes:
the first obtaining module 12 is configured to obtain a detection image of a current wafer through a lens to obtain local positioning coordinates of a plurality of chips on a surface of the current wafer and position data among the plurality of chips, where the position data includes a row pitch and a column pitch among the plurality of chips;
a calculating module 22, configured to calculate reference distance values corresponding to the chips according to the line distances and the column distances, and calculate lens parameters corresponding to the current lens according to the local positioning coordinates and the reference distance values based on a preset algorithm, where the lens parameters include lens intrinsic parameters and lens distortion parameters;
a second obtaining module 32, configured to perform full-scan scanning on the wafer through the current lens to obtain an overall positioning coordinate of the chips on the surface of the wafer, and eliminate a distortion coordinate in the overall positioning coordinate according to the lens intrinsic parameter and the lens distortion parameter to generate a corresponding linear positioning coordinate;
and the processing module 42 is configured to perform standardization processing on the linear positioning coordinate based on a preset single mapping matrix to generate a corresponding theoretical positioning coordinate, and replace a theoretical chip coordinate value in the theoretical positioning coordinate with an actual chip coordinate value in the overall positioning coordinate.
In the chip positioning system, the calculation module 22 is specifically configured to:
when the line spacing and the column spacing between a plurality of chips are obtained, screening out the maximum value and the minimum value in the line spacing and the column spacing, and calculating the average value corresponding to the remaining intermediate values of the line spacing and the column spacing so as to set the average value as the reference spacing value.
In the chip positioning system, the processing module 42 is specifically configured to:
inputting theoretical positioning coordinates of a plurality of chips into a blank mapping matrix, and fitting the mapping matrix based on a RANSAC algorithm to generate a single mapping matrix;
and mapping the linear positioning coordinate to a standard rectangular grid through the single mapping matrix so as to generate a corresponding theoretical positioning coordinate.
In the chip positioning system, the processing module 42 is specifically configured to:
calculating theoretical positioning coordinates on the image corresponding to the standard rectangular grid through the single mapping matrix, and comparing theoretical chip coordinate values in the theoretical positioning coordinates with actual chip coordinate values in the overall positioning coordinates to obtain positioning errors between the theoretical chip coordinate values and the actual chip coordinate values;
judging whether the positioning error between the theoretical chip coordinate value and the actual chip coordinate value corresponding to each chip is larger than a preset threshold value or not;
and replacing the theoretical chip coordinate value in the theoretical positioning coordinate with the actual chip coordinate value in the overall positioning coordinate if the positioning error between the theoretical chip coordinate value corresponding to the chip and the actual chip coordinate value is judged to be larger than a preset threshold.
In the chip positioning system, the processing module 42 is further specifically configured to:
when the theoretical positioning coordinate is obtained, calculating a theoretical chip coordinate value in the theoretical positioning coordinate to the overall positioning coordinate in a reverse direction according to the lens intrinsic parameters and the lens distortion parameters, so as to replace the actual chip coordinate value with the theoretical chip coordinate value in the overall positioning coordinate.
A fourth embodiment of the present invention provides a computer, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor executes the computer program to implement the chip positioning method according to the first embodiment or the second embodiment.
A fifth embodiment of the present invention provides a readable storage medium, on which a computer program is stored, which when executed by a processor, implements the chip positioning method provided in the first or second embodiment described above.
In summary, the chip positioning method, the system, the computer and the readable storage medium provided by the embodiments of the present invention can repeatedly scan different wafers of the same product after the lens parameters are calculated for the first time, and meanwhile, the generated detection result is accurate and stable, the positioning deviation is eliminated, the yield of the product is improved, and the method and the system are suitable for wide popularization and use.
The above modules may be functional modules or program modules, and may be implemented by software or hardware. For a module implemented by hardware, the above modules may be located in the same processor; or the modules can be respectively positioned in different processors in any combination.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent should be subject to the appended claims.
Claims (10)
1. A chip positioning method is applied to a wafer, wherein a plurality of chips are arranged on the surface of the wafer, and the method comprises the following steps:
the method comprises the steps that a current wafer is locally scanned through a lens to obtain local positioning coordinates of a plurality of chips on the surface of the current wafer and position data among the chips, wherein the position data comprise line intervals and column intervals among the chips;
calculating reference distance values corresponding to a plurality of chips according to the line distances and the column distances, and calculating lens parameters corresponding to the current lens according to the local positioning coordinates and the reference distance values based on a preset algorithm, wherein the lens parameters comprise lens internal parameters and lens distortion parameters;
carrying out full-disc scanning on the wafer through the current lens to obtain integral positioning coordinates of a plurality of chips on the surface of the wafer, and eliminating distortion coordinates in the integral positioning coordinates according to the lens internal parameters and the lens distortion parameters to generate corresponding linear positioning coordinates;
and carrying out standardization processing on the linear positioning coordinate based on a preset single mapping matrix to generate a corresponding theoretical positioning coordinate, and replacing a theoretical chip coordinate value in the theoretical positioning coordinate with an actual chip coordinate value in the overall positioning coordinate.
2. The chip positioning method according to claim 1, wherein: the step of calculating the reference spacing values corresponding to the plurality of chips according to the row spacing and the column spacing comprises the following steps:
when the line spacing and the column spacing between a plurality of chips are obtained, screening out the maximum value and the minimum value in the line spacing and the column spacing, and calculating the average value corresponding to the remaining intermediate values of the line spacing and the column spacing so as to set the average value as the reference spacing value.
3. The chip positioning method according to claim 1, wherein: the step of normalizing the linear positioning coordinates based on a preset single mapping matrix to generate corresponding theoretical positioning coordinates comprises:
inputting theoretical positioning coordinates of a plurality of chips into a blank mapping matrix, and fitting the mapping matrix based on a RANSAC algorithm to generate a single mapping matrix;
and mapping the linear positioning coordinates onto a standard rectangular grid through the single mapping matrix to generate corresponding theoretical positioning coordinates.
4. The chip positioning method according to claim 3, wherein: the step of replacing the theoretical chip coordinate value in the theoretical positioning coordinate with the actual chip coordinate value in the overall positioning coordinate comprises:
calculating theoretical positioning coordinates on the image corresponding to the standard rectangular grid through the single mapping matrix, and comparing theoretical chip coordinate values in the theoretical positioning coordinates with actual chip coordinate values in the overall positioning coordinates to obtain positioning errors between the theoretical chip coordinate values and the actual chip coordinate values;
judging whether the positioning error between the theoretical chip coordinate value and the actual chip coordinate value corresponding to each chip is larger than a preset threshold value or not;
and replacing the theoretical chip coordinate value in the theoretical positioning coordinate with the actual chip coordinate value in the overall positioning coordinate if the positioning error between the theoretical chip coordinate value corresponding to the chip and the actual chip coordinate value is judged to be larger than a preset threshold.
5. The chip positioning method according to claim 1, wherein: the step of replacing the theoretical chip coordinate value in the theoretical positioning coordinate with the actual chip coordinate value in the overall positioning coordinate further includes:
when the theoretical positioning coordinate is obtained, calculating a theoretical chip coordinate value in the theoretical positioning coordinate to the overall positioning coordinate in a reverse direction according to the lens intrinsic parameters and the lens distortion parameters, so as to replace the actual chip coordinate value with the theoretical chip coordinate value in the overall positioning coordinate.
6. A chip positioning system is applied to a wafer, wherein a plurality of chips are arranged on the surface of the wafer, and the system comprises:
the first acquisition module is used for acquiring a detection image of a current wafer through a lens so as to acquire local positioning coordinates of a plurality of chips on the surface of the current wafer and position data among the chips, wherein the position data comprises row intervals and column intervals among the chips;
the calculation module is used for calculating reference spacing values corresponding to the chips according to the line spacing and the column spacing, and calculating lens parameters corresponding to the current lens according to the local positioning coordinates and the reference spacing values based on a preset algorithm, wherein the lens parameters comprise lens internal parameters and lens distortion parameters;
the second acquisition module is used for carrying out full-disc scanning on the wafer through the current lens so as to acquire the integral positioning coordinates of a plurality of chips on the surface of the wafer, and eliminating distortion coordinates in the integral positioning coordinates according to the lens intrinsic parameters and the lens distortion parameters so as to generate corresponding linear positioning coordinates;
and the processing module is used for carrying out standardization processing on the linear positioning coordinate based on a preset single mapping matrix so as to generate a corresponding theoretical positioning coordinate, and replacing a theoretical chip coordinate value in the theoretical positioning coordinate with an actual chip coordinate value in the overall positioning coordinate.
7. The chip positioning system according to claim 6, wherein: the calculation module is specifically configured to:
when the line spacing and the column spacing between a plurality of chips are obtained, screening out the maximum value and the minimum value in the line spacing and the column spacing, and calculating the average value corresponding to the remaining intermediate values of the line spacing and the column spacing so as to set the average value as the reference spacing value.
8. The chip positioning system according to claim 6, wherein: the processing module is specifically configured to:
inputting theoretical positioning coordinates of a plurality of chips into a blank mapping matrix, and fitting the mapping matrix based on a RANSAC algorithm to generate a single mapping matrix;
and mapping the linear positioning coordinates onto a standard rectangular grid through the single mapping matrix to generate corresponding theoretical positioning coordinates.
9. A computer comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the chip positioning method according to any one of claims 1 to 5 when executing the computer program.
10. A readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the chip positioning method according to any one of claims 1 to 5.
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