CN114968373A - Instruction dispatching method and device, electronic equipment and computer readable storage medium - Google Patents
Instruction dispatching method and device, electronic equipment and computer readable storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides an instruction dispatching method, an instruction dispatching device, electronic equipment and a computer readable storage medium; the instruction dispatching method comprises the following steps: setting an instruction dispatch cache; when the instruction transmitting queue is not free, storing the instruction to be dispatched to the instruction dispatching cache; in response to the instruction issue queue being free, dispatching the instruction to be dispatched in the instruction dispatch cache to the instruction issue queue. By the method and the device, the efficiency of dispatching the instructions can be improved, and the performance of the processor is further improved.
Description
Technical Field
The present application relates to computer architecture technologies, and in particular, to an instruction dispatching method, an instruction dispatching apparatus, an electronic device, and a computer-readable storage medium.
Background
An out-of-order issue queue is an important component of a high performance processor, and is part of an out-of-order instruction window, and the depth of the out-of-order issue queue has an important impact on the performance, frequency, and power consumption of the processor. In the prior art, when one of the out-of-order issue queues is full, an instruction cannot be dispatched to the issue queue. If the instruction cannot be dispatched to the issue queue, it will cause the front-end pipeline to stall altogether, affecting the performance of the processor. Therefore, it is a continuing goal in the processor art to improve the performance of processors by improving the efficiency with which instructions are dispatched.
Disclosure of Invention
The embodiment of the application provides an instruction dispatching method, an instruction dispatching device, electronic equipment and a computer readable storage medium, which can improve the efficiency of dispatching instructions and further improve the performance of a processor.
The technical scheme of the embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides an instruction dispatching method, including:
setting an instruction dispatch cache;
when the instruction transmitting queue is not free, storing the instruction to be dispatched to the instruction dispatching cache;
in response to the instruction issue queue being free, dispatching the instruction to be dispatched in the instruction dispatch cache to the instruction issue queue.
In some optional embodiments, said dispatching the instruction to be dispatched in the instruction dispatch cache to the instruction issue queue in response to the instruction issue queue being free comprises:
and dispatching the instructions to be dispatched in the instruction dispatch cache to the instruction emission queue according to the storage sequence of the instructions in the instruction dispatch cache.
In some optional embodiments, the instruction dispatch cache comprises at least one sub-instruction dispatch cache, each sub-instruction dispatch cache for storing at least one type of instruction, any two sub-instruction dispatch caches storing instructions of different types.
Said dispatching to-be-dispatched instructions in said instruction dispatch cache to said instruction issue queue in response to said instruction issue queue being free comprises:
when a first instruction transmitting queue corresponding to a first type of instruction is idle, allocating an instruction to be allocated in a first sub-instruction allocation cache to the first instruction transmitting queue;
wherein the first sub-instruction dispatch cache is to store at least the first type of instruction.
In some optional embodiments, said dispatching the instruction to be dispatched in the first sub-instruction dispatch cache to the first instruction issue queue comprises:
and dispatching the instructions to be dispatched in the first sub-instruction dispatch cache to the first instruction transmitting queue according to the storage sequence of the instructions in the first sub-instruction dispatch cache.
In some optional embodiments, said dispatching the instructions to be dispatched in said first sub-instruction dispatch cache to said first instruction issue queue in the order in which the instructions in said first sub-instruction dispatch cache are stored comprises:
and dispatching the instruction to be dispatched which is stored in the first sub-instruction dispatch cache firstly to the first instruction transmitting queue.
In some optional embodiments, the instruction dispatch cache is to store all types of instructions, the all types of instructions corresponding to one instruction issue queue.
In a second aspect, an embodiment of the present application provides an instruction dispatching apparatus, including:
a setting unit for setting an instruction dispatch cache;
the processing unit is used for storing the instruction to be dispatched to the instruction dispatching cache when the instruction transmitting queue is not free;
and the dispatching unit is used for responding to the instruction transmitting queue being free and dispatching the instruction to be dispatched in the instruction dispatching cache to the instruction transmitting queue.
In some optional embodiments, the dispatch unit is configured to dispatch the instructions to be dispatched in the instruction dispatch cache to the instruction issue queue according to a storage order of the instructions in the instruction dispatch cache.
In some optional embodiments, the instruction dispatch cache comprises at least one sub-instruction dispatch cache, each sub-instruction dispatch cache for storing at least one type of instruction, any two sub-instruction dispatch caches storing instructions of different types.
In some optional embodiments, the dispatch unit is configured to, when a first instruction issue queue corresponding to the first type of instruction is free, dispatch an instruction to be dispatched in the first sub-instruction dispatch cache to the first instruction issue queue;
wherein the first sub-instruction dispatch cache is to store at least the first type of instruction.
In some optional embodiments, the dispatch unit is configured to dispatch the to-be-dispatched instructions in the first sub-instruction dispatch cache to the first instruction issue queue according to a storage order of the instructions in the first sub-instruction dispatch cache.
In some optional embodiments, the dispatch unit is configured to dispatch the instruction to be dispatched that is first stored in the first sub-instruction dispatch cache to the first instruction issue queue.
In some alternative embodiments, the instruction dispatch cache is configured to store all types of instructions, the all types of instructions corresponding to an instruction issue queue.
In a third aspect, an embodiment of the present application provides an electronic device, including:
a processor, a memory, and a bus;
the memory stores executable instructions;
the processor and the memory are communicated through the bus, and when the processor executes the executable instructions stored in the memory, the instruction dispatching method is realized.
In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores executable instructions and is configured to, when executed by a processor, implement the instruction dispatching method provided in the embodiment of the present application.
In a fifth aspect, the present application provides a computer program product, wherein the computer program product includes computer programs/instructions, and when the computer programs/instructions are executed by a processor, the instruction dispatching method described above is implemented.
The instruction dispatching method provided by the embodiment of the application comprises the following steps: setting an instruction dispatch cache; when the instruction transmitting queue is not free, storing the instruction to be dispatched to the instruction dispatching cache; in response to the instruction issue queue being free, dispatching the instruction to be dispatched in the instruction dispatch cache to the instruction issue queue. By additionally arranging the instruction dispatching cache, the instruction to be dispatched to the full instruction transmitting queue can be stored in the instruction dispatching cache, so that instruction blockage is avoided; and the front-end pipeline stop caused by instruction blocking is avoided, and the instruction dispatching efficiency and the processor performance are improved. In addition, instruction blocking can cause uneven utilization of an instruction transmitting queue, thereby causing resource waste; this application can promote resource utilization through avoiding the instruction to block up.
Drawings
FIG. 1 is a schematic diagram illustrating an instruction processing flow in the related art;
FIG. 2 is a flowchart illustrating a process for dispatching instructions to a queue according to an embodiment of the present disclosure;
FIG. 3 is a flow diagram illustrating an alternative process for dispatching instructions to a queue according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of yet another process flow for dispatching instructions to a queue according to an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating an alternative process flow of an instruction dispatching method according to an embodiment of the present application;
FIG. 6 is a schematic diagram of yet another process flow for dispatching instructions to a queue according to an embodiment of the present application;
FIG. 7 is a block diagram of an exemplary embodiment of an instruction dispatch device;
fig. 8 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.
Detailed Description
In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be described in further detail with reference to the attached drawings, the described embodiments should not be considered as limiting the present application, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.
In the following description, references to the terms "first", "second", and the like, are only to distinguish similar objects and do not denote a particular order, but rather the terms "first", "second", and the like may be used interchangeably with the order specified, where permissible, to enable embodiments of the present application described herein to be practiced otherwise than as specifically illustrated or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.
It should be understood that, in the various embodiments of the present application, the size of the serial number of each implementation process does not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
Before further detailed description of the embodiments of the present application, terms and expressions referred to in the embodiments of the present application will be described, and the terms and expressions referred to in the embodiments of the present application will be used for the following explanation.
1) Assembly line: the method is an implementation technology for executing a plurality of instructions in an overlapping way, each step in a pipeline finishes one part of the instructions, each step is called as a pipeline stage or a pipeline section, and the pipeline stages are connected in front and back to form the pipeline; instructions enter at one end of the pipeline and exit at the other end of the pipeline through these pipeline stages.
2) Instructions for: an instruction is stored in memory in binary code, and includes an opcode that determines the operation to be performed and an operand that includes the data to be used in the operation and the address of the location of the data.
3) A functional unit: for executing instructions, may include a main integer unit, floating point and integer multipliers, floating point adders, floating point and integer dividers; wherein the main integer Unit is used for processing load and store, integer Arithmetic Logic Unit (ALU) operation and branch; the floating-point adder handles floating-point addition, subtraction and conversion.
4) Cache (Cache): the memory is a high-speed memory which can perform high-speed data exchange, and the access speed of a cache is faster than that of a general random access memory.
In the related art, the instruction processing flow is schematically illustrated, and as shown in fig. 1, a life cycle of an instruction in a pipeline includes: fetching, decoding, executing, accessing and writing back. Instruction fetching refers to a process of reading an instruction from a memory. Instruction decoding refers to a process of translating an instruction fetched from a memory, and after decoding, an operand Register index required by the instruction is obtained, and the operand Register index can be read from a general Register File (Register File) by using the operand Register index. The type of computation to be performed after Instruction decode is known and the required operands have been read from the general purpose register set, then Instruction execution (Instruction execution) follows. Instruction execution refers to the process of actually operating on an instruction. For example, if the instruction is an add operation instruction, the operand is added; if the instruction is a subtraction operation, the operand is subtracted. The most common component in the "execute" stage is the ALU, which is a hardware functional unit that implements specific operations. Memory access refers to the process by which memory access instructions read data from memory or write data to memory. Write-back refers to the process of writing back the result of instruction execution to the general register set, if it is a normal operation instruction, the result value comes from the result of the 'execution' stage calculation; in the case of a memory read command, the result is data read from memory during the "access" phase.
Based on the instruction processing flow shown in fig. 1, after the instruction is decoded, before entering the execution stage, the instruction needs to be dispatched to the instruction issue queues corresponding to different functional units, and then the instruction meeting the issue condition is dispatched from the instruction issue queue corresponding to the functional unit and is issued to the functional unit, so that the functional unit executes the instruction.
A process flow diagram for dispatching instructions to an instruction issue queue, as shown in FIG. 2, a processor includes a centralized issue queue to which all types of instructions are dispatched; and transmitting the instructions in the centralized transmission queue to different functional units according to the types of the instructions. Each item of the centralized transmission queue may include any type of instruction, so that it is necessary to ensure, on the field setting of the queue item, an instruction with the most requirements for storing operands and control information, which results in a situation that some fields are idle when storing a simpler instruction, and a problem of resource waste exists.
Another process flow diagram for dispatching instructions to an instruction issue queue is shown in FIG. 3, where a processor includes multiple distributed issue queues, each of which can hold only one type of instruction, and each of which can issue instructions to only one functional unit. Because each distributed transmission queue only stores one type of instruction, the field setting of the queue entry only needs to ensure the requirement of storing the operand and control information of one type of instruction, so that the distributed transmission queue has smaller area, shallower depth and better time sequence; however, because of the strong dynamics of the instruction type distribution, it often happens that some distributed transmission queue is full, and other transmission queues are idle; the instruction dispatching is sequential, and the instruction dispatching is suspended as long as one distributed transmission queue is full, which causes that other distributed transmission queues with idle items cannot receive the instruction dispatching, and the problem of resource waste is caused.
Yet another process flow diagram for dispatching instructions to queues, as shown in FIG. 4, a processor includes a plurality of distributed issue queues, each of which may hold a plurality of different types of instructions, and each of which may issue instructions to a plurality of functional units. Although the scheme solves the problem of resource waste caused by that the distributed transmission queue with idle entries cannot obtain instruction assignment in the processing flow of assigning instructions to the queues shown in fig. 3, the waste of fields in the queue entries is increased, the queue depth is increased, and the time sequence of the queues is poor.
As shown in table 1 below, the queue entries of the out-of-order transmission queue include: a Global Identifier (GID) of the instruction, instruction control information, source operand control information, and a destination register. Wherein, the GID is used for identifying an instruction in the whole processor core; the instruction control information includes operation type, instruction delay, functional unit pipeline, etc.; the source operand control information includes a register number, a ready flag, and a functional unit that generates the data, etc.; the destination register is used for recording the destination register number of the instruction.
TABLE 1 structural schematic diagram of queue entries of out-of-order issue queue
| GID | Command control information | Source operand 0 control information | … | Source operand N control information | Destination register 1 | … | Destination register M |
In the related art, when any one of the instruction issue queues is full or any one of the instruction issue queues is not idle, and subsequently generated instructions to be issued need to be dispatched to the instruction issue queue which is not idle (or full), the front-end pipeline needs to suspend processing completely; as such, the performance of the processor may be reduced.
An optional processing flow of the instruction dispatching method provided in the embodiment of the present application, as shown in fig. 5, at least includes the following steps:
in step S101, an instruction dispatch cache is set.
In some embodiments, a cache may be divided from an existing cache of the processor, and the divided cache is used as an instruction dispatch cache; a new cache may also be provided in the processor as an instruction dispatch cache.
In some embodiments, for the distributed issue queue shown in FIG. 3 or FIG. 4, the instruction dispatch cache may include at least one sub-instruction dispatch cache, each sub-instruction dispatch cache for storing at least one type of instruction, where the types of instructions stored by any two sub-instruction dispatch caches are not identical. The types of the instructions stored in any two sub-instruction dispatch caches are not completely the same, and may be completely different; or the type of the instructions stored by the two sub-instruction dispatch caches is partly the same, and the type of the instructions stored by the two sub-instruction dispatch caches is partly different. The difference in instruction types may include: the number of destination registers, the number of source registers, whether an immediate operand is provided, the bit width of the immediate operand, the bit width of instruction control information and the sequence requirements among instructions.
For the centralized issue queue shown in FIG. 2, the instruction dispatch cache is used to store all types of instructions, which correspond to one instruction issue queue.
In some embodiments, the existing Cache of the processor may be a first level Cache (L1 Cache) or a second level Cache (L2 Cache). The L1 Cache is a first-level Cache of a Central Processing Unit (CPU), and the L2 Cache is a second-level Cache of the CPU.
Step S102, when the instruction transmitting queue is not free, storing the instruction to be dispatched to the instruction dispatching cache.
In some embodiments, the instruction to be dispatched may be an instruction that, after being decoded, requires entry prior to the instruction execution stage. And dispatching the instruction to be dispatched to the corresponding instruction emission queue according to the functional unit executing the instruction to be dispatched. In specific implementation, each functional unit corresponds to one instruction issue queue, and different functional units may correspond to the same instruction issue queue. If the instruction transmitting queue corresponding to the functional unit executing the instruction to be dispatched is not idle, the instruction to be dispatched is stored to the instruction dispatching cache. Therefore, the instruction blocking generated when the instruction is dispatched can be avoided, so that the front-end pipeline can continuously run without interruption or stop, and the efficiency of dispatching the instruction and the performance of the processor are further improved.
Step S103, responding to the instruction transmitting queue being free, the instruction to be dispatched in the instruction dispatching cache is dispatched to the instruction transmitting queue.
In some embodiments, if an instruction in the full instruction issue queue is issued to a functional unit, the instruction issue queue may be free; in this scenario, instructions to be dispatched in the instruction dispatch cache may be dispatched to the instruction issue queue.
In a specific implementation, if the instruction issue queue is free, the instructions to be dispatched in the instruction dispatch cache may be dispatched to the instruction issue queue according to a storage order of the instructions in the instruction dispatch cache. For example, an instruction stored first in an instruction dispatch buffer is dispatched first to an idle instruction issue queue corresponding to the type of the instruction, following a first in first out principle.
In some optional embodiments, for the distributed issue queue shown in fig. 3 or fig. 4, the instruction dispatch cache includes at least a first sub-instruction dispatch cache, and only the first type of instruction may be stored in the first sub-instruction dispatch cache, or the first type of instruction and other types of instructions except the first type may be stored in the first sub-instruction dispatch cache; when a first instruction transmitting queue corresponding to the first type of instruction is free, the instruction to be dispatched in the first sub-instruction dispatching cache is dispatched to the first instruction transmitting queue. Specifically, the instructions to be dispatched in the first sub-instruction dispatch cache may be dispatched to the first instruction issue queue according to a storage order of the instructions in the first sub-instruction dispatch cache; if so, the instruction to be dispatched which is stored in the first sub-instruction dispatch cache first is dispatched to the first instruction issue queue.
As an example, only the first type of instruction is stored in the first sub-instruction dispatch cache, and if the first instruction issue queue is switched from not free to free, the first type of instruction stored in the first sub-instruction dispatch cache is dispatched to the first sub-instruction dispatch cache.
As another example, a first sub-instruction dispatch cache stores a first type of instruction and a second type of instruction, and a first instruction issue queue stores the first type of instruction and the second type of instruction; and if the first instruction transmitting queue is switched from being idle to being idle, determining the instruction to be dispatched, which is firstly stored into the first sub-instruction dispatching cache, in the first type of instruction and the second type of instruction, and dispatching the instruction to be dispatched, which is firstly stored into the first sub-instruction dispatching cache, to the first instruction transmitting queue. In this scenario, the instruction to be dispatched that is first stored in the first sub-instruction dispatch store may be a first type of instruction or a second type of instruction.
In other alternative embodiments, for the centralized issue queue shown in FIG. 2, the instruction dispatch cache is used to store all types of instructions, which correspond to one instruction issue queue. For example, if the instruction issue queue is switched from not being free to being free, the instruction to be dispatched, which is stored first, of all types of instructions in the instruction dispatch cache is determined, and the instruction to be dispatched, which is stored first, is dispatched to the instruction issue queue.
In yet other embodiments, as shown in FIG. 6, one type of instruction may be stored in at least two instruction issue queues, a first type of instruction corresponding to functional unit 1 may be stored in instruction dispatch queue 1 and instruction dispatch queue 2, a second type of instruction corresponding to functional unit 2 may be stored in instruction dispatch queue X and instruction dispatch queue 2, an N-1 type of instruction corresponding to functional unit N-1 may be stored in instruction dispatch queue N-1 and instruction dispatch queue Q, and an N type of instruction corresponding to functional unit N may be stored in instruction dispatch queue N and instruction dispatch queue Q. In one embodiment, if any instruction dispatch queue corresponding to the first type of instruction is free, the first type of instruction that is first stored in the instruction dispatch cache may be dispatched to the free instruction dispatch queue. For example, if instruction dispatch queue 1 and instruction dispatch queue 2 both store instructions of the first type, and instruction dispatch queue 1 and instruction dispatch queue 2 are full; the newly generated instruction to be issued of the first type will be stored to the instruction dispatch cache. When any one of instruction dispatch queue 1 and instruction dispatch queue 2 is free, the first type of instruction to be issued stored first in the instruction dispatch buffer is stored in the free instruction dispatch queue in instruction dispatch queue 1 or instruction dispatch queue 2. For another example, if instruction dispatch queue 1 and instruction dispatch queue 2 both store instructions of the first type and instruction dispatch queue 1 and instruction dispatch queue 2 are full; the newly generated instruction to be issued of the first type will be stored to the instruction dispatch cache. When the instruction dispatch queue 1 and the instruction dispatch queue 2 are idle at the same time, the first type of instruction to be transmitted, which is stored in the instruction dispatch cache first, can be randomly stored into the instruction dispatch queue 1 or the instruction dispatch queue 2; or the first type of instruction to be issued stored in the instruction dispatch cache firstly is dispatched to the instruction dispatch queues with less functional units in the instruction dispatch queue 1 and the instruction dispatch queue 2, namely the instruction dispatch queue 1 and the instruction dispatch queue 2.
It should be noted that, in the embodiment of the present application, the instruction issue queue is free, which means that a free position in the instruction issue queue can store an instruction, and can dispatch the instruction to the instruction issue queue. In the embodiment of the application, the instruction issue queue is not free or the instruction issue queue is full, which means that no free position in the instruction issue queue can store an instruction and the instruction issue queue cannot be assigned with an instruction.
By additionally arranging the instruction dispatching cache, the instruction to be dispatched to the full instruction transmitting queue can be stored in the instruction dispatching cache, so that instruction blockage is avoided; and the front-end pipeline stop caused by instruction blocking is avoided, and the instruction dispatching efficiency and the processor performance are improved. In addition, instruction blocking can cause uneven utilization of an instruction transmitting queue, thereby causing resource waste; this application can promote resource utilization through avoiding the instruction to block up.
It should be noted that since the advent of the first general-purpose computer, computer technology has gained rapid growth over decades, and that rapid growth in computer technology has benefited from improvements in computer architecture and advances in computer manufacturing technology. The contribution of computer production technology to the development of computer technology has been stable; however, as the computer architecture has been improved for decades, the space for improving the computer architecture is becoming increasingly narrow, and therefore any small improvement on the computer architecture will have a significant impact on the performance of the processor and the development of computer technology.
The instruction dispatching device provided by the embodiment of the application can be implemented in a software manner, and fig. 7 shows the instruction dispatching device stored in the memory, which includes a plurality of modules, where the modules may be software in the form of programs, plug-ins, and the like, and include the following software modules:
a setting unit 701 for setting an instruction dispatch cache;
a processing unit 702, configured to store an instruction to be dispatched to the instruction dispatch cache when the instruction issue queue is not free;
a dispatch unit 703, configured to dispatch the instruction to be dispatched from the instruction dispatch cache to the instruction issue queue in response to the instruction issue queue being free.
In some optional embodiments, the dispatch unit 703 is configured to dispatch the to-be-dispatched instructions in the instruction dispatch cache to the instruction issue queue according to a storage order of the instructions in the instruction dispatch cache.
In some optional embodiments, the instruction dispatch cache comprises at least one sub-instruction dispatch cache, each sub-instruction dispatch cache for storing at least one type of instruction, any two sub-instruction dispatch caches storing instructions of different types.
In some optional embodiments, the dispatch unit 703 is configured to, when a first instruction issue queue corresponding to the first type of instruction is free, dispatch an instruction to be dispatched in the first sub-instruction dispatch cache to the first instruction issue queue;
wherein the first sub-instruction dispatch cache is to store at least the first type of instruction.
In some optional embodiments, the dispatch unit 703 is configured to dispatch the to-be-dispatched instructions in the first sub-instruction dispatch cache to the first instruction issue queue according to a storage order of the instructions in the first sub-instruction dispatch cache.
In some optional embodiments, the dispatch unit 703 is configured to dispatch the instruction to be dispatched, which is stored in the first sub-instruction dispatch cache first, to the first instruction issue queue.
In some optional embodiments, the instruction dispatch cache is to store all types of instructions, the all types of instructions corresponding to one instruction issue queue.
It should be noted that the description of the instruction dispatching device in the embodiment of the present application is similar to the description of the above embodiment of the instruction dispatching method, and has similar advantages to the method embodiment, and therefore, the description is omitted here.
An exemplary application of the electronic device provided in the embodiments of the present application is described below, and the electronic device provided in the embodiments of the present application may be implemented as an electronic device, and the electronic device may be a server or a terminal device.
The server may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a cloud server providing cloud computing services. The terminal device may be, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smart watch, and the like. The terminal device and the server may be directly or indirectly connected through wired or wireless communication, and the embodiment of the present application is not limited herein.
Referring to fig. 8, fig. 8 is a schematic structural diagram of an electronic device 400 according to an embodiment of the present disclosure, illustrating the electronic device
The electronic device 400 shown in fig. 8 includes: at least one processor 410, memory 450, and bus 440; the various components in electronic device 400 are coupled together by a bus 440. It is understood that bus 440 is used to enable connected communication between these components. Bus 440 includes a power bus, a control bus, and a status signal bus in addition to a data bus. But for clarity of illustration the various busses are labeled as bus 440 in figure 8.
The Processor 410 may be an integrated circuit chip having Signal processing capabilities, such as a general purpose Processor, a Digital Signal Processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like, wherein the general purpose Processor may be a microprocessor or any conventional Processor, or the like.
The memory 450 stores executable instructions for implementing the instruction dispatching method provided by the embodiment of the present application, which can be implemented by the setting unit 701, the processing unit 702, and the dispatching unit 703 in the instruction dispatching apparatus shown in fig. 8; the memory 450 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid state memory, hard disk drives, optical disk drives, and the like. Memory 450 optionally includes one or more storage devices physically located remote from processor 410.
In some embodiments, memory 450 is capable of storing data, examples of which include programs, modules, and data structures, or a subset or superset thereof, to support various operations.
In some embodiments, the electronic device 400 may further include:
an operating system 451, including system programs for handling various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and handling hardware-based tasks;
a network communication module 452 for communicating to other computing devices via one or more (wired or wireless) network interfaces 420, exemplary network interfaces 420 including: bluetooth, wireless compatibility authentication (WiFi), and Universal Serial Bus (USB), among others.
Embodiments of the present application provide a computer-readable storage medium having stored therein executable instructions that, when executed by a processor, cause the processor to perform an instruction dispatching method provided by embodiments of the present application, for example, the instruction dispatching method shown in fig. 5.
In some embodiments, the computer-readable storage medium may be memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash, magnetic surface memory, optical disk, or CD-ROM; or may be various devices including one or any combination of the above memories.
In some embodiments, the executable instructions may be in the form of a program, software module, script, or code written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.
By way of example, executable instructions may be deployed to be executed on one computing device or on multiple computing devices at one site or distributed across multiple sites and interconnected by a communication network.
Embodiments of the present application provide a computer program product comprising a computer program/instructions, which when executed by a processor, implement the instruction dispatching method described herein.
The above description is only an example of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, and improvement made within the spirit and scope of the present application are included in the protection scope of the present application.
Claims (11)
1. A method of instruction dispatch, the method comprising:
setting an instruction dispatch cache;
when the instruction transmitting queue is not free, storing the instruction to be dispatched to the instruction dispatching cache;
in response to the instruction issue queue being free, dispatching the instruction to be dispatched in the instruction dispatch cache to the instruction issue queue.
2. The method of claim 1, wherein said dispatching the instruction to be dispatched in the instruction dispatch cache to the instruction issue queue in response to the instruction issue queue being free comprises:
and dispatching the instructions to be dispatched in the instruction dispatching cache to the instruction emission queue according to the storage sequence of the instructions in the instruction dispatching cache.
3. The method of claim 1, wherein said instruction dispatch cache comprises at least one sub-instruction dispatch cache, each said sub-instruction dispatch cache for storing at least one type of instruction, any two sub-instruction dispatch caches storing instructions of different types.
4. The method of claim 3, wherein said dispatching the instruction to be dispatched in the instruction dispatch cache to the instruction issue queue in response to the instruction issue queue being free comprises:
when a first instruction transmitting queue corresponding to a first type of instruction is idle, allocating an instruction to be allocated in a first sub-instruction allocation cache to the first instruction transmitting queue;
wherein the first sub-instruction dispatch cache is to store at least the first type of instruction.
5. The method of claim 4, wherein said dispatching the instruction to be dispatched in the first sub-instruction dispatch cache to the first instruction issue queue comprises:
and dispatching the instructions to be dispatched in the first sub-instruction dispatch cache to the first instruction transmitting queue according to the storage sequence of the instructions in the first sub-instruction dispatch cache.
6. The method as claimed in claim 5, wherein said dispatching instructions to be dispatched in said first sub-instruction dispatch cache to said first instruction issue queue in an order in which instructions in said first sub-instruction dispatch cache are stored comprises:
and dispatching the instruction to be dispatched which is stored in the first sub-instruction dispatch cache firstly to the first instruction transmitting queue.
7. The method of claim 1, wherein the instruction dispatch cache is configured to store all types of instructions, the all types of instructions corresponding to an instruction issue queue.
8. An instruction dispatching apparatus, comprising:
a setting unit for setting an instruction dispatch cache;
the processing unit is used for storing the instruction to be dispatched to the instruction dispatching cache when the instruction transmitting queue is not free;
and the dispatching unit is used for responding to the instruction transmitting queue being free, and dispatching the instruction to be dispatched in the instruction dispatching cache to the instruction transmitting queue.
9. An electronic device, characterized in that the electronic device comprises:
a processor, a memory, and a bus;
the memory stores executable instructions;
the processor and the memory are communicated through the bus, and when the processor executes the executable instructions stored in the memory, the instruction dispatching method of any one of claims 1 to 7 is realized.
10. A computer-readable storage medium storing executable instructions for implementing the instruction dispatch method of any one of claims 1 to 7 when executed by a processor.
11. A computer program product comprising a computer program/instructions which, when executed by a processor, implements the instruction dispatch method of any one of claims 1 to 7.
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