CN114966223A - Capacitance measuring method for eliminating parasitic capacitance in measuring circuit - Google Patents

Capacitance measuring method for eliminating parasitic capacitance in measuring circuit Download PDF

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Publication number
CN114966223A
CN114966223A CN202210522862.5A CN202210522862A CN114966223A CN 114966223 A CN114966223 A CN 114966223A CN 202210522862 A CN202210522862 A CN 202210522862A CN 114966223 A CN114966223 A CN 114966223A
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CN
China
Prior art keywords
capacitance
parasitic
capacitor
measurement
measuring
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Pending
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CN202210522862.5A
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Chinese (zh)
Inventor
徐建
杨逸凡
闵可
秦唐臻
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Nanjing Sino Chip Microelectronics Co ltd
Southeast University
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Nanjing Sino Chip Microelectronics Co ltd
Southeast University
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Priority to CN202210522862.5A priority Critical patent/CN114966223A/en
Publication of CN114966223A publication Critical patent/CN114966223A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/14—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
    • G01R15/16—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using capacitive devices

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

The invention discloses a capacitance measuring method for eliminating parasitic capacitance in a measuring circuit, which generates negative capacitance based on Miller effect and cancels the parasitic capacitance, thereby solving the problems of limited measuring range and low measuring precision caused by the parasitic capacitance in the field of capacitance measurement at present. Meanwhile, the capacitance measuring circuit can dynamically adapt to the change of parasitic capacitance caused by the change of a parasitic environment through a logic function, and solves the problem that a common circuit cannot eliminate the influence of the parasitic capacitance, thereby improving the accuracy and the measuring range of capacitance measurement. The method can be widely applied to the fields of capacitive sensor, touch screen design and the like.

Description

Capacitance measuring method for eliminating parasitic capacitance in measuring circuit
Technical Field
The invention relates to a capacitance measuring method, in particular to a capacitance measuring method for eliminating parasitic capacitance in a measuring circuit.
Background
Capacitors are electronic components that are used very frequently, both in terms of the kind and the number of uses. With the development of electronic materials and processes, on one hand, capacitance is developed towards large capacity and high frequency, and on the other hand, due to the requirement of miniaturization development of equipment, the use of capacitors is also more and more extensive, which requires that a measuring circuit can meet the continuously developed requirement.
With the requirements on the accuracy and the speed of capacitance measurement becoming higher and higher, the error ratio generated by some non-ideal factors in an actual circuit becomes larger and larger, and the capacitance measurement is greatly influenced. When the capacitance is measured, the miniaturization of the device and the connecting line in the internal structure of the circuit bring parasitic capacitance, and some parasitic capacitance even have the same size with the measured capacitance, thus deteriorating the detection result. Therefore, in modern capacitance measurement techniques, more and more methods are applied to eliminate parasitic capacitance, such as the add initial capacitance method, the drive cable technique, and the integral shielding method. The method of increasing the initial capacitance value may reduce the parasitic capacitance with respect to the capacitance of the capacitive sensor, but is limited by the manufacturing and assembly processes, precision, range of indication, breakdown voltage, etc. The parasitic capacitance is eliminated by adopting the drive cable technology, the amplification factor of the drive amplifier is strictly equal to 1 in a very wide frequency band, the phase shift of input and output is zero, and the design requirement is high. The integral shielding method is to utilize metal materials with better absorption and reflection capability to electromagnetic waves for anti-interference, and shield the capacitive sensor, the adopted measuring circuit, the adopted transmission cable and the like by the same shielding shell, so that the structure becomes more complex. These approaches can mitigate the effects of parasitic capacitance, but introduce more complex design structures and manufacturing costs, especially for integrated circuit designs, which consume excessive area. In addition, when the environmental temperature and the like change, the size of the parasitic capacitance changes, and the above conventional capacitance measurement method cannot eliminate the influence of the parasitic capacitance changing with the environment.
Disclosure of Invention
The purpose of the invention is as follows: in view of the above prior art, a capacitance measurement method for eliminating parasitic capacitance in a measurement circuit is provided.
The technical scheme is as follows: a capacitance measurement method of eliminating parasitic capacitance in a measurement circuit, comprising: before the capacitor to be measured is connected into the capacitance measuring module, a negative capacitor is generated through the Miller effect to cancel the equivalent input parasitic capacitor, and then the capacitor to be measured is connected into the capacitor to be measured to measure the capacitance.
Further, if the equivalent input parasitic capacitance detected by the capacitance measuring module is larger than a set threshold, the size of the negative capacitance generated by the miller effect is increased step by step until the condition is met, and then the capacitance to be measured is accessed for capacitance measurement.
Further, after the equivalent input parasitic capacitance is re-detected and cancelled every t time intervals, the capacitance to be measured is measured again, and parasitic capacitance change in the self-adaptive capacitance measurement is achieved.
Further, the capacitance measuring module is used for converting the capacitance size into an electrical analog quantity.
Further, the negative capacitance is generated through a negative capacitance generator, the negative capacitance generator is composed of a gain-adjustable non-inverting amplifier and a feedback capacitance connected across the non-inverting amplifier, and the output negative capacitance is connected in parallel with the input end of the capacitance measuring module.
Further, the capacitance value of a feedback capacitor connected across the non-inverting amplifier is changed to adjust the magnitude of the negative capacitance value.
Furthermore, the feedback capacitor comprises (n +1) capacitors connected in parallel, a pair of switches is respectively arranged on branches of each capacitor, and the capacitor is located between the two switches.
Furthermore, the first capacitor in the (n +1) capacitors connected in parallel has the size of C B Starting from the second capacitance, the ith capacitance has a magnitude of 2 (i-2) C B 。
Has the advantages that: the method aims to solve the problems that the capacitance measurement range is limited due to the fact that parasitic capacitance is generated in design, manufacture and use environments during capacitance measurement, and measurement deviation is caused due to the fact that the parasitic capacitance is changed due to the fact that the environment changes. The invention generates negative capacitance based on the Miller effect and cancels the parasitic capacitance, thereby solving the problems of limited measurement range and low measurement precision caused by the parasitic capacitance in the field of capacitance measurement at present. Meanwhile, the capacitance measuring circuit can dynamically adapt to the change of parasitic capacitance caused by the change of a parasitic environment through a logic function, and solves the problem that a common circuit cannot eliminate the influence of the parasitic capacitance, thereby improving the accuracy and the measuring range of capacitance measurement. The method can be widely applied to the fields of capacitive sensor, touch screen design and the like.
Drawings
FIG. 1 is a block diagram of the hardware architecture upon which the present invention is based;
FIG. 2 is a block diagram of a negative capacitor generator according to the present invention;
FIG. 3 is a schematic diagram of a feedback capacitor structure of a negative capacitor generator;
FIG. 4 is a flow chart of the method of the present invention.
Detailed Description
The invention is further explained below with reference to the drawings.
The hardware circuit structure for implementing the method of the present invention is shown in FIG. 1, and includes a capacitor C to be measured X The device comprises an input switch 2, a logic control module 4, a negative capacitance generator 5 and a capacitance measuring module 6.
As shown in FIG. 2, the negative capacitance generator 5 comprises a non-inverting amplifier 501 and a feedback capacitor C connected across the non-inverting amplifier 501 F And (4) forming. As shown in fig. 3, the feedback capacitor C F The circuit comprises (n +1) capacitors 503 connected in parallel, a pair of switches 504 is respectively arranged on branches of each capacitor 503, the capacitors are positioned between the two switches, namely, each capacitor access circuit is simultaneously controlled by the pair of switches, and the switch pairs are controlled by the logic module 4. In the capacitor array, the first capacitor has a size of C B Starting from the second capacitance, the ith capacitance has a magnitude of 2 (i-2) C B I.e. the second capacitor begins to increase its capacitance value by an arithmetic progression with a difference value of C B 。
Capacitance C to be measured X Is electrically connected with the input switch 2. The logic control module 4 is electrically connected with the negative capacitance generator 5 and the capacitance measuring module 6, and can be used for the input switch 2 and the feedback capacitor C F The switch in (1) is controlled.
Equivalent input parasitic capacitance C P Is the negative capacitance generator 5Connected to a feedback capacitor C F The sum of all the equivalent parasitic capacitances at the input of the capacitance detection module 6. Equivalent input parasitic capacitance C P The capacitance is the equivalent sum of all parasitic capacitances of an external capacitance interface end to be measured, an input end of a capacitance measurement module and an input switch, and the equivalent input parasitic capacitance C P The specific value is an uncertain value due to various factors such as the specific design scheme of the adopted circuit, the process type of the circuit, the measured working environment, the process deviation and the like.
Based on the structure, the capacitance measuring method for eliminating the parasitic capacitance in the measuring circuit is used for measuring the capacitance C to be measured X Before the input switch 2 is connected to the capacitance measuring module 6, a negative capacitance generator 5 generates a negative capacitance 502 to cancel the equivalent input parasitic capacitance C P Then the capacitance C to be measured is accessed X A capacitance measurement is performed.
Specifically, the negative capacitance generator 5 generates a negative capacitance by the miller effect, as shown in fig. 2, a feedback capacitance C F The in-phase amplifier 501 is a practical device, and the capacitance equivalent to the input end of the in-phase amplifier 501 is a feedback capacitance C F And the amplification factor a of the non-inverting amplifier 502 V Determined together, the value of the capacitance is (1-A) obtained by the Miller's equivalent theorem V )C F . Since the gain of the in-phase amplifier 501 is positive, when the amplification factor A is large V Above 1, the capacitance equivalent to the input of the non-inverting amplifier 501 will become negative, thereby providing a negative capacitance 502. The range of the negative capacitance 502 generated by the negative capacitance generator 5 is to include the equivalent input parasitic capacitance C P The range of variation of (a).
The capacitance measuring module 6 is able to convert the capacitance into an electrical quantity which can be recognized by the logic control module 4. The negative capacitance generator 5 cancels the equivalent input parasitic capacitance C through the negative capacitance 502 generated by the Miller effect P If the capacitance measuring module 6 detects the obtained equivalent input parasitic capacitance C P If the current value is larger than the set threshold value, the size of the negative capacitor 502 generated by the Miller effect is increased step by step until the condition is met, and then the capacitor C to be measured is accessed X A capacitance measurement is performed. In particular, logicThe control module 4 carries out logic control through the output quantity delta generated by the capacitance measuring module 6, the logic control module 4 contains a set error epsilon, and in the state that the input switch 2 is disconnected, if the electric quantity delta is>ε, then means the parasitic capacitance is not cancelled out successfully, if the electrical quantity is δ<E, it means that the parasitic capacitance cancellation is successful.
The feedback capacitor array structure shown in FIG. 3 can provide the minimum capacitance C B Can provide the maximum capacitance value (2) n +1)C B . When the parasitic capacitance is not successfully cancelled, the logic control module 4 controls the switch pair in the negative capacitance generator 5, so that the feedback capacitance C F Each increment is C B . A parasitic capacitance C equivalent to the input is generated by the negative capacitance generator 5 P The negative capacitors 502 with the same size are connected in parallel with the negative capacitors 502 at the input end of the capacitance measuring module 6, namely the negative capacitors 502 and the parasitic capacitor C P And the parasitic capacitance is cancelled in parallel. After the parasitic capacitance is cancelled, the input switch 2 is controlled to be closed, and the capacitance C to be measured is detected X And the capacitance measurement module 6 is accessed to carry out capacitance measurement.
In the process, the equivalent input parasitic capacitance C changing with the environment is detected and counteracted again at the time of t interval P Then, for the capacitance C to be measured X And measuring again to realize the change of the parasitic capacitance in the self-adaptive capacitance measurement.
As shown in fig. 4, a specific embodiment of the method of the present invention includes:
s1: capacitance C to be measured X Accessing a circuit, and starting the circuit to work;
s2: the logic control module 4 controls the input switch 2 to be switched off, which is equivalent to the situation that the measuring capacitor C is not accessed X Seen from the input end, there is only the equivalent input parasitic capacitance C P ；
S3: the logic control module 4 controls all switch pairs in the negative capacitance generator 5 to be disconnected, namely, the feedback capacitance C is not connected F ；
S4: at this moment, the capacitance measuring module 6 inputs the equivalent input parasitic capacitance C at the moment P The magnitude is converted into an electrical quantity delta which is compared with a set error epsilon. If the electrical analog quantity delta>ε, then S5 is performed, otherwise S is performed6。
S5: the logic control module 4 controls the switch pairs in the negative capacitance generator 5 so that the feedback capacitance array is increased by an amount C B The size of the feedback capacitor array access circuit is changed to C F ’ The gain produced by the non-inverting amplifier is A V A feedback capacitor C connected across the in-phase amplifier due to Miller effect F ’ Equivalent to generate a negative capacitance at the input end, the capacitance is (1-A) V1 )C F Connected in parallel with the parasitic capacitance; after the above operation is completed, S4 is executed;
s6: the logic control module 4 controls the input switch 2 to be closed, namely the capacitor C to be tested X And (4) conducting, wherein the electrical quantity measured by the capacitance measuring module 6 is the corresponding capacitance conversion value.
S7: after time t, equivalent input parasitic capacitance C P As the application environment is changed, the control circuit of the logic control module 4 restarts to jump to execute S1, the influence of the changed parasitic capacitance is eliminated in a self-adaptive manner, and a new capacitor C to be measured is obtained X A conversion value;
s8: and (4) calculating the number of times of measurement, returning to S2 if the number of times of measurement is less than the preset number n, and otherwise, finishing the measurement step.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (8)

1. A capacitance measurement method for eliminating parasitic capacitance in a measurement circuit, comprising: before the capacitor to be measured is connected into the capacitance measuring module, a negative capacitor is generated through the Miller effect to cancel the equivalent input parasitic capacitor, and then the capacitor to be measured is connected into the capacitor to be measured to measure the capacitance.
2. The method as claimed in claim 1, wherein if the equivalent input parasitic capacitance detected by the capacitance measuring module is greater than a predetermined threshold, the magnitude of the negative capacitance generated by miller effect is increased step by step until a capacitance to be measured is accessed for capacitance measurement after a condition is met.
3. The capacitance measurement method for eliminating the parasitic capacitance in the measurement circuit according to claim 1 or 2, wherein after the equivalent input parasitic capacitance is re-detected and eliminated every t time, the capacitance to be measured is re-measured, so as to realize the parasitic capacitance change in the adaptive capacitance measurement.
4. The capacitance measuring method for eliminating parasitic capacitance in a measuring circuit according to claim 1 or 2, wherein the capacitance measuring module is used for converting a capacitance magnitude into an electrical analog quantity.
5. The capacitance measurement method for eliminating the parasitic capacitance in the measurement circuit according to claim 1 or 2, wherein the negative capacitance is generated by a negative capacitance generator, the negative capacitance generator is composed of a gain-adjustable non-inverting amplifier and a feedback capacitance connected across the non-inverting amplifier, and the output negative capacitance is connected in parallel with an input end of the capacitance measurement module.
6. The capacitance measurement method for eliminating parasitic capacitance of claim 5, wherein the magnitude of the negative capacitance is adjusted by changing a capacitance value of a feedback capacitance connected across the non-inverting amplifier.
7. The capacitance measurement method for eliminating the parasitic capacitance in the measurement circuit according to claim 6, wherein the feedback capacitance comprises (n +1) capacitors connected in parallel, a pair of switches is respectively arranged on branches of each capacitor, and the capacitor is located between the two switches.
8. The capacitance measuring method for eliminating parasitic capacitance of a measuring circuit according to claim 7, wherein (n +1) pieces are connected in parallelOf the capacitors, the first capacitor has a value of C B Starting from the second capacitance, the ith capacitance has a magnitude of 2 (i-2) C B 。
CN202210522862.5A 2022-05-13 2022-05-13 Capacitance measuring method for eliminating parasitic capacitance in measuring circuit Pending CN114966223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210522862.5A CN114966223A (en) 2022-05-13 2022-05-13 Capacitance measuring method for eliminating parasitic capacitance in measuring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210522862.5A CN114966223A (en) 2022-05-13 2022-05-13 Capacitance measuring method for eliminating parasitic capacitance in measuring circuit

Publications (1)

Publication Number Publication Date
CN114966223A true CN114966223A (en) 2022-08-30

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Application Number Title Priority Date Filing Date
CN202210522862.5A Pending CN114966223A (en) 2022-05-13 2022-05-13 Capacitance measuring method for eliminating parasitic capacitance in measuring circuit

Country Status (1)

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