CN114944973A - Clock signal recovery method and system - Google Patents
Clock signal recovery method and system Download PDFInfo
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- CN114944973A CN114944973A CN202210876714.3A CN202210876714A CN114944973A CN 114944973 A CN114944973 A CN 114944973A CN 202210876714 A CN202210876714 A CN 202210876714A CN 114944973 A CN114944973 A CN 114944973A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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Abstract
The application discloses a clock signal recovery method and a system, wherein the method comprises the following steps: converting PAM4 serial data into NRZ serial data; recovering a clock signal from the NRZ serial data; and if the corresponding clock signal does not exist at the current time, generating the clock signal corresponding to the current time according to the clock signal which is closest to the current time in the recovered clock signals. According to the technical scheme, the PAM4 signal is converted into the NRZ signal to recover the clock signal, so that the clock signal is relatively simply and reliably recovered, the synchronism of clock signal recovery is improved, and the clock signal corresponding to the current time is generated according to the clock signal which is closest to the current time in the recovered clock signals when the corresponding clock signal does not exist at the current time, so that the stable output of the clock signal is ensured, and the clock signal recovery effect is improved.
Description
Technical Field
The present application relates to the field of optical fiber communication technologies, and in particular, to a clock signal recovery method and system.
Background
In digital optical fiber transmission systems, there are generally two ways to obtain a timing clock signal, one is to transmit the clock signal alone in a channel, and the other is to extract the clock signal from a received digital signal. However, the former approach is expensive, and therefore, the latter approach is usually implemented by means of a timing extraction circuit in the receiver.
PAM4 (4 Pulse Amplitude Modulation) is a Modulation technique that uses 4 different signal levels for signal transmission, and is currently widely used in the field of high-speed signal interconnection. At present, PAM4 signals are generally input directly to a PAM4 serial data to an optical fiber communication clock recovery unit, and clock signals are recovered from PAM4 serial data by the optical fiber communication clock recovery unit. However, the PAM4 signal not only has two high and low levels, but also has two intermediate levels between the high and low levels. In the case of comparable signal peaks, the PAM4 signal will be much more complex in level-shifted form and much shorter in time available for amplitude sampling, and therefore, it is difficult to recover a synchronous clock signal from the PAM4 signal, and the recovered clock signal will be much less synchronous.
In view of the above, how to easily recover a clock signal from a PAM4 signal and improve the synchronization of clock signal recovery is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, it is an object of the present invention to provide a clock signal recovery method and system, which can easily recover a clock signal from a PAM4 signal and improve the synchronization of clock signal recovery.
In order to achieve the above purpose, the present application provides the following technical solutions:
a clock signal recovery method, comprising:
converting PAM4 serial data into NRZ serial data;
recovering a clock signal from the NRZ serial data;
and if the corresponding clock signal does not exist in the current time, generating the clock signal corresponding to the current time according to the clock signal which is closest to the current time in the recovered clock signals.
Preferably, before converting the PAM4 serial data into the NRZ serial data, the method further includes:
and performing high-frequency compensation on the PAM4 serial data.
Preferably, after recovering a clock signal from the NRZ serial data, the method further includes:
carrying out frequency division processing on the recovered clock signal;
and calculating the clock frequency of the clock signal obtained by frequency division, and recording the clock frequency.
Preferably, the generating the clock signal corresponding to the current time according to the clock signal closest to the current time in the recovered clock signals includes:
generating a reference clock according to the clock frequency corresponding to the clock signal which is closest to the current time in the recovered clock signals;
and generating a clock signal corresponding to the current time according to the reference clock.
A clock signal recovery system comprises a data conversion unit, an optical fiber communication clock recovery unit connected with the data conversion unit and a clock signal generation unit connected with the optical fiber communication clock recovery unit, wherein:
the data conversion unit is used for converting PAM4 serial data into NRZ serial data;
the optical fiber communication clock recovery unit is used for recovering a clock signal from the NRZ serial data;
the clock signal generating unit is used for generating the clock signal corresponding to the current time according to the clock signal which is closest to the current time in the recovered clock signals if the corresponding clock signal does not exist at the current time.
Preferably, the method further comprises the following steps:
and the equalizer is connected with the data conversion unit and is used for performing high-frequency compensation on the PAM4 serial data.
Preferably, the method further comprises the following steps:
the frequency divider is used for carrying out frequency division processing on the recovered clock signal;
the clock signal generation unit includes:
and the FPGA is connected with the frequency divider and used for calculating the clock frequency of the clock signal obtained by frequency division and recording the clock frequency.
Preferably, the clock signal generating unit further comprises a clock generator connected to the FPGA;
the FPGA is further used for controlling the clock generator to generate a reference clock according to the clock frequency corresponding to the clock signal closest to the current time in the recovered clock signals, and the reference clock is input to the optical fiber communication clock recovery unit by the clock generator;
and the optical fiber communication clock recovery unit is used for generating a clock signal corresponding to the current time according to the reference clock.
Preferably, the data conversion unit is embodied as a limiting amplifier.
The application provides a clock signal recovery method and a system, wherein the method comprises the following steps: converting PAM4 serial data into NRZ serial data; recovering a clock signal from the NRZ serial data; and if the corresponding clock signal does not exist at the current time, generating the clock signal corresponding to the current time according to the clock signal which is closest to the current time in the recovered clock signals.
According to the technical scheme disclosed by the application, the PAM4 serial data is converted into the NRZ serial data, then the clock signal is recovered from the NRZ serial data, namely, the PAM4 signal is converted into the NRZ signal to recover the clock signal, and the NRZ serial data only has high and low level values, so that the clock signal can be recovered relatively simply and reliably, and the synchronism of clock signal recovery can be improved. In addition, when PAM4 serial data is converted into NRZ serial data for clock signal recovery, if no corresponding clock signal exists at the current time, the clock signal corresponding to the current time can be generated according to the clock signal closest to the current time in the recovered clock signals, so as to avoid interruption of the recovered clock signal due to less sampling opportunities caused by conversion of PAM4 serial data into NRZ serial data, that is, to ensure stable output of the clock signal, thereby improving the clock signal recovery effect.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating a conventional method for recovering a synchronous clock signal from data in PAM4 format;
fig. 2 is a flowchart of a clock recovery method according to an embodiment of the present application;
FIG. 3 is a schematic diagram of recovering a clock signal from NRZ serial data according to an embodiment of the present application;
fig. 4 is a logic diagram of a basic component of a clock recovery unit for optical fiber communication according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a clock signal recovery system according to an embodiment of the present disclosure.
Detailed Description
Referring to fig. 1, a schematic diagram of recovering a synchronous clock signal from data in PAM4 format in the prior art is shown, that is, a clock signal is recovered from data in PAM4 format directly by using an optical fiber communication clock recovery unit, where the optical fiber communication clock recovery unit in fig. 1 may specifically be an optical fiber communication clock recovery unit taking a phase-locked loop circuit as a core. However, the PAM4 signal has four levels, and in the case of equivalent signal peaks, the level conversion form of the PAM4 signal is much more complex, and the time available for amplitude sampling is much shorter, so that it is difficult to recover a synchronous clock signal from the PAM4 signal, and the synchronism of the recovered clock signal is much worse. And this situation becomes more severe with small signals, resulting in a less sensitive clock recovery system.
Therefore, the present application provides a clock signal recovery method and system, which can easily recover a clock signal from a PAM4 signal and improve the synchronization of clock signal recovery.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 2, which shows a flowchart of a clock recovery method provided in an embodiment of the present application, a clock signal recovery method provided in an embodiment of the present application may include:
s11: PAM4 serial data is converted into NRZ serial data.
When clock signal recovery is performed from PAM4 serial data, PAM4 serial data may be converted into NRZ (Not Return to Zero) serial data first, so that clock signal recovery of PAM4 serial data is achieved by performing clock signal recovery on the converted NRZ serial data.
Specifically, the PAM4 serial data may be converted into NRZ serial data by setting a threshold in advance (the size of the threshold may be set according to actual needs), comparing PAM4 serial data with the preset threshold, converting data smaller than the preset threshold in PAM4 serial data into a low level, and converting data not smaller than the preset threshold in PAM4 serial data into a high level. Of course, this can be achieved in other ways.
It should be noted that, in the case of ensuring the system index, PAM4 serial data needs to be converted into NRZ serial data, so as to improve the reliability and operational stability of the entire system.
S12: a clock signal is recovered from the NRZ serial data.
On the basis of step S11, a clock signal may be recovered from the converted NRZ serial data. The manner of recovering the clock signal from the conversion into the NRZ serial data may be specifically the same as the manner of recovering the clock signal from the NRZ serial data in the related art. Specifically, the shortest jump is selected as a reference for recovering the clock signal in the process of converting from a low level to a high level and converting from the high level to the low level, namely, the clock signal is recovered by capturing the most adjacent one-time rising edge and falling edge in the NRZ serial data.
Specifically, referring to fig. 3, a schematic diagram of recovering a clock signal from NRZ serial data is shown, where there are only two levels, i.e., high and low, in NRZ-format binary data, the clock signal recovery is relatively simple to implement, and a synchronous clock signal is recovered from NRZ-format binary data. Therefore, by converting PAM4 serial data into NRZ serial data, recovery of a data clock can be performed relatively easily and reliably in a manner of performing clock signal recovery, and the synchronism and effect of clock signal recovery can be improved.
It should be noted that, the optical fiber communication clock recovery unit in fig. 3 may specifically adopt a phase-locked loop method to recover a clock signal, and certainly, may also adopt other methods to recover a clock signal, which is not limited in this application.
S13: and if the corresponding clock signal does not exist at the current time, generating the clock signal corresponding to the current time according to the clock signal which is closest to the current time in the recovered clock signals.
It is considered that transition information of the intermediate level is lost in converting PAM4 serial data into NRZ serial data, i.e., rising and falling edges of the intermediate level are ignored, and thus, a long high level duration occurs. The clock signal can still be recovered by sampling the rising and falling edges of the NRZ signal into which the PMA4 signal is converted, but the presence of a sustained level (e.g., a sustained high level) reduces the chance of such sampling and interrupts the output of the recovered clock signal without any processing. Therefore, when a clock signal is recovered from NRZ serial data, if the fact that the corresponding clock signal does not exist at the current time is determined, the clock signal corresponding to the current time can be generated according to the clock signal which is closest to the current time in the recovered clock signals. For example: taking the theoretical sampling once per second and performing clock signal recovery as an example, it is assumed that the clock signal is recovered from the converted NRZ serial data in the first second; if the clock signal cannot be recovered in the second, generating a clock signal corresponding to the second according to the recovered clock signal in the first second; if the clock signal cannot be recovered in the third second, the clock signal … … corresponding to the third second is generated according to the recovered clock signal in the first second until the fifth second, and the clock signal is recovered from the converted NRZ serial data; if the clock signal cannot be recovered in the sixth second, the clock signal … … corresponding to the sixth second is generated according to the recovered clock signal in the fifth second until the last recovery or generation of the clock signal is completed.
Through the above process, the latest clock signal output can still be maintained in a state that the converted NRZ serial data continues at a certain level (for example, continues at a high level), so that a stable output clock signal can be ensured (i.e., a continuous and uninterrupted clock signal can be output), and the clock signal recovery effect can be improved.
According to the technical scheme disclosed by the application, PAM4 serial data is firstly converted into NRZ serial data, then the clock signal is recovered from the NRZ serial data, namely, the PAM4 signal is converted into the NRZ signal to recover the clock signal, and because the NRZ serial data only has two levels, namely a high level and a low level, the clock signal can be recovered simply and reliably, and the synchronization of clock signal recovery can be improved. In addition, when PAM4 serial data is converted into NRZ serial data for clock signal recovery, if no corresponding clock signal exists at the current time, the clock signal corresponding to the current time can be generated according to the clock signal closest to the current time in the recovered clock signals, so as to avoid interruption of the recovered clock signal due to less sampling opportunities caused by conversion of PAM4 serial data into NRZ serial data, that is, to ensure stable output of the clock signal, thereby improving the clock signal recovery effect.
Before converting PAM4 serial data into NRZ serial data, the clock signal recovery method according to an embodiment of the present application may further include:
high frequency compensation is performed on PAM4 serial data.
In the application, before PAM4 serial data is converted into NRZ serial data, high-frequency compensation can be performed on PAM4 serial data, so that the level change of the PAM4 serial data can become steeper, namely symbol jump is steeper, information loss is reduced, the sampling time is almost the same as the sampling time in the converted NRZ serial data, and the recovery effect, the recovery accuracy and the recovery reliability of clock signal recovery of the PAM4 serial data are improved.
The clock signal recovery method provided in the embodiment of the present application, after recovering a clock signal from NRZ serial data, may further include:
carrying out frequency division processing on the recovered clock signal;
and calculating the clock frequency of the clock signal obtained by frequency division, and recording the clock frequency.
In the present application, since the recovered clock signal belongs to a high frequency signal, in order to better record the recovered clock signal and to facilitate better generation of the clock signal according to the recovered clock signal to ensure stable output of the clock signal, after the clock signal is recovered from the NRZ serial data, the recovered clock signal may be subjected to frequency division processing to divide the clock signal of a low frequency therefrom and to facilitate sampling after frequency division. After the frequency division processing is performed on the recovered clock signal, the clock frequency of the clock signal obtained by frequency division can be calculated, and the calculated clock frequency can be recorded, so that the generation of the corresponding clock signal when no clock signal is recovered is performed according to the recorded clock frequency, and the subsequent checking and acquisition of the related clock frequency are facilitated.
According to the process, if the corresponding recovered clock signal exists at the current time, frequency division processing is carried out on the recovered clock signal; calculating the clock frequency of the clock signal obtained by frequency division, and recording the clock frequency; and if the corresponding clock signal does not exist at the current time, generating the clock signal corresponding to the current time according to the clock signal which is closest to the current time in the recovered clock signals.
It should be noted that the above process can be performed once after recovering the clock signal from each NRZ serial data.
The clock signal recovery method provided in the embodiment of the present application generates a clock signal corresponding to a current time according to a clock signal closest to the current time in a recovered clock signal, and may include:
generating a reference clock according to the clock frequency corresponding to the clock signal closest to the current time in the recovered clock signals;
and generating a clock signal corresponding to the current time according to the reference clock.
In the present application, when the clock signal corresponding to the current time is generated according to the clock signal closest to the current time in the recovered clock signals, specifically, the reference clock may be generated according to the clock frequency corresponding to the clock signal closest to the current time in the recovered clock signals, which is subjected to processing such as frequency division processing. Specifically, the reference clock may be generated by multiplying a clock frequency corresponding to a clock signal closest to the current time in the recovered clock signals by a ratio determined in advance according to the design of the optical fiber communication clock recovery unit for recovering the clock signal from the NRZ serial data. Specifically, the ratio may be 1/32, 1/64, or the like. And when the optical fiber communication clock recovery unit determines, the corresponding proportion is also determined. The phase-locked loop circuit inside the optical fiber communication clock recovery unit generally has a frequency divider with a fixed dividing ratio, and the frequency divider determines the ratio of the reference clock and the output clock signal. Specifically, refer to fig. 4, which shows a logic diagram of a basic configuration of the optical fiber communication clock recovery unit provided in the embodiment of the present application, where the phase frequency detector, the low pass filter, the frequency divider, and the voltage controlled oscillator form a phase-locked loop circuit, a clock signal output by the voltage controlled oscillator is divided into two parts, one part outputs a clock signal output by the optical fiber communication clock recovery unit, the other part is frequency-divided by the frequency divider and then inputs the clock signal into the phase frequency detector (i.e., the frequency divider signal is input into the phase frequency detector), the other input of the phase frequency detector is either NRZ serial data or a reference clock, and the frequency divider signal input into the phase frequency detector and the reference clock have equal frequencies. Therefore, after the optical fiber communication clock recovery unit determines, the input frequency of the reference clock is determined. As can be seen from the above description, the ratio determined by the design of the optical fiber communication clock recovery unit itself is specifically determined by the frequency divider included in the phase-locked loop circuit in the optical fiber communication clock recovery unit.
After generating the reference clock from the clock frequency corresponding to the clock signal closest to the current time among the recovered clock signals, which is subjected to the frequency division processing or the like, the clock signal corresponding to the current time may be generated from the generated reference clock, and specifically, the generated reference clock may be used to trigger the optical fiber communication clock recovery unit for recovering the clock signal from the NRZ serial data to generate the clock signal corresponding to the current time. The optical fiber communication clock recovery unit has a phase-locked loop circuit therein, and the phase-locked loop circuit can generate a clock signal according to a reference clock (see fig. 4 and the above description), which is determined by the function of the phase-locked loop circuit.
Through the process, the latest clock output frequency can be still kept in the state that NRZ serial data continues to a certain level, so that the stable output of a clock signal can be ensured, and the clock signal recovery effect is improved.
An embodiment of the present application further provides a clock signal recovery system, see fig. 5, which shows a schematic structural diagram of a clock signal recovery system provided in an embodiment of the present application, and the clock signal recovery system may include a data conversion unit, an optical fiber communication clock recovery unit connected to the data conversion unit, and a clock signal generation unit connected to the optical fiber communication clock recovery unit, where:
a data conversion unit for converting PAM4 serial data into NRZ serial data;
the optical fiber communication clock recovery unit is used for recovering a clock signal from the NRZ serial data;
and the clock signal generating unit is used for generating the clock signal corresponding to the current time according to the clock signal which is closest to the current time in the recovered clock signals if the corresponding clock signal does not exist at the current time.
The embodiment of the present application further provides a clock signal recovery system, which can be used to implement any one of the above clock signal recovery methods, where the clock signal recovery system may include a data conversion unit, an optical fiber communication clock recovery unit connected to the data conversion unit, and a clock signal generation unit connected to the optical fiber communication clock recovery unit.
The data conversion unit is used for converting PAM4 serial data into NRZ serial data and sending the converted NRZ serial data to the optical fiber communication clock recovery unit. The optical fiber communication clock recovery unit is used for recovering a clock signal from the NRZ serial data. The clock signal generating unit is used for generating a clock signal corresponding to the current time according to a clock signal which is closest to the current time in the recovered clock signals if the corresponding clock signal does not exist at the current time.
According to the technical scheme disclosed by the application, the PAM4 serial data is converted into the NRZ serial data, then the clock signal is recovered from the NRZ serial data, namely, the PAM4 signal is converted into the NRZ signal to recover the clock signal, and the NRZ serial data only has high and low level values, so that the clock signal can be recovered relatively simply and reliably, and the synchronism of clock signal recovery can be improved. In addition, when PAM4 serial data is converted into NRZ serial data for clock signal recovery, if no corresponding clock signal exists at the current time, the clock signal corresponding to the current time can be generated according to the clock signal closest to the current time in the recovered clock signals, so as to avoid interruption of the recovered clock signal due to less sampling opportunities caused by conversion of PAM4 serial data into NRZ serial data, that is, to ensure stable output of the clock signal, thereby improving the clock signal recovery effect.
The clock signal recovery system provided in the embodiment of the present application may further include:
and the equalizer is connected with the data conversion unit and is used for carrying out high-frequency compensation on the PAM4 serial data.
The clock signal recovery system provided by the application can further comprise an equalizer connected with the data conversion unit, so that PAM4 serial data are received by the equalizer connected with the data conversion unit, and high-frequency compensation is carried out on PAM4 serial data, and the level change is steeper. Thereafter, the equalizer inputs PAM4 serial data after high frequency compensation to the data conversion unit to convert PAM4 serial data after high frequency compensation into NRZ serial data using the data conversion unit.
The clock signal recovery system provided in the embodiment of the present application may further include:
the frequency divider is used for carrying out frequency division processing on the recovered clock signal;
the clock signal generating unit may include:
and the FPGA is connected with the frequency divider and used for calculating the clock frequency of the clock signal obtained by frequency division and recording the clock frequency.
The clock signal recovery system provided by the application can further comprise a frequency divider, so that the frequency divider is used for carrying out frequency division processing on the clock signal recovered by the optical fiber communication clock recovery unit.
The clock signal generating unit included in the clock signal recovery system in the present application may include an FPGA (Field Programmable Gate Array) connected to the frequency divider, and the FPGA may calculate the clock frequency of the clock signal obtained by frequency division and record the clock frequency.
In the clock signal recovery system provided by the embodiment of the present application, the clock signal generating unit may further include a clock generator connected to the FPGA;
the FPGA is also used for controlling the clock generator to generate a reference clock according to the clock frequency corresponding to the clock signal which is closest to the current time in the recovered clock signals, and the reference clock is input to the optical fiber communication clock recovery unit by the clock generator;
and the optical fiber communication clock recovery unit is used for generating a clock signal corresponding to the current time according to the reference clock.
In the clock signal recovery system provided by the present application, the clock signal generating unit may further include a clock generator connected to the FPGA.
If the corresponding clock signal exists at the current time, the frequency divider performs frequency division processing on the clock signal recovered by the optical fiber communication clock recovery unit, the FPGA calculates the clock frequency of the clock signal obtained by frequency division, and the FPGA records the clock frequency; if no corresponding clock signal exists at the current time, the FPGA controls a clock generator connected with the FPGA to generate a reference clock according to the clock frequency corresponding to the clock signal closest to the current time in the recovered clock signals, and then the reference clock is input into the optical fiber communication clock recovery unit by the clock generator, so that the optical fiber communication clock recovery unit generates the clock signal corresponding to the current time according to the reference clock
According to the clock signal recovery system provided by the embodiment of the application, the data conversion unit is specifically a limiting amplifier.
In the clock signal recovery system provided by the present application, the data conversion unit may be specifically a limiting amplifier, so as to convert PAM4 serial data into NRZ serial data by using the limiting amplifier.
It should be noted that for the description of the relevant parts in the clock signal recovery system provided by the present application, reference may be made to the detailed description of the corresponding parts in the clock signal recovery method provided by the embodiments of the present application, and details are not repeated herein.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include elements inherent in the list. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. In addition, parts of the technical solutions provided in the embodiments of the present application that are consistent with implementation principles of corresponding technical solutions in the prior art are not described in detail, so as to avoid redundant description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A clock signal recovery method, comprising:
converting PAM4 serial data into NRZ serial data;
recovering a clock signal from the NRZ serial data;
and if the corresponding clock signal does not exist at the current time, generating the clock signal corresponding to the current time according to the clock signal which is closest to the current time in the recovered clock signals.
2. The clock signal recovery method of claim 1, further comprising, before converting PAM4 serial data to NRZ serial data:
and performing high-frequency compensation on the PAM4 serial data.
3. The clock signal recovery method of claim 1, further comprising, after recovering a clock signal from the NRZ serial data:
carrying out frequency division processing on the recovered clock signal;
and calculating the clock frequency of the clock signal obtained by frequency division, and recording the clock frequency.
4. The method for recovering a clock signal according to claim 3, wherein generating the clock signal corresponding to the current time according to the clock signal closest to the current time in the recovered clock signals comprises:
generating a reference clock according to the clock frequency corresponding to the clock signal which is closest to the current time in the recovered clock signals;
and generating a clock signal corresponding to the current time according to the reference clock.
5. A clock signal recovery system is characterized by comprising a data conversion unit, an optical fiber communication clock recovery unit connected with the data conversion unit and a clock signal generation unit connected with the optical fiber communication clock recovery unit, wherein:
the data conversion unit is used for converting PAM4 serial data into NRZ serial data;
the optical fiber communication clock recovery unit is used for recovering a clock signal from the NRZ serial data;
the clock signal generating unit is used for generating the clock signal corresponding to the current time according to the clock signal which is closest to the current time in the recovered clock signals if the corresponding clock signal does not exist at the current time.
6. The clock signal recovery system of claim 5, further comprising:
and the equalizer is connected with the data conversion unit and is used for performing high-frequency compensation on the PAM4 serial data.
7. The clock signal recovery system of claim 5, further comprising:
the frequency divider is used for carrying out frequency division processing on the recovered clock signal;
the clock signal generation unit includes:
and the FPGA is connected with the frequency divider and used for calculating the clock frequency of the clock signal obtained by frequency division and recording the clock frequency.
8. The clock signal recovery system of claim 7 wherein the clock signal generation unit further comprises a clock generator coupled to the FPGA;
the FPGA is further used for controlling the clock generator to generate a reference clock according to the clock frequency corresponding to the clock signal closest to the current time in the recovered clock signals, and the reference clock is input to the optical fiber communication clock recovery unit by the clock generator;
and the optical fiber communication clock recovery unit is used for generating a clock signal corresponding to the current time according to the reference clock.
9. The clock signal recovery system according to claim 5, wherein the data conversion unit is embodied as a limiting amplifier.
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| US9184906B1 (en) * | 2014-09-22 | 2015-11-10 | Oracle International Corporation | Configurable pulse amplitude modulation clock data recovery |
| CN210518344U (en) * | 2019-09-20 | 2020-05-12 | 武汉光迅科技股份有限公司 | 100G-QSFP28 optical transmission module based on PAM4 |
| CN111371523A (en) * | 2018-12-25 | 2020-07-03 | 深圳市中兴微电子技术有限公司 | Clock signal processing device and method |
| US20210288783A1 (en) * | 2020-03-13 | 2021-09-16 | Anritsu Corporation | Clock recovery device, an error rate measurement device, a clock recovery method, and an error rate measurement method. |
| CN214591376U (en) * | 2020-12-25 | 2021-11-02 | 北京国科天迅科技有限公司 | Circuit for converting PAM3 level signal into NRZ level signal |
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2022
- 2022-07-25 CN CN202210876714.3A patent/CN114944973B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9184906B1 (en) * | 2014-09-22 | 2015-11-10 | Oracle International Corporation | Configurable pulse amplitude modulation clock data recovery |
| CN111371523A (en) * | 2018-12-25 | 2020-07-03 | 深圳市中兴微电子技术有限公司 | Clock signal processing device and method |
| CN210518344U (en) * | 2019-09-20 | 2020-05-12 | 武汉光迅科技股份有限公司 | 100G-QSFP28 optical transmission module based on PAM4 |
| US20210288783A1 (en) * | 2020-03-13 | 2021-09-16 | Anritsu Corporation | Clock recovery device, an error rate measurement device, a clock recovery method, and an error rate measurement method. |
| CN214591376U (en) * | 2020-12-25 | 2021-11-02 | 北京国科天迅科技有限公司 | Circuit for converting PAM3 level signal into NRZ level signal |
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Address after: Building 5, No. 1508, Xiangjiang Road, Suzhou High-tech Zone, Suzhou City, Jiangsu Province 215129 Patentee after: Suzhou Lianxun Instrument Co.,Ltd. Address before: 215129 Building 1, No. 1508, Xiangjiang Road, high tech Zone, Suzhou, Jiangsu Patentee before: STELIGHT INSTRUMENT Inc. |