CN114944830B - Filter circuit - Google Patents

Filter circuit Download PDF

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Publication number
CN114944830B
CN114944830B CN202210860211.7A CN202210860211A CN114944830B CN 114944830 B CN114944830 B CN 114944830B CN 202210860211 A CN202210860211 A CN 202210860211A CN 114944830 B CN114944830 B CN 114944830B
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resistor
circuit
amplifier
filter circuit
voltage
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CN114944830A (en
Inventor
周爵
刘欢
李飞宇
陈君涛
甄建宇
孙诗强
王滔
朱安康
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San Microelectronics Technology Suzhou Co ltd
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San Microelectronics Technology Suzhou Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H03H11/1217—Frequency selective two-port networks using amplifiers with feedback using a plurality of operational amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H03H11/126—Frequency selective two-port networks using amplifiers with feedback using a single operational amplifier

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Networks Using Active Elements (AREA)

Abstract

The invention discloses a filter circuit. The filter circuit includes: the voltage sampling circuit, the signal amplifying circuit and the converting circuit; the voltage sampling circuit comprises a voltage division resistance unit and a filtering unit, the voltage division resistance unit is connected between input voltage and a ground end, the voltage division resistance unit comprises a first resistor and a second resistor which are connected in series, the filtering unit comprises a third resistor and a first capacitor which are connected in series, the other end of the third resistor is connected with the first resistor and the second resistor, the other end of the first capacitor is grounded, and the third resistor is a high-resistance resistor; the first input end of the signal amplification circuit is connected with the third resistor and the first capacitor, the second input end of the signal amplification circuit is connected with the first resistor and the second resistor, and the output end of the signal amplification circuit is connected with the control end of the conversion circuit; the conversion circuit is connected between the input voltage and the ground terminal. In the filter circuit provided by the invention, the area of the capacitor polar plate is reduced, so that the filter circuit is small in size and is suitable for being integrated in a chip.

Description

Filter circuit
Technical Field
The invention relates to the technical field of filtering, in particular to a filtering circuit.
Background
In recent years, as various electronic devices applied to the civil field and the military field have higher and higher requirements for high performance, miniaturization, and low power consumption, the performance requirements of people on integrated circuits have been increased.
The integrated circuit chip is used as a core component of electronic equipment, the requirement of the inside of the chip on a power supply is higher and higher, and whether the power supply voltage is stable or not even directly influences the performance of the whole chip.
However, the power supply voltage has a problem of insufficient power supply rejection ratio at low frequency, and in order to eliminate ripple signals in the power supply voltage and improve the power supply rejection ratio, a filter circuit is usually externally mounted on a chip. In order to achieve the desired filtering effect, the size of the filter circuit is very large and cannot be integrated in a chip.
Disclosure of Invention
The invention provides a filter circuit which is beneficial to integration of the filter circuit in a chip.
According to an aspect of the present invention, there is provided a filter circuit including: the voltage sampling circuit, the signal amplifying circuit and the converting circuit;
the voltage sampling circuit comprises a voltage division resistance unit and a filtering unit, the voltage division resistance unit is connected between input voltage and a ground end, the voltage division resistance unit comprises a first resistor and a second resistor which are connected in series, the filtering unit comprises a third resistor and a first capacitor which are connected in series, the other end of the third resistor is connected with the first resistor and the second resistor, the other end of the first capacitor is connected with the ground end, and the third resistor is a high-resistance resistor;
a first input end of the signal amplification circuit is connected with the third resistor and the first capacitor, a second input end of the signal amplification circuit is connected with the first resistor and the second resistor, and an output end of the signal amplification circuit is connected with a control end of the conversion circuit;
the conversion circuit is connected between the input voltage and the ground terminal.
Further, the resistance value of the third resistor is larger than 1000 ohms.
Further, the filter circuit further includes: a reference circuit;
the reference circuit is connected between the input voltage and the ground terminal.
Further, the signal amplifying circuit comprises a first amplifier, a second amplifier and a third amplifier;
the first output end of the first amplifier is connected with the non-inverting input end of the second amplifier, and the second output end of the first amplifier is connected with the inverting input end of the second amplifier;
the non-inverting input end of the first amplifier and the non-inverting input end of the third amplifier are connected with the third resistor and the first capacitor, and the inverting input end of the first amplifier and the inverting input end of the third amplifier are connected with the first resistor and the second resistor;
and the output end of the second amplifier and the output end of the third amplifier are connected with the control end of the conversion circuit together.
Further, the first amplifier is a fully differential folded cascode amplifier;
the second amplifier and the third amplifier are both single-ended output amplifiers.
Further, the transfer function of the output end of the signal amplification circuit is formula (1):
Figure 755335DEST_PATH_IMAGE001
；
A v1 =g m1 r oa ；
A v2 =g m2 r ob ；
A v3 =g m3 r ob ；
ω p1 =1/(c oa r oa )；
ω p2 =1/(c ob r ob )；
a is the inverting input of the second amplifier, b is the output of the second amplifier, s is a variable related to angular frequency, A v1 、A v2 、A v3 The voltage amplification factor, omega, of the first amplifier, the second amplifier and the third amplifier in sequence p1 、ω p2 In sequenceAngular frequencies of a pole a and b, g m1 、g m2 、g m3 Transconductances r of the first, second and third amplifiers in that order oa 、r ob Equivalent output resistance of a pole and b pole in sequence, c oa 、c ob The equivalent output capacitance of the a pole and the b pole in sequence.
Further, the conversion circuit includes a conversion transistor.
Further, the width-to-length ratio of the conversion transistor is greater than 100.
Further, the conversion transistor is a PMOS.
Further, the input impedance R of the filter circuit in Is represented by formula (2):
Figure 176739DEST_PATH_IMAGE002
；
R 1 is the resistance value, R, of the first resistor 2 Is the resistance value of the second resistor, A V Is the voltage amplification factor, g, of the signal amplification circuit m Is the equivalent transconductance of the conversion circuit.
In the filter circuit provided by the invention, the voltage sampling circuit comprises a voltage dividing resistor unit and a filter unit, wherein the resistor in the filter unit is a high-resistance resistor, so that the capacitance value of a capacitor in the filter unit can be correspondingly greatly reduced, the area of a capacitor plate is reduced, and the filter circuit is small in size and suitable for being integrated in a chip. In addition, the signal amplification circuit can amplify the electric signal output by the voltage sampling circuit and transmit the electric signal to the control end of the conversion circuit, so that the conversion circuit can filter signal noise of a target frequency band, the filtering effect is achieved, the power consumption can be limited, and the influence on the efficiency of a post-stage circuit is avoided.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a filter circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another filter circuit provided by an embodiment of the invention;
FIG. 3 is a schematic diagram of another filter circuit provided by an embodiment of the invention;
FIG. 4 is a diagram illustrating a power management chip according to an embodiment of the present invention;
FIG. 5 is a graph of power supply rejection ratio with and without a filter circuit;
FIG. 6 is a graph of another power supply rejection ratio with or without a filter circuit;
FIG. 7 is a diagram of another power management chip according to an embodiment of the invention;
FIG. 8 is a graph of power supply rejection ratio for yet another filter circuit;
FIG. 9 is a graph of power supply rejection ratio for yet another filter circuit;
FIG. 10 is a schematic diagram of an input impedance of a filter circuit according to an embodiment of the invention;
fig. 11 is a schematic diagram of an input impedance of another filter circuit according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic diagram of a filter circuit according to an embodiment of the present invention. In this embodiment, the filter circuit may be integrated into the power management chip, or may be separately manufactured into a filter chip and integrated into various electric devices, so as to filter the electric signals in the target frequency band, and the application field of the filter circuit is not described herein again.
As shown in fig. 1, the filter circuit provided in this embodiment includes: a voltage sampling circuit 11, a signal amplification circuit 12, and a conversion circuit 13; the voltage sampling circuit 11 comprises a voltage-dividing resistance unit 14 and a filtering unit 15, the voltage-dividing resistance unit 14 is connected between an input voltage VIN and a ground end GND, the voltage-dividing resistance unit 14 comprises a first resistor R11 and a second resistor R12 which are connected in series, the filtering unit 15 comprises a third resistor R13 and a first capacitor C11 which are connected in series, the other end of the third resistor R13 is connected with the first resistor R11 and the second resistor R12, the other end of the first capacitor C11 is connected with the ground end GND, and the third resistor R13 is a high-resistance resistor; a first input end of the signal amplifying circuit 12 is connected with the third resistor R13 and the first capacitor C11, a second input end of the signal amplifying circuit 12 is connected with the first resistor R11 and the second resistor R12, and an output end of the signal amplifying circuit 12 is connected with a control end of the switching circuit 13; the conversion circuit 13 is connected between the input voltage VIN and the ground terminal GND. The third resistor R13 may optionally have a resistance value of more than 1000 ohms.
In this embodiment, the filter circuit includes a voltage sampling circuit 11, the voltage sampling circuit 11 is connected between the input voltage VIN and the ground terminal GND, and the voltage sampling circuit 11 is configured to sample the input voltage VIN and provide a filtered electrical signal for a subsequent circuit. If the filter circuit is applied to the power management chip, the voltage sampling circuit 11 samples the ripple voltage signal from the power supply and provides a dc bias voltage for the subsequent circuit. The voltage sampling circuit 11 includes a voltage-dividing resistance unit 14 and a filter unit 15.
The voltage-dividing resistance unit 14 is connected between the input voltage VIN and the ground terminal GND, and the voltage-dividing resistance unit 14 includes a first resistor R11 and a second resistor R12 connected in series. The first end of the first resistor R11 is connected to the input voltage VIN, the first end of the second resistor R12 is connected to the ground GND, and the second end of the first resistor R11 is connected to the second end of the second resistor R12. The voltage-dividing resistance unit 14 divides the input voltage VIN such that the voltage output from the connection end of the first resistance R11 and the second resistance R12 is different from the input voltage VIN. Specifically, the voltage dividing resistor unit 14 samples the ripple voltage signal, and the sampled signal is a dc offset voltage, that is, the second end of the first resistor R11 outputs the dc offset voltage.
The filter unit 15 is connected between the voltage dividing resistor unit 14 and the ground terminal GND, and the filter unit 15 includes a third resistor R13 and a first capacitor C11 connected in series. A first end of the third resistor R13 is connected to the second end of the first resistor R11 and the second end of the second resistor R12, a first end of the first capacitor C11 is grounded GND, and a second end of the third resistor R13 is connected to the second end of the first capacitor C11. The filtering unit 15 may be selected as a low-pass filtering unit. The filtering unit 15 can filter signals of a target frequency band and a higher frequency, does not affect the dc bias voltage output by the voltage dividing resistance unit 14, and can also prevent the signals from being common mode input signals.
It should be noted that, the third resistor R13 in the filtering unit 15 may be a high-resistance resistor during design, and the higher the resistance of the third resistor R13 is, the smaller the capacitance of the first capacitor C11 may be, and then the smaller the size of the filtering unit 15 may be, based on which, the smaller the size of the filtering circuit may be, and the filtering circuit may be integrated inside a chip. In addition, the voltage dividing resistor unit 14 is connected between the filter unit 15 and the input voltage VIN, and the filter unit 15 is not directly connected in series to the input voltage VIN, so that the power consumption of the filter unit 15 is low, and the magnitude of the dc bias voltage output by the voltage dividing resistor unit 14 is hardly affected.
The third resistor R13 may optionally have a value of more than 1000 ohms. The larger the resistance value of the third resistor R13 is, the smaller the capacitance value of the first capacitor C11 is in the same filtering range. The resistance values of the resistors in the filter unit are 1 ohm and 1000000 ohms for example.
The filtering range, namely the target frequency band, of the filtering unit is assumed to be 100Hz to 1MHz. If the resistance of the resistor in the filter unit is 1 ohm, the following description is given:
(1/jwc)/(R+jwc)≤(1/100)；
after transformation, 1/jwc is not more than R (1/100);
r =1 Ω, to obtain, 1/jwc ≤ 0.01 Ω;
when w =100Hz, the capacitance value c of the capacitor in the filter unit is more than or equal to 1mF;
in this case, the capacitance of the capacitor in the filter unit is as high as 1mF, and the plate area of the capacitor is large, which results in large size of the whole filter unit, and the filter unit cannot be integrated into a chip or other chips.
Assume that the filtering range of the filtering unit 15 is 100Hz to 1MHz. If the resistance of the third resistor R13 in the filter unit 15 is 1000000 ohms, the following description is given:
(1/jwc)/(R+jwc)≤(1/100)；
after transformation, 1/jwc is not more than R (1/100);
r =1000000 Ω to obtain 1/jwc ≤ 10000 Ω;
when w =100Hz, the capacitance C of the first capacitor C11 in the filter unit 15 is greater than or equal to 0.000001mF, i.e. C is greater than or equal to 1nF;
at this time, the capacitance value of the first capacitor C11 in the filtering unit 15 can be as low as 1nF, the plate area of the capacitor of 1nF is very small compared with the plate area of the capacitor of 1mF, and the size difference between the 1 ohm resistor and the 1000000 ohm resistor is not large, so that the overall size of the filtering unit 15 can be made very small, and the filtering unit is suitable for integration into a chip or other chips. It follows that the filter circuit can be reduced in size and integrated in a chip.
Optionally, the resistance of the third resistor R13 ranges from 100K Ω to 400K Ω, so that the capacitance of the first capacitor C11 can be as low as about 1 nF. But not limited thereto, those skilled in the art can reasonably select the resistance of the third resistor according to the product requirement.
In this embodiment, the filter circuit further includes a signal amplification circuit 12. The signal amplification circuit 12 is connected between the voltage sampling circuit 11 and the conversion circuit 13, and the signal amplification circuit 12 amplifies the filtered electric signal. If the filter circuit is applied to the power management chip, the signal amplifying circuit 12 amplifies the dc bias voltage output by the voltage sampling circuit 11.
A first input end of the signal amplifying circuit 12 is connected to the filtering unit 15, specifically, the first input end of the signal amplifying circuit 12 is connected to a second end of the third resistor R13 and a second end of the first capacitor C11; a second input terminal of the signal amplifying circuit 12 is connected to the voltage dividing resistor unit 14, and specifically, the second input terminal of the signal amplifying circuit 12 is connected to a second terminal of the first resistor R11 and a second terminal of the second resistor R12. As described above, the voltage dividing resistance unit 14 filters the sampled dc bias voltage through the filtering unit 15 and transmits the filtered dc bias voltage to the first input terminal of the signal amplifying circuit 12, and meanwhile, the voltage dividing resistance unit 14 directly transmits the sampled dc bias voltage to the second input terminal of the signal amplifying circuit 12. The two input terminals of the signal amplifying circuit 12 can receive different electrical signals, so that the output terminal of the signal amplifying circuit 12 outputs normally. The signal amplified by the signal amplifying circuit 12 is transmitted to the control terminal of the converting circuit 13. It should be noted that the signal amplifying circuit 12 has a function of amplifying a signal, so that negative feedback is enhanced, and output impedance can be further reduced.
In this embodiment, the filter circuit further includes a conversion circuit 13. The control terminal of the converting circuit 13 is connected to the output terminal of the signal amplifying circuit 12, and the converting circuit 13 is connected between the input voltage VIN and the ground GND. The conversion circuit 13 provides a path from the input voltage VIN to the ground terminal GND. The impedance of the path to signals outside the target frequency band is large, so that signals outside the target frequency band in the input voltage VIN cannot be transmitted to the ground terminal GND through the conversion circuit 13, and signals outside the target frequency band in the input voltage VIN cannot be filtered by the filter circuit. The impedance of a path from the input voltage VIN to the ground GND is small for a signal within a target frequency band, so that a signal within the target frequency band in the input voltage VIN is transmitted to the ground GND through the conversion circuit 13, and the signal within the target frequency band in the input voltage VIN is filtered by the filter circuit. The filtering of signal noise of the target frequency band is realized, and the filtering effect is achieved.
Signals outside the selectable target frequency band are direct current signals and extremely low frequency signals, so that the direct current signals and the extremely low frequency signals in the input voltage VIN cannot be filtered by the filter circuit, and the target frequency band and higher frequency signals can be filtered by the filter circuit, so that the filter circuit can limit the size of direct current, further limit power consumption, and avoid affecting the efficiency of a rear-stage circuit.
Fig. 2 is a schematic diagram of another filter circuit according to an embodiment of the present invention. As shown in fig. 2, the optional filter circuit further includes: a reference circuit 16; the reference circuit 16 is connected between the input voltage VIN and the ground GND. The reference circuit 16 may optionally be a reference current source circuit that provides a reference bias current and/or a reference bias voltage for various other structures in the filter circuit.
In the filter circuit provided by the invention, the voltage sampling circuit comprises a voltage dividing resistor unit and a filter unit, wherein the resistor in the filter unit is a high-resistance resistor, so that the capacitance value of a capacitor in the filter unit can be correspondingly greatly reduced, the area of a capacitor plate is reduced, and the filter circuit is small in size and suitable for being integrated in a chip. In addition, the signal amplification circuit can amplify the electric signal output by the voltage sampling circuit and transmit the electric signal to the control end of the conversion circuit, so that the conversion circuit can filter signal noise of a target frequency band, the filtering effect is achieved, the power consumption can be limited, and the influence on the efficiency of a post-stage circuit is avoided.
Fig. 3 is a schematic diagram of another filter circuit according to an embodiment of the present invention. As shown in fig. 3, the optional signal amplifying circuit 12 includes a first amplifier 17, a second amplifier 18, and a third amplifier 19; a first output end of the first amplifier 17 is connected with a non-inverting input end of the second amplifier 18, and a second output end of the first amplifier 17 is connected with an inverting input end of the second amplifier 18; the non-inverting input end of the first amplifier 17 and the non-inverting input end of the third amplifier 19 are commonly connected with a third resistor R13 and a first capacitor C11, and the inverting input end of the first amplifier 17 and the inverting input end of the third amplifier 19 are commonly connected with a first resistor R11 and a second resistor R12; the output of the second amplifier 18 and the output of the third amplifier 19 are connected in common to the control terminal of the switching circuit 13. The first amplifier 17 may be selected to be a fully differential folded cascode amplifier; the second amplifier 18 and the third amplifier 19 are both single-ended output amplifiers.
In the present embodiment, the signal amplification circuit 12 includes 3 amplifiers. The first amplifier 17 and the second amplifier 18 are connected in series, and the first amplifier 17 and the third amplifier 19 are connected in parallel. Specifically, the first amplifier 17 is a double-ended output amplifier, and the second amplifier 18 and the third amplifier 19 are both single-ended output amplifiers.
For the first amplifier 17, the non-inverting input terminal thereof is connected to the filtering unit 15, i.e., between the third resistor R13 and the first capacitor C11, the inverting input terminal thereof is connected to the voltage dividing resistor unit 14, i.e., between the first resistor R11 and the second resistor R12, and 2 output terminals thereof are respectively connected to the non-inverting input terminal and the inverting input terminal of the second amplifier 18. The non-inverting input end of the first amplifier 17 receives the ripple voltage signal processed by the voltage dividing resistance unit 14 and the filtering unit 15, the inverting input end of the first amplifier 17 receives the ripple voltage signal processed by the voltage dividing resistance unit 14, and the amplified electric signal is transmitted to the second amplifier 18.
The output of the second amplifier 18 and the output of the third amplifier 19 are connected in common to the control terminal of the switching circuit 13. The output of the second amplifier 18 and the output of the third amplifier 19 are connected together and the equivalent output impedance is the same, both amplifiers produce a pole b. The second amplifier 18 amplifies the received electric signal and outputs the amplified electric signal.
For the third amplifier 19, the non-inverting input terminal thereof is connected to the filtering unit 15, i.e., between the third resistor R13 and the first capacitor C11, the inverting input terminal thereof is connected to the voltage dividing resistor unit 14, i.e., between the first resistor R11 and the second resistor R12, and 1 output terminal thereof is connected to the converting circuit 13. The non-inverting input terminal of the third amplifier 19 receives the ripple voltage signal processed by the voltage dividing resistance unit 14 and the filtering unit 15, and the inverting input terminal of the third amplifier 19 receives the ripple voltage signal processed by the voltage dividing resistance unit 14, amplifies the received electric signal, and outputs the amplified electric signal.
Obviously, the dc bias voltage received by the inverting input terminal of the third amplifier 19 is the same as that received by the inverting input terminal of the first amplifier 17, the dc bias voltage received by the non-inverting input terminal of the third amplifier 19 is the same as that received by the non-inverting input terminal of the first amplifier 17, and the dc bias voltage received by the non-inverting input terminal and that received by the inverting input terminal of the first amplifier 17 are different. The filtering unit 15 filters the electrical signal and then transmits the filtered electrical signal to the non-inverting input terminal of the first amplifier 17, so that the dc bias voltage is not affected, and meanwhile, the signals received by the 2 input terminals of the amplifier can be prevented from being common-mode input signals.
The transfer function at the output of the selectable signal amplifying circuit 12 is equation (1):
Figure 314460DEST_PATH_IMAGE001
；
A v1 =g m1 r oa ；
A v2 =g m2 r ob ；
A v3 =g m3 r ob ；
ω p1 =1/(c oa r oa )；
ω p2 =1/(c ob r ob )；
a is the inverting input of the second amplifier 18, b is the output of the second amplifier 18, s is a variable related to the angular frequency, A v1 、A v2 、A v3 Sequentially amplifying the voltages of the first amplifier 17, the second amplifier 18 and the third amplifier 19Number, omega p1 、ω p2 Angular frequencies of pole a and pole b, g m1 、g m2 、g m3 Transconductors r of a first amplifier 17, a second amplifier 18 and a third amplifier 19 in this order oa 、r ob Equivalent output resistance of a pole and b pole in sequence, c oa 、c ob The equivalent output capacitance of the a pole and the b pole in sequence.
As can be seen from the above-mentioned transmission function expression of the output end of the signal amplifying circuit 12, two left half-plane poles and one left half-plane zero exist in the filter circuit, and it is only necessary to adjust at least one of the voltage amplification factor of the first amplifier 17, the voltage amplification factor of the second amplifier 18, and the voltage amplification factor of the third amplifier 19, and compensate ω using the zero p2 That is, the stability of the filter circuit is thus ensured. The three amplifiers have the function of amplifying signals, so that negative feedback is enhanced, and output impedance is further reduced.
Referring to fig. 3, the optional conversion circuit 13 includes a conversion transistor M1. The width-to-length ratio of the optional conversion transistor M1 is greater than 100. The optional conversion transistor M1 is PMOS.
In this embodiment, the converting circuit 13 is a voltage-to-current converting circuit, and can convert the input voltage VIN into a current signal. Specifically, the conversion circuit 13 includes a conversion transistor M1, a gate of the conversion transistor M1 is commonly connected to the output terminal of the second amplifier 18 and the output terminal of the third amplifier 19, and the conversion transistor M1 is connected between the input voltage VIN and the ground terminal GND. The optional switching transistor M1 is PMOS. The amplified electrical signal output from the output terminal of the second amplifier 18 is transmitted to the gate of the converting transistor M1, so that the converting transistor M1 is in a saturation region.
The width-to-length ratio of the optional conversion transistor M1 is 240. But not limited thereto, those skilled in the art can select the width-to-length ratio of the converting transistor M1 according to the product requirement.
The conversion transistor M1 is in a saturation region under the control of the second amplifier 18. Specifically, the converting transistor M1 is connected between the input voltage VIN and the ground terminal GND, and provides a path from the input voltage VIN to the ground terminal GND, so as to convert the ac voltage signal into an ac current signal. When the input voltage VIN is a signal within the target frequency band, the impedance of a path from the input voltage VIN to the ground terminal GND is very small, and at this time, the input voltage VIN is converted into a current signal through the conversion transistor M1 and is transmitted to the ground terminal GND, so that the power supply noise of the target frequency band is directly filtered out, and the filtering effect is achieved. When the input voltage VIN is a direct current signal or a very low frequency signal or other signals outside the target frequency band, the impedance of the path from the input voltage VIN to the ground terminal GND is very large, and at this time, the input voltage VIN cannot be transmitted to the ground terminal GND through the conversion transistor M1, so that the magnitude of the direct current can be limited, the power consumption is further limited, and the influence on the efficiency of a rear-stage circuit is avoided.
In other embodiments, the structure of the conversion circuit is not limited to the conversion transistor, and the conversion circuit may also be other alternative structures; alternatively, the converting transistor may be an NMOS, and the width-to-length ratio is not limited to be greater than 100, and those skilled in the art can design the structure and operating parameters of the converting circuit and/or the converting transistor appropriately according to the product requirement.
Input impedance R of selectable filter circuit in Is represented by formula (2):
Figure 776665DEST_PATH_IMAGE002
；
R 1 is the resistance value of the first resistor, R 2 Is the resistance value of the second resistor, A V Is the voltage amplification factor, g, of the signal amplification circuit m Is the equivalent transconductance of the conversion circuit.
As described above, the negative sign-characterizing filter circuit loop in equation (2) is a negative feedback loop, which can ensure the stability of the circuit. A. The V Is the voltage amplification factor, g, of the signal amplification circuit m Is the equivalent transconductance of the conversion transistor M1. It can be understood that the operating parameters of the filter capacitor may change if the resistance of the resistor, the capacitance of the capacitor, the operating parameters of the transistor, the amplification factor of the amplifier, etc. in the filter circuit change.
In this embodiment, the filter circuit is a low-frequency low-resistance circuit, and can be integrated in a chip. The filter circuit can also sample an alternating voltage signal, and can solve the problem of direct current offset of a post-stage differential operational amplifier while sampling the alternating voltage signal, so that the direct current working point of the small-signal amplifier is ensured.
Fig. 4 is a schematic diagram of a power management chip according to an embodiment of the present invention. As shown in fig. 4, the power management chip includes the filter circuit 21 and the low dropout regulator 22 according to any of the above embodiments. It should be noted that the power management chip is not limited to the above structure, and includes other structures, which are not described herein again; in addition, the structure cooperating with the filter circuit 21 is not limited to the LDO22, but may be other structures, which are not specifically exemplified herein.
The filter circuit 21 is connected between the input voltage VIN and the ground GND, the low dropout regulator 22 is connected between the input voltage VIN and the output voltage VOUT, and one end of the low dropout regulator 22 is connected to the ground GND.
In this embodiment, the filter circuit 21 is a low-frequency integratable low-resistance circuit, and can be integrated in the power management chip, so as to effectively improve the power supply rejection ratio of the power management chip with no voltage drop and relatively low power consumption. The power management chip can accurately detect the alternating current signal in the input voltage VIN in real time, and perform filtering processing on the input voltage VIN through the filtering circuit 21. Therefore, the power management chip can obtain an input voltage VIN optimized in the target frequency band, and the power supply rejection ratio of the power management chip in the target frequency band is greatly improved. The filter circuit 21 is integrated in the power management chip, so that an external filter capacitor is not needed, external components are reduced, and a large amount of cost can be saved. In addition, the filter circuit 21 is a parallel filter circuit, and is connected in parallel to the input voltage VIN, so that the input voltage VIN is preprocessed without affecting other circuits, and the filter circuit has a wide application range and strong universality.
The advantages of the filter circuit 21 in the present invention in the power management chip will be described below by comparing with specific examples.
In this embodiment, the optional filter circuit 21 is designed and manufactured by a 0.18 μm BCD process, and the filter circuit 21 and the LDO22 are connected in parallel between the input voltage VIN and the ground GND. The circuit structure of the filter circuit 21 is as described in any of the above embodiments, and is not described herein again.
Fig. 5 is a graph of power supply rejection ratio with or without a filter circuit. As shown in fig. 5, the abscissa indicates the frequency freq, the ordinate indicates the power supply rejection ratio PSRR, the curve 23 indicates the power supply rejection ratio curve of the filter-circuit-less power supply management chip, and the curve 24 indicates the power supply rejection ratio curve of the power supply management chip including the filter circuit 21 shown in fig. 4. From curve 24, it can be seen that the power management chip including the filter circuit 21 has a significantly optimized power supply rejection ratio of the LDO22 from 100Hz to 1MHz. At the frequency x position, curve 24 has a maximum optimization of the power supply rejection ratio of more than 30dB compared to curve 23. Optionally, the input voltage VIN is equal to 5V.
Fig. 6 is a graph of power supply rejection ratio with or without a filter circuit. The difference from fig. 5 is that the input voltage VIN in fig. 6 is equal to 4V. Curve 25 is a power supply rejection ratio curve of the power supply management chip without the filter circuit, and curve 26 is a power supply rejection ratio curve of the power supply management chip including the filter circuit 21. As can be seen from the curve 26, the power management chip including the filter circuit 21 also has the effect of increasing the power supply rejection ratio at a low input voltage VIN.
Fig. 7 is a schematic diagram of another power management chip according to an embodiment of the invention. As shown in fig. 7, the power management chip includes the filter circuit 31, the low dropout regulator 32 and the filter capacitor 33 according to any of the above embodiments.
The filter circuit 31 is connected between an input voltage VIN and a ground terminal GND, the low dropout regulator 32 is connected between the input voltage VIN and an output voltage VOUT, and one terminal of the low dropout regulator 32 is connected to the ground terminal GND. The filter capacitor 33 is connected between the input voltage VIN and the ground GND.
In this embodiment, the filter circuit 31 is a low-frequency integratable low-resistance circuit, and can be integrated in the power management chip, so that the power consumption is relatively low, and the power supply rejection ratio of the power management chip can be effectively improved. The power management chip can obtain an input voltage VIN optimized in the target frequency band, so that the power supply rejection ratio of the power management chip in the target frequency band is greatly improved.
The advantages of the filter circuit 31 in the present invention in the power management chip will be described below by comparing with specific examples.
In this embodiment, the optional filter circuit 31 is designed and manufactured by a 0.18 μm BCD process, and the filter circuit 31 and the LDO32 are connected in parallel between the input voltage VIN and the ground GND. The circuit structure of the filter circuit 31 is as described in any of the above embodiments, and is not described herein again.
Fig. 8 is a graph showing the power supply rejection ratio of the filter circuit. As shown in fig. 8, the abscissa indicates the frequency freq, the ordinate indicates the power supply rejection ratio PSRR, the curve 34 indicates the power supply rejection ratio curve of the filter-circuit-less power supply management chip, and the curve 35 indicates the power supply rejection ratio curve of the power supply management chip including the filter circuit 31 shown in fig. 7. As can be seen from the curve 35, the power management chip including the filter circuit 31 significantly improves the power supply rejection ratio of the LDO32 in the target frequency band in the frequency band of 100Hz to 100 KHz. The input voltage VIN is equal to 5V.
The optimizable band of curve 35 in fig. 8, 100Hz to 100KHz is narrower than the optimizable band of curve 24, 100Hz to 1MHz, compared to curve 24 in fig. 5. The reason for this is that the capacitance of the filter capacitor 33 is large, and the equivalent resistance in the MHz band is small, even lower than that of the filter circuit 31. Then the power supply rejection ratio PSRR is increased in the MHz band mainly by the filter capacitor 33.
Fig. 9 is a graph showing the power supply rejection ratio of the filter circuit. The difference from fig. 8 is that the input voltage VIN in fig. 9 is equal to 4V. Curve 36 is a power supply rejection ratio curve of the power supply management chip without the filter circuit, and curve 37 is a power supply rejection ratio curve of the power supply management chip including the filter circuit 31. As can be seen from the curve 37, the power management chip including the filter circuit 31 also has the effect of increasing the power supply rejection ratio at a low input voltage VIN.
Fig. 10 is a schematic diagram of an input impedance of a filter circuit according to an embodiment of the present invention. The filter circuit in this embodiment is the filter circuit described in any of the above embodiments, and as shown in fig. 10, the abscissa represents frequency freq, the ordinate resistance R represents Rin in the input impedance formula (2), and the input impedance of the filter circuit decreases with increasing frequency from 1Hz to 1 GHz. Specifically, at an extremely low frequency, the input impedance is extremely large, so that the direct current characteristic of the power management chip is not influenced; as the frequency increases, the input impedance of the filter circuit decreases rapidly; after higher frequency, the equivalent input impedance will increase due to the limited operational amplifier bandwidth and the reduced gain, and at this time, the effect of optimizing the power supply rejection ratio will not be improved.
Fig. 11 is a schematic diagram of an input impedance of another filter circuit according to an embodiment of the present invention. The filter circuit in this embodiment is the filter circuit described in any of the above embodiments, and as shown in fig. 11, the input impedance of the filter circuit at 100Hz to 1MHz decreases with increasing frequency. Specifically, the input impedance of the filter circuit is very low from 100Hz to 1MHz, the maximum impedance is not more than 0.65 ohm, the minimum impedance is less than 0.07 ohm, and the impedance of the filter circuit exceeds 1 ohm no matter the input voltage VIN or LDO, so the filter circuit has obvious improvement effect on the power supply rejection ratio from 100Hz to 1MHz.
The invention provides a parallel ripple filter circuit which can be integrated into a power management chip and solves the problem that the power supply rejection ratio is lower at low frequency; the chip can be manufactured independently, and the power supply rejection ratio of various power supply management chips is improved.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A filter circuit, comprising: the device comprises a voltage sampling circuit, a signal amplifying circuit and a conversion circuit;
the voltage sampling circuit comprises a voltage division resistance unit and a filtering unit, the voltage division resistance unit is connected between input voltage and a ground end, the voltage division resistance unit comprises a first resistor and a second resistor which are connected in series, the filtering unit comprises a third resistor and a first capacitor which are connected in series, the other end of the third resistor is connected with the first resistor and the second resistor, the other end of the first capacitor is connected with the ground end, and the third resistor is a high-resistance resistor;
a first input end of the signal amplifying circuit is connected with the third resistor and the first capacitor, a second input end of the signal amplifying circuit is connected with the first resistor and the second resistor, and an output end of the signal amplifying circuit is connected with a control end of the conversion circuit;
the conversion circuit is connected between the input voltage and the ground terminal;
the signal amplification circuit comprises a first amplifier, a second amplifier and a third amplifier;
the first output end of the first amplifier is connected with the non-inverting input end of the second amplifier, and the second output end of the first amplifier is connected with the inverting input end of the second amplifier;
the non-inverting input end of the first amplifier and the non-inverting input end of the third amplifier are connected with the third resistor and the first capacitor, and the inverting input end of the first amplifier and the inverting input end of the third amplifier are connected with the first resistor and the second resistor;
and the output end of the second amplifier and the output end of the third amplifier are connected with the control end of the conversion circuit together.
2. The filter circuit of claim 1, wherein the third resistor has a resistance greater than 1000 ohms.
3. The filter circuit of claim 1, further comprising: a reference circuit;
the reference circuit is connected between the input voltage and the ground.
4. The filter circuit of claim 1, wherein the first amplifier is a fully differential folded cascode amplifier;
the second amplifier and the third amplifier are both single-ended output amplifiers.
5. The filter circuit of claim 1, wherein the transfer function at the output of the signal amplification circuit is given by equation (1):
Figure DEST_PATH_IMAGE002
；
A v1 =g m1 r oa ；
A v2 =g m2 r ob ；
A v3 =g m3 r ob ；
ω p1 =1/(c oa r oa )；
ω p2 =1/(c ob r ob )；
a is the inverting input of the second amplifier, b is the output of the second amplifier, s is a variable related to angular frequency, A v1 、A v2 、A v3 The voltage amplification factor, omega, of the first amplifier, the second amplifier and the third amplifier in sequence p1 、ω p2 Angular frequencies of pole a and pole b, g m1 、g m2 、g m3 Transconductances r of the first, second and third amplifiers in that order oa 、r ob Equivalent output resistance of a pole and b pole in sequence, c oa 、c ob The equivalent output capacitance of the a pole and the b pole in sequence.
6. The filter circuit of claim 1, wherein the conversion circuit comprises a conversion transistor.
7. The filter circuit of claim 6, wherein the width-to-length ratio of the conversion transistor is greater than 100.
8. The filter circuit of claim 6, wherein the conversion transistor is a PMOS.
9. Filter circuit according to claim 1, characterized in that the input impedance R of the filter circuit in Is represented by formula (2):
Figure DEST_PATH_IMAGE004
；
R 1 is the resistance value, R, of the first resistor 2 Is the resistance value of the second resistor, A V Is the voltage amplification factor, g, of the signal amplification circuit m Is the equivalent transconductance of the conversion circuit.
CN202210860211.7A 2022-07-22 2022-07-22 Filter circuit Active CN114944830B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101436851A (en) * 2007-11-16 2009-05-20 安凡微电子(上海)有限公司 Compensating circuit and method, filter applying the compensating circuit
CN106249793A (en) * 2016-07-20 2016-12-21 瑞声声学科技(深圳)有限公司 Power regulator circuit
CN109002074A (en) * 2018-09-12 2018-12-14 杰华特微电子（杭州）有限公司 Linear voltage-stabilizing circuit, method for stabilizing voltage and the electric power management circuit using it

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101436851A (en) * 2007-11-16 2009-05-20 安凡微电子(上海)有限公司 Compensating circuit and method, filter applying the compensating circuit
CN106249793A (en) * 2016-07-20 2016-12-21 瑞声声学科技(深圳)有限公司 Power regulator circuit
CN109002074A (en) * 2018-09-12 2018-12-14 杰华特微电子（杭州）有限公司 Linear voltage-stabilizing circuit, method for stabilizing voltage and the electric power management circuit using it

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