CN114944342B - Bonding compensation method and device, chip rewiring method and bonding structure - Google Patents

Bonding compensation method and device, chip rewiring method and bonding structure Download PDF

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Publication number
CN114944342B
CN114944342B CN202210856839.XA CN202210856839A CN114944342B CN 114944342 B CN114944342 B CN 114944342B CN 202210856839 A CN202210856839 A CN 202210856839A CN 114944342 B CN114944342 B CN 114944342B
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chip
compensation
rewiring layer
setting position
offset
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CN114944342A (en
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刘天建
田应超
曹瑞霞
王逸群
刘淑娟
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Hubei 3d Semiconductor Integrated Innovation Center Co ltd
Hubei Jiangcheng Laboratory
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Hubei 3d Semiconductor Integrated Innovation Center Co ltd
Hubei Jiangcheng Laboratory
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Priority to PCT/CN2022/135834 priority patent/WO2024016555A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/829—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving monitoring, e.g. feedback loop

Abstract

The embodiment of the disclosure provides a bonding compensation method and device, a chip rewiring method and a bonding structure. The compensation method comprises the following steps: providing at least one bottom chip having a plurality of top chips bonded thereto; acquiring the offset of the actual bonding position of each top chip relative to the bottom chip and the preset error precision of the setting position of the rewiring layer to be formed on each top chip relative to the bottom chip; constructing compensation quantity of the setting position of the rewiring layer to be formed, which contains a pre-compensation parameter, relative to each top chip, and calculating to obtain the pre-compensation parameter by taking the preset error precision as a boundary condition; the pre-compensation parameter is a compensation parameter of the setting position of the rewiring layer to be formed relative to the bottom chip.

Description

Bonding compensation method and device, chip rewiring method and bonding structure
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductor manufacturing, in particular to a bonding compensation method and device, a chip rewiring method and a bonding structure.
Background
Bonding processes may be distinguished by the bonding targets, including wafer to wafer (wafer) bonding, die to wafer (or so-called die) bonding, and die to die (die to die) bonding. Generally, a plurality of top chips may be bonded to corresponding positions on the bottom chip, however, there may be a deviation between the actual bonding position and the predetermined bonding position of each top chip, and the deviation of the actual bonding position of each top chip bonded on the same bottom chip with respect to the predetermined bonding position is different.
Further, in the photolithography process, if the alignment accuracy compensation is performed on the bottom chip as a basic unit, the rewiring requirements of all the top chips bonded on the bottom chip may not be satisfied at the same time, so that the accuracy compensation in the photolithography process becomes a difficult problem.
Disclosure of Invention
In view of the above, the embodiments of the present disclosure provide a bonding compensation method and apparatus, a chip rewiring method, and a bonding structure to solve at least one technical problem in the prior art.
In order to achieve the purpose, the technical scheme of the disclosure is realized as follows:
in a first aspect, an embodiment of the present disclosure provides a bonding compensation method, where the compensation method includes:
providing at least one bottom chip having a plurality of top chips bonded thereto;
acquiring the offset of the actual bonding position of each top chip relative to the bottom chip and the preset error precision of the setting position of the rewiring layer to be formed on each top chip relative to the bottom chip;
constructing compensation quantity of the setting position of the rewiring layer to be formed, which contains a pre-compensation parameter, relative to each top chip, and calculating to obtain the pre-compensation parameter by taking the preset error precision as a boundary condition; the pre-compensation parameter is a compensation parameter of the setting position of the rewiring layer to be formed relative to the bottom chip.
In some embodiments, the constructing the compensation amount of the arrangement position of the redistribution layer to be formed including the pre-compensation parameter with respect to each of the top chips includes:
and decomposing the pre-compensation parameters of the setting position of the rewiring layer to be formed relative to the bottom chip according to the offset of each top chip to obtain the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip.
In some embodiments, the pre-compensation parameters include: a first offset component along a first direction, a second offset component along a second direction, and an angle parameter; wherein the first direction and the second direction are perpendicular to each other.
In some embodiments, the constructing the compensation amount of the arrangement position of the redistribution layer to be formed including the pre-compensation parameter with respect to each of the top chips includes:
decomposing the angle parameters along the first direction and the second direction respectively to obtain a first angle component and a second angle component;
obtaining a first compensation component of the setting position of the rewiring layer to be formed relative to each top chip along the first direction according to the offset, the first offset component and the first angle component of each top chip;
obtaining a second compensation component of the setting position of the rewiring layer to be formed relative to each top chip along the second direction according to the offset, the second offset component and the second angle component of each top chip;
wherein the first compensation component and the second compensation component constitute the compensation amount.
In some embodiments, the calculating the pre-compensation parameter with the preset error precision as a boundary condition includes:
and calculating to obtain the pre-compensation parameter according to the condition that the offset of each top chip and the sum of the compensation quantity of the arrangement position of the rewiring layer to be formed relative to each top chip meet the preset error precision.
In some embodiments, after the calculating the pre-compensation parameter, the compensation method further includes:
calculating to obtain the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip according to the pre-compensation parameters and the offset of each top chip;
and determining the setting position of the rewiring layer to be formed on each top chip according to the offset of each top chip and the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip.
In some embodiments, the predetermined error accuracy of each of the top chips is determined according to a process node of each of the top chips.
In a second aspect, embodiments of the present disclosure provide a bonding compensation apparatus, the apparatus comprising:
the data acquisition module is used for acquiring the offset of the actual bonding position of each top chip relative to the bottom chip and the preset error precision of the setting position of the rewiring layer to be formed on each top chip relative to the bottom chip; wherein a plurality of the top chips are bonded on the bottom chip;
the data calculation module is used for constructing compensation quantities of the setting position of the rewiring layer to be formed, which contains pre-compensation parameters, relative to each top chip, and calculating the pre-compensation parameters by taking the preset error precision as a boundary condition; the pre-compensation parameter is a compensation parameter of the setting position of the rewiring layer to be formed relative to the bottom chip.
In some embodiments, the data calculation module is further configured to calculate, according to the pre-compensation parameter and the offset of each top chip, the compensation amount of the setting position of the redistribution layer to be formed with respect to each top chip;
the device further comprises:
and the wiring module is used for determining the setting position of the rewiring layer to be formed on each top chip according to the offset of each top chip and the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip.
In a third aspect, an embodiment of the present disclosure provides a chip rewiring method, where the wiring method includes:
providing at least one bottom chip having a plurality of top chips bonded thereto;
the setting position of the rewiring layer to be formed on the bottom chip is determined through the bonding compensation method in the technical scheme.
In some embodiments, the routing method further comprises:
determining a compensation amount between the setting position of the rewiring layer to be formed and the offset according to the setting position of the rewiring layer to be formed and the offset of the corresponding top chip;
and compensating the alignment precision of the photoetching process for forming the rewiring layer according to the compensation amount between the setting position of the rewiring layer to be formed and the offset.
In a fourth aspect, an embodiment of the present disclosure provides a bonding structure, including:
at least one bottom chip having a plurality of top chips bonded thereto;
a rewiring layer arranged on each top chip; the compensation quantity between the setting position of the rewiring layer of each top chip and the offset of the actual bonding position of each top chip relative to the bottom chip respectively meets the boundary condition of each top chip; the boundary condition is the preset error precision of the setting position of the rewiring layer on each top chip relative to the bottom chip.
The embodiment of the disclosure provides a bonding compensation method and device, a chip rewiring method and a bonding structure. The compensation method comprises the following steps: providing at least one bottom chip having a plurality of top chips bonded thereto; acquiring the offset of the actual bonding position of each top chip relative to the bottom chip and the preset error precision of the setting position of the rewiring layer to be formed on each top chip relative to the bottom chip; constructing compensation quantity of the setting position of the rewiring layer to be formed, which contains a pre-compensation parameter, relative to each top chip, and calculating to obtain the pre-compensation parameter by taking the preset error precision as a boundary condition; the pre-compensation parameter is a compensation parameter of the setting position of the rewiring layer to be formed relative to the bottom chip. In the embodiment of the disclosure, a plurality of top chips are bonded on the bottom chip, and errors caused by a bonding process cause different deviations of actual bonding positions of the top chips relative to the bottom chip, and the pre-compensation parameters can be calculated by constructing the compensation quantities of the setting positions of the rewiring layers to be formed, which contain the pre-compensation parameters, relative to the top chips, so that the compensation quantities of the top chips can be calculated, and the setting positions of the rewiring layers to be formed on the top chips are compensated respectively.
In this way, when the variations of the top chips bonded to the bottom chip are different, the misalignment of the rewiring layer provided on each top chip bonded to the same bottom chip with respect to the bottom chip is made the same by compensating the alignment accuracy of the photolithography process for forming the rewiring layer on each top chip. In the embodiment of the disclosure, the setting position of the rewiring layer is adjusted to compensate the deviation generated in the process of bonding the top chip to the bottom chip, so that the rewiring method of the chip is optimized, and the performance of the bonding structure is improved.
Drawings
Fig. 1 is a schematic flow chart of a bonding compensation method according to an embodiment of the present disclosure;
FIG. 2 is a partial top view of a bonding structure during bond compensation provided by an embodiment of the present disclosure;
FIG. 3 is a second partial top view of a bonding structure during bond compensation provided by an embodiment of the present disclosure;
FIG. 4 is a partial top view III of a bonding structure during bond compensation provided by an embodiment of the present disclosure;
FIG. 5 is a partial top view of a fourth bonding structure during bond compensation provided by embodiments of the present disclosure;
fig. 6A is a first exploded schematic diagram of a bonding compensation process according to an embodiment of the present disclosure;
fig. 6B is a schematic diagram illustrating a second decomposition principle in the bonding compensation process according to the embodiment of the disclosure;
the drawing comprises the following steps: 210. a bottom chip; 221. a first top chip; 222. a second top chip; 223. a third top chip; 224. a fourth top chip; 225. a fifth top chip; 231. a first actual bonding location; 232. a second actual bonding location; 233. a third actual bonding location; 234. a fourth actual bonding location; 235. a fifth actual bonding location; 241. a first predetermined bonding location; 242. a second predetermined bonding location; 243. a third predetermined bonding location; 244. a fourth predetermined bonding position; 245. a fifth predetermined bonding location; 261. a first set position; 262. a second set position.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the embodiments of the present disclosure and the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without inventive step, are within the scope of the present disclosure.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that the first element, component, region, layer or section is necessarily present in the disclosure.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be set forth in the following description in order to explain the technical aspects of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.
Hybrid Bonding (Hybrid Bonding) is an emerging Bonding technology in the field of semiconductor manufacturing technology, which gradually transfers the Bonding process from Back End (Back End) to Front End (Front End) wafer fabrication, and has many advantages compared to Bump Bonding (Bump Bonding) of Back End package, such as simple process, smaller size, and higher Input/Output (I/O) density. Hybrid bonding is more suitable for fabricating High-power-consumption, High-Bandwidth chips, such as High Bandwidth Memory (HBM), Neural-Network Processing Unit (NPU), Artificial Intelligence (AI) chips, and the like.
After the chips are mixed and bonded to the wafer, the 2.5D small chips (chips) can be continuously wired or stacked on the upper surface of the chips to form 3D small chips, so as to realize three-dimensional integration of the semiconductor device. A chiplet may also be referred to herein as a module chip, and multiple module chips and base chips are packaged together by interconnection technology between the chips. In general, a plurality of top chips may be bonded to corresponding positions on a bottom chip, there may be a deviation between the actual bonding position of the top chip and the predetermined bonding position, and the deviation of the actual bonding position of each top chip bonded on the same bottom chip with respect to the predetermined bonding position is different.
However, in the photolithography process, the alignment accuracy is usually compensated in basic units of exposure areas (shots), in which only one bottom chip is included in one exposure area, but a plurality of top chips may be included in one exposure area. That is, in the photolithography process, alignment accuracy compensation is simultaneously performed for a plurality of top chips different in deviation of an actual bonding position from a predetermined bonding position within an exposure area. Here, performing precision compensation on the exposure region as a basic unit cannot simultaneously satisfy rewiring requirements of all top chips, further causing the problem of precision compensation in the photolithography process.
In view of this, the embodiments of the present disclosure provide a bonding compensation method and apparatus, a chip rewiring method, and a bonding structure.
Referring to fig. 1, fig. 1 is a schematic flow chart of a bonding compensation method according to an embodiment of the disclosure. As shown in fig. 1, an embodiment of the present disclosure provides a bonding compensation method, where the compensation method includes:
step S101, providing at least one bottom chip, wherein a plurality of top chips are bonded on the bottom chip;
step S102, obtaining the offset of the actual bonding position of each top chip relative to the bottom chip and the preset error precision of the setting position of the rewiring layer to be formed on each top chip relative to the bottom chip;
step S103, constructing compensation quantities of the setting positions of the rewiring layers to be formed, which contain pre-compensation parameters, relative to the top chips, and calculating to obtain the pre-compensation parameters by taking the preset error precision as a boundary condition; the pre-compensation parameter is a compensation parameter of the setting position of the rewiring layer to be formed relative to the bottom chip.
In the embodiment of the disclosure, a plurality of top chips are bonded on the bottom chip, the deviations of the top chips relative to the bottom chip are different, and the pre-compensation parameters can be calculated by constructing the compensation amount of the setting position of the redistribution layer to be formed containing the pre-compensation parameters relative to the top chips, so that the compensation amount of each top chip can be calculated, and the compensation is performed respectively for the setting position of the redistribution layer to be formed on each top chip. In this way, when the variations of the top chips bonded to the bottom chip are different, the misalignment of the rewiring layer provided on each top chip bonded to the same bottom chip with respect to the bottom chip is made the same by compensating the alignment accuracy of the photolithography process for forming the rewiring layer on each top chip. In the embodiment of the disclosure, the setting position of the rewiring layer is adjusted to compensate the deviation generated in the process of bonding the top chip to the bottom chip, so that the rewiring method of the chip is optimized, and the performance of the bonding structure is improved.
In the embodiment of the present disclosure, in step S101, at least one bottom chip is provided, and a plurality of top chips are bonded on the bottom chip.
Referring to fig. 2, fig. 2 is a partial top view of a bonding structure during bonding compensation provided by the embodiment of the present disclosure. As shown in fig. 2, a first top chip 221, a second top chip 222, a third top chip 223, a fourth top chip 224, and a fifth top chip 225 are sequentially bonded to the bottom chip 210. The solid line boxes in fig. 2 show that the actual bonding positions of the first top chip 221, the second top chip 222, the third top chip 223, the fourth top chip 224 and the fifth top chip 225 are the first actual bonding position 231, the second actual bonding position 232, the third actual bonding position 233, the fourth actual bonding position 234 and the fifth actual bonding position 235, respectively. The dashed boxes in fig. 2 show that the predetermined bonding positions of the first top chip 221, the second top chip 222, the third top chip 223, the fourth top chip 224 and the fifth top chip 225 are a first predetermined bonding position 241, a second predetermined bonding position 242, a third predetermined bonding position 243, a fourth predetermined bonding position 244 and a fifth predetermined bonding position 245, respectively.
Here, the types of the plurality of top chips bonded on the same bottom chip may be the same or different. For example, the top chips may each be a memory chip, a control chip, or other type of chip.
Here, due to a deviation generated in the bonding process of bonding the top chip to the bottom chip, the actual bonding positions of the plurality of top chips bonded on the same bottom chip may be different from the predetermined bonding positions.
It should be noted that only a partial top view of the bonding structure of the top chip bonded to the bottom chip is shown in fig. 2, that is, five top chips are bonded to the bottom chip in fig. 2. However, in an actual bonding process, the number of top chips is much larger than that shown in fig. 2. The number of top chips bonded to the bottom chip is not particularly limited by the embodiments of the present disclosure.
In step S102, in the embodiment of the present disclosure, an offset of an actual bonding position of each top chip with respect to the bottom chip and a preset error precision of a setting position of a redistribution layer to be formed on each top chip with respect to the bottom chip are obtained.
It should be noted that any point on the bottom chip may be selected as an origin, and a two-dimensional coordinate system is established on a plane where the bottom chip is located, where the two-dimensional coordinate system includes an X axis and a Y axis that are perpendicular to each other. For example, if the bottom chip appears as a rectangle in top view, the intersection of the diagonals of the rectangle may be selected as the origin of the two-dimensional coordinate system, or the vertex of the rectangle may also be selected as the origin of the two-dimensional coordinate system. In the embodiment of the disclosure, the offset is a distance between coordinate points corresponding to the top chip and the bottom chip, and therefore, a position of an origin of the two-dimensional coordinate system does not affect a deviation between an actual bonding position of the top chip and a predetermined bonding position and an offset of the top chip relative to the bottom chip.
Specifically, the first top chip is taken asThe examples are illustrative. If the coordinate of the actual bonding position of the first top chip is (X) 231 ，Y 231 ) The coordinates of the predetermined bonding position of the first top chip are (X) 241 ，Y 241 ) Then the deviation between the actual bonding position and the predetermined bonding position of the first top die is Δ X 34 ，∆Y 34 ) Therein is Δ X 34 =X 231 −X 241 ，∆Y 34 =Y 231 −Y 241 。
Δ if necessary 34 And, am 34 Indicating the distances of the coordinate point corresponding to the actual bonding position of the first top chip and the coordinate point corresponding to the predetermined bonding position on the X axis and the Y axis respectively, and Δ X 34 And Δ Y 34 The numerical result of (c) has positive and negative, where positive and negative indicate direction. For example, Δ X of the first top chip 34 A positive result of (d) indicates that the coordinates of the actual bonding position of the first top chip on the X-axis are located in a positive direction along the X-axis with respect to its intended bonding position. Also, for example, the first top die 34 A negative result of (d) indicates that the coordinate of the actual bonding position of the first top chip on the X-axis is located in a negative direction along the X-axis of its intended bonding position.
Here, the deviation between the actual bonding position and the predetermined bonding position of each top chip is different. For example, on the same bottom chip, the coordinates of the actual bonding position of the first top chip on the XY plane and the coordinates of the predetermined bonding position on the XY plane differ only by the value of the X-axis coordinate or the value of the Y-axis coordinate, i.e. X 231 Is equal to X 241 And Y is 231 And Y 241 Different, or X 231 And X 241 Is different and Y 231 Is equal to Y 241 (ii) a And the actual bonding position of the second top chip has the coordinate (X) 232 ，Y 232 ) The coordinates of the predetermined bonding position of the first top chip are (X) 242 ，Y 242 ) The coordinates of the actual bonding position of the second top chip on the XY plane and the coordinates of the predetermined bonding position on the XY plane are different, i.e. X-axis coordinate value and Y-axis coordinate value 232 And X 242 Is different and Y 232 And Y 242 Different. The actual bonding positions of a plurality of top chips bonded on the same bottom chip exhibit irregular deviations from the predetermined bonding positions.
Referring to fig. 3, fig. 3 is a partial top view of a bonding structure in a bonding compensation process provided by the embodiment of the disclosure. As shown in fig. 3, four vertices of a rectangle presented by the bottom chip 210 in the top view are numbered, the top left corner vertex of the bottom chip 210 is numbered first, the top right corner vertex of the bottom chip 210 is numbered second, the bottom right corner vertex of the bottom chip 210 is numbered third, the bottom left corner vertex of the bottom chip 210 is numbered fourth, and the coordinates of the four vertices of the bottom chip can be determined according to the established two-dimensional coordinate system. Using a similar method to number four vertexes of a rectangle presented by each top chip in a top view, numbering the top left vertex of the actual bonding position of the first top chip as first ', numbering the top right vertex of the actual bonding position of the first top chip as second', numbering the bottom right vertex of the actual bonding position of the first top chip as third ', numbering the bottom left vertex of the actual bonding position of the first top chip as fourth' according to the sequence of the forward pointer, and determining the coordinates of the four vertexes of each top chip according to the established two-dimensional coordinate system. Here, fig. 3 only illustrates four vertex numbers of the first top chip 221 and the fifth top chip 225, and as shown in fig. 3, the first top chip 221 has an upper left vertex (r '), an upper right vertex (r'), a lower right vertex (c '), a lower left vertex (r'), an upper left vertex (r "), an upper right vertex (r"), a lower right vertex (r "), and a lower left vertex (r") of the fifth top chip 225.
For ease of identification, fig. 3 only illustrates the first top chip 221 and the fifth top chip 225. Here, the offset amount of the actual bonding position of each top chip with respect to the bottom chip is determined by subtracting the coordinates of the four vertices of the bottom chip from the coordinates of the four vertices of the actual bonding position of each top chip, respectively. Subtracting the coordinates of the top left corner vertex of the bottom chip from the coordinates of the top left corner vertex of the actual bonding position of each top chip; subtracting the coordinate of the top right corner vertex of the bottom chip from the coordinate of the top right corner vertex of the actual bonding position of each top chip; subtracting the coordinates of the top right corner of the bottom chip from the coordinates of the top right corner of the actual bonding position of each top chip; the coordinates of the bottom chip's bottom left corner vertex are subtracted from the coordinates of the bottom chip's bottom left corner vertex of the actual bonding location of each top chip.
Here, the coordinates (X) are used n-m ，Y n-m ) Indicates the offset of the actual bonding position of each top chip relative to the bottom chip, where X n-m Representing the component in the direction of the X-axis, Y, of the offset of the actual bonding position of each top chip with respect to the bottom chip n-m Representing the component in the Y-axis direction of the offset of the actual bonding location of each top chip relative to the bottom chip; wherein, X n-m And Y n-m Constituting an offset of the actual bonding position of each top chip with respect to the bottom chip. In the coordinate (X) n-m ，Y n-m ) In the above description, n denotes the top chip number, and m denotes the top chip number of the actual bonding position. In the disclosed embodiment, n may be an integer of 1 to 5, and m may be an integer of 1 to 4.
For example, referring to FIG. 3, (X) 1-1 ，Y 1-1 ）、（X 1-2 ，Y 1-2 ）、（X 1-3 ，Y 1-3 ) And (X) 1-4 ，Y 1-4 ) Refer to an offset of an upper left vertex of an actual bonding position of the first top chip 221 (i.e., (r) shown in fig. 3) with respect to an upper left vertex of the bottom chip 210 (i.e., (r) shown in fig. 3), an offset of an upper right vertex of an actual bonding position of the first top chip 221 (i.e., (r) shown in fig. 3) with respect to an upper right vertex of the bottom chip 210 (i.e., (r) shown in fig. 3), an offset of a lower right vertex of an actual bonding position of the first top chip 221 (i.e., (c) shown in fig. 3) with respect to an lower right vertex of the bottom chip 210 (i.e., (r) shown in fig. 3), and an offset of a lower left vertex of an actual bonding position of the first top chip 221 (i.e., (r) with respect to a lower left vertex of the bottom chip 210 (i.e., (r) shown in fig. 3), respectivelyDeviation amount of (d). Also for example, (X) 5-1 ，Y 5-1 ）、（X 5-2 ，Y 5-2 ）、（X 5-3 ，Y 5-3 ) And (X) 5-4 ，Y 5-4 ) Refer to the offset of the top left corner vertex of the actual bonding position of the fifth top chip 225 (i.e., (r ") shown in fig. 3) from the top left corner vertex of the bottom chip 210, the offset of the top right corner vertex of the actual bonding position of the fifth top chip 225 (i.e., (r") shown in fig. 3) from the top right corner vertex of the bottom chip 210, the offset of the bottom right corner vertex of the actual bonding position of the fifth top chip 225 (i.e., (r ") shown in fig. 3) from the bottom right corner vertex of the bottom chip 210, and the offset of the bottom left corner vertex of the actual bonding position of the fifth top chip 225 (i.e., (r") shown in fig. 3) from the bottom left corner vertex of the bottom chip 210, respectively.
In some embodiments, the default error precision of each of the top chips is determined according to a process node of each of the top chips.
Here, the type of the plurality of top chips bonded on the same bottom chip may be different, and the process nodes of the plurality of top chips may be different. The process node is a main index of the advanced level of the integrated circuit process, and represents the minimum line width which can be achieved by the integrated circuit production process. In a specific example, the process node may refer to a length of a gate of a MOS transistor or a length of a channel of a MOS transistor. Since the main function of the MOS transistor is to control the current between the source and the drain through the gate, the length of the gate is the most important parameter in the semiconductor process. In another specific example, a process node may refer to a half pitch, i.e., half the distance between interconnect lines within an integrated circuit.
In the embodiment of the disclosure, since the process nodes of the top chips may be different, the preset error precision of the top chips may be different. For example, the process node of the first top chip is 50nm, and then the preset error precision of the first top chip may be 5 nm; the process node of the second top chip is 20nm, and the preset error precision of the second top chip can be 4 nm. In the embodiment of the present disclosure, there is no particular limitation on the proportional relationship between the numerical value of the process node of the top chip and the predetermined error precision.
In the embodiment of the present disclosure, in step S103, a compensation amount of a setting position of the redistribution layer to be formed, which includes a pre-compensation parameter, with respect to each top chip is constructed, and the pre-compensation parameter is calculated by using the preset error precision as a boundary condition; the pre-compensation parameters are compensation parameters of the setting position of the rewiring layer to be formed relative to the bottom chip.
Referring to fig. 4, fig. 4 is a partial top view three of a bonding structure in a bonding compensation process provided by the embodiment of the present disclosure. For ease of identification, fig. 4 only illustrates the first top chip 221 and the fifth top chip 225. As shown in fig. 4, according to the established two-dimensional coordinate system, the compensation amount of the arrangement position of the rewiring layer to be formed including the pre-compensation parameter with respect to each top chip is established; wherein the pre-compensation parameter is a compensation parameter (X) of a setting position of the rewiring layer to be formed relative to the bottom chip 0 ，Y 0 ，θ 0 ) At this time, the pre-compensation parameter is an unknown parameter. With the preset error accuracy as a boundary condition, the value of the unknown parameter (i.e., the pre-compensation parameter) can be calculated.
Here, the coordinates (X) are used n-m-0 ，Y n-m-0 ) Represents the compensation amount of the arrangement position of the rewiring layer to be formed with respect to each top chip, wherein X n-m-0 Representing a component in the X-axis direction of the compensation amount of the arrangement position of the re-wiring layer to be formed with respect to each top chip, Y n-m-0 A component in the Y-axis direction representing the compensation amount of the setting position of the rewiring layer to be formed with respect to each top chip; x n-m-0 And Y n-m-0 The compensation amount of the arrangement position of the rewiring layer to be formed with respect to each top chip is constituted. In the coordinate (X) n-m-0 ，Y n-m-0 ) In the above description, n denotes the top chip number, and m denotes the top chip number of the actual bonding position. In the disclosed embodiment, n may be an integer of 1 to 5, and m may be an integer of 1 to 4.
For example, referring to FIG. 4, (X) 1-1-0 ，Y 1-1-0 ）、（X 1-2-0 ，Y 1-2-0 ）、（X 1-3-0 ，Y 1-3-0 ) And (X) 1-4-0 ，Y 1-4-0 ) The compensation amount of the set position where the re-wiring layer is to be formed with respect to the top left corner vertex of the first top chip 221 (i.e., < i > shown in fig. 4), the compensation amount of the set position where the re-wiring layer is to be formed with respect to the top right corner vertex of the first top chip 221 (i.e., < i > shown in fig. 4), the compensation amount of the set position where the re-wiring layer is to be formed with respect to the bottom right corner vertex of the first top chip 221 (i.e., < i > shown in fig. 4), and the compensation amount of the set position where the re-wiring layer is to be formed with respect to the bottom left corner vertex of the first top chip 221 (i.e., < i > shown in fig. 4), respectively. Also for example, (X) 5-1-0 ，Y 5-1-0 ）、（X 5-2-0 ，Y 5-2-0 ）、（X 5-3-0 ，Y 5-3-0 ) And (X) 5-4-0 ，Y 5-4-0 ) The compensation amount of the set position where the re-wiring layer is to be formed with respect to the top left corner vertex of the fifth top chip 225 (i.e., < r > shown in fig. 4), the compensation amount of the set position where the re-wiring layer is to be formed with respect to the top right corner vertex of the fifth top chip 225 (i.e., < r > shown in fig. 4), the compensation amount of the set position where the re-wiring layer is to be formed with respect to the bottom right corner vertex of the fifth top chip 225 (i.e., < r > shown in fig. 4), and the compensation amount of the set position where the re-wiring layer is to be formed with respect to the bottom left corner vertex of the fifth top chip 225 (i.e., < r > shown in fig. 4) are referred to, respectively.
Here, the deviations of the actual bonding positions of the plurality of top chips bonded on the same bottom chip from their predetermined bonding positions are different due to errors generated in the bonding of the respective top chips to the bottom chip. If the bottom chip is used as a basic unit for alignment accuracy compensation, the rewiring requirements of all top chips bonded on the same bottom chip cannot be met.
In the embodiment of the disclosure, the compensation amount of each top chip is calculated according to the offset of the actual bonding position of each top chip relative to the bottom chip, and the alignment precision compensation is performed on the redistribution layer formed on each top chip, so that the deviation of the setting position of the redistribution layer relative to the predetermined bonding position of the corresponding top chip is the same or the setting position of the redistribution layer is the same as the predetermined bonding position of the corresponding top chip. Therefore, the setting position of the rewiring layer on each top chip is adjusted to enable the setting position of the rewiring layer on each top chip to have the same deviation relative to the bottom chip so as to compensate the deviation generated in the process of bonding the top chip to the bottom chip, so that the rewiring method of the chip is optimized, and the performance of the bonding structure is improved.
In some embodiments, the calculating the pre-compensation parameter with the preset error precision as a boundary condition includes:
and calculating to obtain the pre-compensation parameter according to the condition that the offset of each top chip and the sum of the compensation quantity of the arrangement position of the rewiring layer to be formed relative to each top chip meet the preset error precision.
In some embodiments, the pre-compensation parameters include: a first offset component along a first direction, a second offset component along a second direction, and an angle parameter; wherein the first direction and the second direction are perpendicular to each other.
Here, the first direction may be an X direction, and the second direction may be a Y direction.
Here, equations (1) to (4) are constructed so that the offset amount of each vertex of each top chip bonded on the same bottom chip and the compensation amount of each vertex of each top chip for a rewiring layer to be formed satisfy the preset error accuracy are as follows:
（X n-1 ，Y n-1 ）+（X n-1-0 ，Y n-1-0 ）<（X n ，Y n ) (formula 1)
（X n-2 ，Y n-2 ）+（X n-2-0 ，Y n-2-0 ）<（X n ，Y n ) (formula 2)
（X n-3 ，Y n-3 ）+（X n-3-0 ，Y n-3-0 ）<（X n ，Y n ) (formula 3)
（X n-4 ，Y n-4 ）+（X n-4-0 ，Y n-4-0 ）<（X n ，Y n ) (formula 4)
Where n represents the top chip serial number. Specifically, equation (1) represents the offset of the top left corner vertex of each top chip (i.e., (X) n-1 ，Y n-1 ) And the amount of compensation of the top left corner vertex of the rewiring layer to be formed (i.e., (X) with respect to each top chip n-1-0 ，Y n-1-0 ) The sum of (X) satisfies a predetermined error accuracy (i.e., (X) n ，Y n ) Equation (2) represents the offset of the top right vertex of each top chip (i.e., (X) n-2 ，Y n-2 ) And the amount of compensation of the top right vertex of the rewiring layer to be formed with respect to each top chip (i.e., (X) n-2-0 ，Y n-2-0 ) The sum of (X) satisfies a predetermined error accuracy (i.e., (X) n ，Y n ) Equation (3) represents the offset of the vertex of the lower right corner of each top chip (i.e., (X) n-3 ，Y n-3 ) And the amount of compensation of the top right corner vertex of the redistribution layer to be formed (i.e., (X) with respect to each top chip n-3-0 ，Y n-3-0 ) The sum of (X) satisfies a predetermined error accuracy (i.e., (X) n ，Y n ) Equation (4) represents the offset of the vertex of the lower left corner of each top chip (i.e., (X) n-4 ，Y n-4 ) And the amount of compensation of the top left corner vertex of the rewiring layer to be formed (i.e., (X) with respect to each top chip n-4-0 ，Y n-4-0 ) The sum satisfies a predetermined error accuracy (i.e., (X)) n ，Y n ））。
According to the formulas (1) to (4), the offset of the actual bonding position of each top chip relative to the bottom chip is a known parameter, the preset error precision of the setting position of the rewiring layer to be formed on each top chip relative to the bottom chip is also a known parameter, and the compensation amount of the rewiring layer to be formed relative to each top chip can be determined according to each formulaAnd determining the offset and the pre-compensation parameter of each top chip. In the above expressions (1) to (4), only the precompensation parameter is an unknown parameter, and therefore, according to the expressions (1) to (4), the precompensation parameter (X) satisfying the accuracy of the preset error of the arrangement position of the rewiring layer to be formed on each top chip with respect to the bottom chip can be solved 0 ，Y 0 ，θ 0 ）。
How to decompose the pre-compensation parameters will be described in detail below with reference to fig. 5, 6A, and 6B.
In some embodiments, the constructing the compensation amount of the arrangement position of the redistribution layer to be formed including the pre-compensation parameter with respect to each of the top chips includes:
and decomposing the pre-compensation parameters of the setting position of the rewiring layer to be formed relative to the bottom chip according to the offset of each top chip to obtain the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip.
In some embodiments, the constructing the compensation amount of the arrangement position of the redistribution layer to be formed including the pre-compensation parameter with respect to each of the top chips includes:
decomposing the angle parameters along the first direction and the second direction respectively to obtain a first angle component and a second angle component;
obtaining a first compensation component of the setting position of the rewiring layer to be formed relative to each top chip along the first direction according to the offset, the first offset component and the first angle component of each top chip;
obtaining a second compensation component of the setting position of the rewiring layer to be formed relative to each top chip along the second direction according to the offset, the second offset component and the second angle component of each top chip;
wherein the first compensation component and the second compensation component constitute the compensation amount.
Referring to FIG. 5, there is shownAnd 5 is a partial top view four of the bonding structure in the bonding compensation process provided by the embodiment of the disclosure. As shown in FIG. 5, the first setting position 261 of the bottom chip 210 is a rectangle defined by top left vertex (I), top right vertex (II), bottom right vertex (III) and bottom left vertex (III), wherein (X) 0-3 ，Y 0-3 ) And coordinates of the vertex (c) of the lower right corner of the first set position 261 for the bottom chip. Here, the bottom chip has bonded thereto a first top chip 221, a second top chip 222, a third top chip 223, a fourth top chip 224, and a fifth top chip 225. Assuming that the bottom chip 210 is used as a basic unit to compensate the bottom chip 210, the bottom chip 210 is compensated from the first setting position 261 to the second setting position 262, and according to the clockwise sequence, the top left corner, the top right corner, the bottom right corner, and the bottom left corner of the second setting position 262 of the bottom chip 210 are numbered, # c, and b, respectively. Here, in the process of compensating the bottom chip from the first set position to the second set position, the respective top chips bonded on the bottom chip are also compensated from the positions shown by the solid line boxes to the positions shown by the broken line boxes. If the second setting position is determined as the setting position where the rewiring layer is formed on the bottom chip with the bottom chip as the basic unit, the compensation parameter of the second setting position with respect to the first setting position may be determined as the pre-compensation parameter (X) 0 ，Y 0 ，θ 0 ) Wherein X is 0 Denotes a component of offset in the X-axis direction (i.e., a first offset component), Y, of the bottom chip from a first set position to a second set position 0 Denotes a shift component in the Y-axis direction (i.e., a second shift component), θ, of the bottom chip from the first set position to the second set position 0 An angle parameter is indicated which compensates the bottom chip from the first set position to the second set position.
In addition, if X 0 The positive value indicates that the bottom chip is compensated from the first setting position to the second setting position along the positive direction of the X axis; if X 0 Negative values indicate that the compensation of the bottom chip from the first set position to the second set position is negative along the X-axisThe direction is compensated. Similarly, may be according to Y 0 Determines the moving direction along the Y axis of the bottom chip from the first setting position to the second setting position. Here, the angle parameter θ may be set 0 It is meant that the compensation is performed by rotating the bottom chip in a clockwise or counterclockwise direction from the first set position to the second set position. The clockwise rotation or the counterclockwise rotation is related, for example, a 90-degree clockwise rotation is equivalent to a 270-degree counterclockwise rotation. Therefore, it is possible to set only the bottom chip to rotate in the clockwise direction or to rotate in the counterclockwise direction from the first set position to the second set position.
It should be noted that the bottom chip is used as a basic unit illustrated in fig. 5, and the compensation from the first setting position to the second setting position is performed to illustrate the pre-compensation parameter (X) 0 ，Y 0 ，θ 0 ) In the decomposition process, the top chips are compensated in a targeted manner preferentially in the subsequent actual process to form the rewiring layer, the bottom chips are not compensated to the second setting position directly from the first setting position, and the bottom chips are not compensated to form the rewiring layer directly by taking the bottom chips as a basic unit.
As also shown in fig. 5, in the process of compensating the bottom chip from the first setting position to the second setting position, each top chip is also compensated from the solid line box to the dashed line box correspondingly. It should be noted that, in the process of compensating the bottom chip from the first setting position to the second setting position, each top chip will also move the first offset component along the X-axis direction and the second offset component along the Y-axis direction. However, in the process of compensating the bottom chip from the first setting position to the second setting position, the vectors corresponding to the angle parameters of the respective vertexes of the respective top chips are different. Therefore, the angular parameter of the pre-compensation parameter needs to be decomposed for each vertex of each top chip to obtain the compensation amount of each top chip.
Here, the process of compensating the bottom chip from the first set position to the second set position may be understood as the process of compensating the bottom chip from the first set position to the second set positionThe position firstly translates along the X-axis direction 0 One unit, then translated along the Y axis by Y 0 Unit, last rotation angle θ 0 And then to a second setting position. It should be noted that the bottom chip is translated by X along the X-axis direction 0 Unit, then each top chip bonded on the bottom chip will also be translated in the X-axis direction by X 0 A unit; translating the bottom chip along the Y-axis by Y 0 By one unit, then each top chip bonded on the bottom chip will also be translated in the Y-axis direction by Y 0 A unit; but the bottom chip is rotated by an angle theta 0 Corresponding vector
Figure 571102DEST_PATH_IMAGE001
The rotation angle of each top chip bonded on the bottom chip corresponds to a vector different from the rotation angle theta of the bottom chip 0 Corresponding vector
Figure 946632DEST_PATH_IMAGE001
Therefore, the component of the vector in the X-axis direction and the component in the Y-axis direction corresponding to each top chip rotation angle are also different from the bottom chip rotation angle θ 0 Corresponding vector
Figure 195211DEST_PATH_IMAGE001
A component in the X-axis direction and a component in the Y-axis direction. Here, the vectors corresponding to the rotation angles of the respective top chips bonded on the bottom chip are related to the offsets of the respective top chips with respect to the bottom chip, and therefore, the components in the X-axis direction and the components in the Y-axis direction of the vectors corresponding to the rotation angles of each top chip may also be different. Therefore, after the pre-compensation parameters meeting the preset error precision are obtained through solving, a first angle component of the vector corresponding to each top chip rotation angle along the X-axis direction and a second angle component of the vector corresponding to each top chip rotation angle along the Y-axis direction can be obtained through calculation.
In the embodiment of the disclosure, the compensation amount of each top chip is calculated according to the offset of each top chip, the setting position of the redistribution layer formed on each top chip can be determined according to the offset of each top chip and the compensation amount of each top chip, and the process error in the process of bonding each top chip to the bottom chip can be compensated in a targeted manner by adjusting the setting position of the redistribution layer.
Referring to fig. 6A and 6B, fig. 6A is a first schematic diagram illustrating an exploded principle in a bonding compensation process provided by the embodiment of the present disclosure, and fig. 6B is a second schematic diagram illustrating an exploded principle in a bonding compensation process provided by the embodiment of the present disclosure. As shown in FIG. 6A, the coordinates (X) of the vertex of the bottom chip's lower right corner are used 0-3 ，Y 0-3 ) For example, by compensating the vertex of the lower right corner of the bottom chip from the first setting position to the second setting position, the pre-compensation parameter can be decomposed into a first offset component X along the X-axis direction 0 Second offset component Y in Y-axis direction 0 And an angle parameter theta 0 Corresponding vector
Figure 793682DEST_PATH_IMAGE001
. The angle parameter θ is required for each top chip bonded on the same bottom chip 0 Corresponding vector
Figure 326164DEST_PATH_IMAGE001
Decomposition is performed into a first angular component along the X-axis direction and a second angular component along the Y-axis direction.
As shown in fig. 6B, the coordinates (X) of the vertex of the bottom chip's lower right corner 0-3 ，Y 0-3 ) For example, the angle parameter θ 0 Corresponding vector
Figure 617468DEST_PATH_IMAGE001
Decomposition is carried out. FIG. 6B shows a right triangle ABC with the right side AB as X 0-3 The right-angle side BC is Y 0-3 The hypotenuse AC and ═ BAC (i.e., θ') can be solved as shown in equation 5 below. FIG. 6B also shows a vertex angle θ 0 The isosceles triangle AEC of (1), wherein the hypotenuse AC and the hypotenuse AE are equal, and the base CE of the triangle AEC is the vector
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Can be based on the angle parameter theta 0 And a beveled edgeCalculating to obtain vector by AC
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The absolute value of (a) is shown in the following formula 6. FIG. 6B also shows a pair vector
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Decomposing along the X-axis direction to obtain a first angle component
Figure 870278DEST_PATH_IMAGE002
And resolving along the Y-axis to obtain a second angle component
Figure 93448DEST_PATH_IMAGE003
First angle component
Figure 299302DEST_PATH_IMAGE002
The absolute value of (D) is the right-angle side DE of the right-angle triangle CDE, the second angle component
Figure 275217DEST_PATH_IMAGE003
The absolute value of (c) is the right-angle side CD of the right-angle triangle CDE, and the ≈ DCE (i.e. θ ") is obtained by solving, according to the hypotenuse CE of the right-angle triangle CDE (i.e.,
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absolute value of) and & (i.e., θ ") to obtain the right angle edge DE (i.e., the first angular component)
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) And a perpendicular edge CD (i.e., a second angular component)
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) The following formulae 7, 8 and 9.
Figure 193177DEST_PATH_IMAGE004
(formula 5)
Figure 731606DEST_PATH_IMAGE005
(formula 6)
Figure 178637DEST_PATH_IMAGE006
(formula 7)
Figure 460714DEST_PATH_IMAGE007
(formula 8)
Figure 161953DEST_PATH_IMAGE008
(formula 9)
Wherein, X 0-3 Is the abscissa, Y, of the vertex of the lower right corner of the bottom chip 0-3 Is the ordinate, theta, of the vertex of the lower right corner of the bottom chip 0 Is an angle parameter.
As shown in FIG. 5, taking the third top chip as an example, the offset (X) of the vertex of the lower right corner of the third top chip is set 3-3 ，Y 3-3 ) Substituting the first angle component into the above equations 8 and 9 to calculate the first angle component of the vertex of the lower right corner of the third top chip
Figure 386130DEST_PATH_IMAGE002
And a second angular component
Figure 274452DEST_PATH_IMAGE003
. And, based on the first offset component X 0 And a first angular component of a bottom right corner vertex of a third top chip
Figure 343908DEST_PATH_IMAGE002
The sum is calculated to obtain a first compensation component X of the vertex of the lower right corner of the third top chip along the X-axis direction 3-3-0 As shown in the following formula 10; according to the second offset component Y 0 And a second angular component of a lower right corner vertex of a third top chip
Figure 165233DEST_PATH_IMAGE003
The sum is calculated to obtain a second compensation component Y of the vertex of the lower right corner of the third top chip along the Y-axis direction 3-3-0 This is shown in the following formula 11. The first compensation component and the second compensation component constitute a compensation quantity (X) of a vertex of a lower right corner of the third top chip 3-3-0 ，Y 3-3-0 ）。
Figure 311044DEST_PATH_IMAGE009
(formula 10)
Figure 195649DEST_PATH_IMAGE010
(formula 11)
Here, the first offset component X according to each top chip 0 And a first angular component
Figure 553949DEST_PATH_IMAGE002
Calculating to obtain a first compensation component of each top chip along the X-axis direction; second offset component Y from each top chip 0 And a second angular component
Figure 744628DEST_PATH_IMAGE003
And calculating to obtain a second compensation component of each top chip along the Y-axis direction. As described above, both the first offset component and the second offset component may be positive values or negative values, and according to the negativity and the positivity of the first offset component, it can be determined that each top chip is compensated along the positive direction or the negative direction of the X axis; according to the positive and negative of the second offset component, the positive direction or the negative direction of each top chip along the Y axis can be judged for compensation.
It should be noted that the angle parameter θ may be set 0 It is shown that the bottom chip is compensated for rotation in a clockwise direction from the first set position to the second set position. As can be seen from equations 10 and 11, the positivity or negativity of the first angle component and the second angle component depends on the positivity or negativity of the sine function and the cosine function, that is, on the angle parameter θ 0 The size of (2).
The method for decomposing the angle parameter in the pre-compensation parameter, constructing the compensation amount of each top chip including the pre-compensation parameter, and calculating the pre-compensation parameter and the compensation amount of each top chip with the preset error precision as the boundary condition, as shown in fig. 6A and 6B, is only a specific example of the present disclosure. In the bonding compensation method provided in the embodiment of the present disclosure, there is no particular limitation on how to decompose the pre-compensation parameter.
In some embodiments, after the calculating the pre-compensation parameter, the compensation method further includes:
calculating to obtain the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip according to the pre-compensation parameters and the offset of each top chip;
and determining the setting position of the rewiring layer to be formed on each top chip according to the offset of each top chip and the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip.
Here, the first compensation component and the second compensation component of the arrangement position of the rewiring layer with respect to each top chip may be calculated from the pre-compensation parameter, and the first compensation component and the second compensation component of each top chip constitute the compensation amount. Further, the setting position of the rewiring layer on each top chip is determined according to the offset and the compensation amount of each top chip.
In the embodiment of the present disclosure, when the deviation of each top chip bonded on the bottom chip is different, the compensation amount of the rewiring layer to be formed with respect to each top chip is determined with respect to the offset of each top chip with respect to the bottom chip. Thus, the deviation of the arrangement position of the rewiring layer on each top chip bonded on the same bottom chip relative to the bottom chip can be made the same by compensating the alignment accuracy of the photolithography process for forming the rewiring layer on each top chip.
Further, in the embodiment of the present disclosure, the alignment accuracy of the photolithography process for forming the first redistribution layer on each top chip may be compensated by determining the compensation amount of the setting position of the redistribution layer to be formed with respect to each top chip, so as to form the first redistribution layer on each top chip. Thus, the deviation of the arrangement position of the first rewiring layer on each top chip with respect to the bottom chip is the same. Further, since the setting position of the first rewiring layer has been adjusted, it is possible to form the second rewiring layer on the first rewiring layer of each top chip while taking the exposure area (i.e., the bottom chip) as a basic unit again. Thus, the time for forming the second rewiring layer on the first rewiring layer can be greatly shortened.
The embodiment of the present disclosure further provides a chip rewiring method, where the wiring method includes:
providing at least one bottom chip having a plurality of top chips bonded thereto;
the setting position of the rewiring layer to be formed on the bottom chip is determined through the bonding compensation method in the technical scheme.
In some embodiments, the routing method further comprises:
determining a compensation amount between the setting position of the rewiring layer to be formed and the offset according to the setting position of the rewiring layer to be formed and the offset of the corresponding top chip;
and compensating the alignment precision of the photoetching process for forming the rewiring layer according to the compensation amount between the setting position of the rewiring layer to be formed and the offset.
In the embodiment of the disclosure, the compensation amount of each top chip can be calculated, and the first rewiring layer is formed on each top chip to perform targeted compensation on the process error of each top chip in the bonding process. Here, the adjustment of the arrangement position of the rewiring layer is used to compensate the deviation generated in the process of bonding the top chip to the bottom chip, so that the rewiring method of the chip is optimized, and the performance of the bonding structure is improved.
The embodiment of the present disclosure further provides a bonding structure, where the bonding structure includes:
at least one bottom chip having a plurality of top chips bonded thereto;
a rewiring layer arranged on each top chip; the compensation quantity between the setting position of the rewiring layer of each top chip and the offset of the actual bonding position of each top chip relative to the bottom chip respectively meets the boundary condition of each top chip; and the boundary condition is the preset error precision of the setting position of the rewiring layer on each top chip relative to the bottom chip.
The disclosed embodiment also provides a bonding compensation device, which includes:
the data acquisition module is used for acquiring the offset of the actual bonding position of each top chip relative to the bottom chip and the preset error precision of the setting position of the rewiring layer to be formed on each top chip relative to the bottom chip; wherein a plurality of the top chips are bonded on the bottom chip;
the data calculation module is used for constructing compensation quantities of the setting position of the rewiring layer to be formed, which contains pre-compensation parameters, relative to each top chip, and calculating the pre-compensation parameters by taking the preset error precision as a boundary condition; the pre-compensation parameters are compensation parameters of the setting position of the rewiring layer to be formed relative to the bottom chip.
In some embodiments, the data calculation module is further configured to calculate, according to the pre-compensation parameter and the offset of each top chip, the compensation amount of the setting position of the redistribution layer to be formed with respect to each top chip;
the device further comprises:
and the wiring module is used for determining the setting position of the rewiring layer to be formed on each top chip according to the offset of each top chip and the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip.
The embodiment of the disclosure provides a bonding compensation method and device, a chip rewiring method and a bonding structure. The compensation method comprises the following steps: providing at least one bottom chip, wherein a plurality of top chips are bonded on the bottom chip; acquiring the offset of the actual bonding position of each top chip relative to the bottom chip and the preset error precision of the setting position of the rewiring layer to be formed on each top chip relative to the bottom chip; constructing compensation quantity of the setting position of the rewiring layer to be formed, which contains a pre-compensation parameter, relative to each top chip, and calculating to obtain the pre-compensation parameter by taking the preset error precision as a boundary condition; the pre-compensation parameter is a compensation parameter of the setting position of the rewiring layer to be formed relative to the bottom chip. In the embodiment of the disclosure, a plurality of top chips are bonded on the bottom chip, and errors caused by a bonding process cause different deviations of actual bonding positions of the top chips relative to the bottom chip, and the pre-compensation parameters can be calculated by constructing the compensation quantity of the setting position of the redistribution layer to be formed, which contains the pre-compensation parameters, relative to each top chip, so that the compensation quantity of each top chip can be calculated, and the setting position of the redistribution layer to be formed on each top chip is compensated respectively.
In this way, when the variations of the top chips bonded to the bottom chip are different, the misalignment of the rewiring layer provided on each top chip bonded to the same bottom chip with respect to the bottom chip is made the same by compensating the alignment accuracy of the photolithography process for forming the rewiring layer on each top chip. In the embodiment of the disclosure, the setting position of the rewiring layer is adjusted to compensate the deviation generated in the process of bonding the top chip to the bottom chip, so that the rewiring method of the chip is optimized, and the performance of the bonding structure is improved.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description, and do not represent the advantages or disadvantages of the embodiments.
The above description is only a preferred embodiment of the present disclosure, and not intended to limit the scope of the present disclosure, and all modifications and equivalents of the technical solutions of the present disclosure, which are made by using the contents of the present disclosure and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present disclosure.

Claims (12)

1. A bonding compensation method, the compensation method comprising:
providing at least one bottom chip, wherein a plurality of top chips are bonded on the bottom chip;
acquiring the offset of the actual bonding position of each top chip relative to the bottom chip and the preset error precision of the setting position of the rewiring layer to be formed on each top chip relative to the bottom chip;
constructing compensation quantity of the setting position of the rewiring layer to be formed, which contains a pre-compensation parameter, relative to each top chip, and calculating to obtain the pre-compensation parameter by taking the preset error precision as a boundary condition; the pre-compensation parameter is a compensation parameter of the setting position of the rewiring layer to be formed relative to the bottom chip.
2. The bonding compensation method according to claim 1, wherein the constructing a compensation amount of a setting position of the rewiring layer to be formed including a pre-compensation parameter with respect to each of the top chips comprises:
and decomposing the pre-compensation parameters of the setting position of the rewiring layer to be formed relative to the bottom chip according to the offset of each top chip to obtain the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip.
3. The bond compensation method of claim 1, wherein the pre-compensation parameters comprise: a first offset component along a first direction, a second offset component along a second direction, and an angle parameter; wherein the first direction and the second direction are perpendicular to each other.
4. The bonding compensation method according to claim 3, wherein the constructing a compensation amount of a setting position of the rewiring layer to be formed including a pre-compensation parameter with respect to each of the top chips comprises:
decomposing the angle parameters along the first direction and the second direction respectively to obtain a first angle component and a second angle component;
obtaining a first compensation component of the setting position of the rewiring layer to be formed relative to each top chip along the first direction according to the offset, the first offset component and the first angle component of each top chip;
obtaining a second compensation component of the setting position of the rewiring layer to be formed relative to each top chip along the second direction according to the offset, the second offset component and the second angle component of each top chip;
wherein the first compensation component and the second compensation component constitute the compensation amount.
5. The bonding compensation method according to claim 1, wherein the calculating the pre-compensation parameter with the predetermined error precision as a boundary condition comprises:
and calculating to obtain the pre-compensation parameter according to the condition that the offset of each top chip and the sum of the compensation quantity of the arrangement position of the rewiring layer to be formed relative to each top chip meet the preset error precision.
6. The bonding compensation method of claim 1, wherein after the calculating the pre-compensation parameter, the compensation method further comprises:
calculating to obtain the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip according to the pre-compensation parameters and the offset of each top chip;
and determining the setting position of the rewiring layer to be formed on each top chip according to the offset of each top chip and the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip.
7. The bonding compensation method of claim 1, wherein the predetermined error accuracy of each of the top chips is determined according to a process node of each of the top chips.
8. A bond compensation apparatus, comprising:
the data acquisition module is used for acquiring the offset of the actual bonding position of each top chip relative to the bottom chip and the preset error precision of the setting position of the rewiring layer to be formed on each top chip relative to the bottom chip; wherein a plurality of the top chips are bonded on the bottom chip;
the data calculation module is used for constructing compensation quantities of the setting position of the rewiring layer to be formed, which contains pre-compensation parameters, relative to each top chip, and calculating the pre-compensation parameters by taking the preset error precision as a boundary condition; the pre-compensation parameter is a compensation parameter of the setting position of the rewiring layer to be formed relative to the bottom chip.
9. The bonding compensation apparatus of claim 8, wherein the data calculation module is further configured to calculate the compensation amount of the setting position of the redistribution layer to be formed with respect to each of the top chips according to the pre-compensation parameter and the offset of each of the top chips;
the device further comprises:
and the wiring module is used for determining the setting position of the rewiring layer to be formed on each top chip according to the offset of each top chip and the compensation quantity of the setting position of the rewiring layer to be formed relative to each top chip.
10. A chip rewiring method is characterized by comprising the following steps:
providing at least one bottom chip having a plurality of top chips bonded thereto;
the setting position of a rewiring layer to be formed on the bottom chip is determined by the bonding compensation method of claim 6.
11. The chip rewiring method of claim 10, wherein the wiring method further comprises:
determining a compensation amount between the setting position of the rewiring layer to be formed and the offset according to the setting position of the rewiring layer to be formed and the offset of the corresponding top chip;
and compensating the alignment precision of the photoetching process for forming the rewiring layer according to the compensation amount between the setting position of the rewiring layer to be formed and the offset.
12. A bonding structure, comprising:
at least one bottom chip having a plurality of top chips bonded thereto;
a rewiring layer arranged on each top chip; the compensation quantity between the setting position of the rewiring layer of each top chip and the offset of the actual bonding position of each top chip relative to the bottom chip respectively meets the boundary condition of each top chip; the boundary condition is the preset error precision of the setting position of the rewiring layer on each top chip relative to the bottom chip.
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