CN114943075A - Physical attack detection method and device, processor assembly and chip - Google Patents

Abstract

A method and a device for detecting physical attack, a processor assembly and a chip are provided, the method comprises the following steps: acquiring output signals of a plurality of processors, wherein input signals of the plurality of processors are the same, and the plurality of processors run the same computer program; and judging whether the output signals of the processors are consistent or not, and if not, determining that at least one of the processors is attacked physically. By the scheme provided by the invention, the physical attack condition can be quickly identified.

Description

Physical attack detection method and device, processor assembly and chip

Technical Field

The invention relates to the technical field of information security, in particular to a method and a device for detecting physical attack, a processor assembly and a chip.

Background

In recent years, with the progress of informatization and intellectualization, the application of information security in various fields is more and more extensive, and the information security relates to important fields such as finance, communication, energy, traffic, medical treatment, national defense and the like. Chips often store important information and therefore chips are often at risk of being attacked, a physical attack being one of the common types of attacks. Physical attacks are usually snooping and destroying (e.g., splitting, physically cloning, etc.) the physical characteristics (e.g., voltage, clock, energy radiation, etc.) of the chip by physical means (e.g., by means of associated instrumentation, etc.) to obtain internal programs or data.

Therefore, a solution capable of rapidly identifying physical attacks is needed, so as to protect the information security of the chip.

Disclosure of Invention

The invention aims to provide a method capable of quickly identifying physical attack.

In order to solve the above technical problem, an embodiment of the present invention provides a method for detecting a physical attack, where the method includes: acquiring output signals of a plurality of processors, wherein input signals of the plurality of processors are the same, and the plurality of processors run the same computer program; and judging whether the output signals of the processors are consistent or not, and if not, determining that at least one of the processors is attacked physically.

Optionally, the number of processors is 2.

Optionally, the method further includes: if at least one of the plurality of processors is determined to be under physical attack, sending an interrupt signal to the plurality of processors, the interrupt signal indicating physical attack; and/or modifying the access addresses of the plurality of processors to preset addresses if at least one of the plurality of processors is determined to be physically attacked.

Optionally, the method further includes: and determining the processors which are attacked physically in the plurality of processors according to the output signals of the plurality of processors.

Optionally, the input signal includes: a clock signal and a reset signal.

The embodiment of the invention also provides a detection device for physical attack, which comprises: the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring output signals of a plurality of processors, input signals of the plurality of processors are the same, and the plurality of processors run the same computer program; and the judging module is used for judging whether the output signals of the processors are consistent or not, and if not, determining that at least one of the processors is attacked physically.

The embodiment of the present invention further provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for detecting a physical attack are executed.

The embodiment of the present invention further provides a computing device, which includes a memory and a processor, where the memory stores a computer program that can be executed on the processor, and the processor executes the steps of the above-mentioned physical attack detection method when executing the computer program.

An embodiment of the present invention further provides a processor component, where the processor component includes: a plurality of processors, wherein input signals of the plurality of processors are the same and the plurality of processors have the same computer program running thereon; and the wrapper is used for executing the steps of the detection method of the physical attack.

The embodiment of the invention also provides a chip which comprises the processor assembly.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

the scheme of the embodiment of the invention provides a multi-processor architecture, input signals of a plurality of processors are kept consistent, and the same computer program runs on the plurality of processors. That is, multiple processors operate synchronously. Under the structure, the output signals of the plurality of processors can be acquired, and when the output signals of the plurality of processors are detected to be inconsistent, at least one of the plurality of processors can be determined to be under physical attack. Compared with the prior art, the embodiment of the invention can judge whether physical attack exists by comparing the output signals by increasing the number of the processors. Upon detecting an inconsistency in the output signals of the plurality of processors, it may be determined that at least one processor is under physical attack. By adopting the scheme, no complex algorithm is needed, so that the situation of physical attack can be quickly identified

Further, in the solution of the embodiment of the present invention, if it is determined that at least one of the plurality of processors is under physical attack, an interrupt signal is sent to the plurality of processors, and/or an access address of the plurality of processors is modified to a preset address. By adopting the scheme, the running state of the processor can be adjusted, so that physical attack can be resisted, and the data of the chip can be prevented from being further stolen.

Drawings

FIG. 1 is a diagram illustrating a chip architecture according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a wrapper according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating a method for detecting a physical attack according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a physical attack detection device in an embodiment of the present invention.

Detailed Description

As described in the background, there is a need for a method that can quickly identify physical attacks.

Currently, physical attacks can be classified into three types based on whether a chip is destroyed after being attacked: invasive attacks, semi-invasive attacks, and non-invasive attacks. Among them, the invasive attack usually adopts the micro-probing technique to directly access the inside of the chip, the semi-invasive attack usually also needs to open the package of the chip, but does not need to contact with the internal circuit of the chip, and the non-invasive attack usually needs to measure or disturb the voltage, current, clock, reset signal, etc. of the chip.

In an actual scene, the intrusive attack and the semi-intrusive attack need to open a packaging layer of a chip at the position of a processor so as to attack the processor, so that the processor is in an abnormal operating state, and data is stolen. In the non-invasive attack, it is usually necessary to find the clock signal line and the reset signal line of the processor, and then attack the clock signal, the reset signal, and the like. Therefore, existing approaches to physical attacks are typically performed for on-chip processors.

To this end, the embodiments of the present invention provide a method for detecting a physical attack, and the solution of the embodiments of the present invention provides a multiprocessor architecture, where input signals of a plurality of processors are kept consistent, and the plurality of processors run the same computer program. That is, multiple processors operate synchronously. Under the structure, the output signals of the plurality of processors can be acquired, and when the output signals of the plurality of processors are detected to be inconsistent, at least one of the plurality of processors can be determined to be under physical attack. Compared with the prior art, the embodiment of the invention can judge whether physical attack exists by comparing the output signals by increasing the number of the processors. Upon detecting an inconsistency in the output signals of the plurality of processors, it may be determined that at least one processor is under physical attack. By adopting the scheme, no complex algorithm is needed, so that the situation of physical attack can be quickly identified.

In the embodiment of the present invention, the processor may be any of various conventional devices having data receiving and data processing capabilities, for example, the processor may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processing (DSP) unit, or the like, and the embodiment of the present invention is not limited thereto.

It should be noted that, in the solution of the embodiment of the present invention, the multiple processors refer to multiple processors of the same type and the same purpose.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 1, fig. 1 is a schematic diagram of a chip according to an embodiment of the present invention. As shown in fig. 1, the chip 10 may include: a processor assembly 100, a bus 200, a first memory 300, a second memory 400, and an external device 500.

In one embodiment, the Chip 10 may be a System on Chip (SoC), which is an integrated circuit with a dedicated target that contains the entire System and has the entire contents of the embedded software. In other embodiments, the chip 10 may also be other types of chips, which is not limited in this embodiment.

In the prior art, one or more processors are typically integrated on a chip, each processor being configured to perform a different data processing task. The scheme of the embodiment of the invention is to expand each processor on the existing chip into a plurality of processors, and the plurality of processors work synchronously.

In other words, the processor components corresponding to each processor on the chip in the prior art generally only include: a single processor and its wrapper. In the solution of the embodiment of the present invention, the processor component 100 corresponding to each processor includes: a plurality of processors and a wrapper. The processors in the processor assembly 100 are the same processor, and the processors operate synchronously.

It should be noted that, the number of processors in the processor assembly 100 is not limited by the embodiment of the present invention. As shown in fig. 1, in a specific example, the number of processors in the processor assembly 100 may be 2, that is, the plurality of processors may include: a first processor and a second processor.

Further, the processor assembly 100 may include a Wrapper (Wrapper). Specifically, a plurality of processors are integrated inside the wrapper to constitute the processor assembly 100. In one specific example, the processor in the processor assembly 100 is a CPU and the wrapper is a CPU wrapper.

In an implementation, a wrapper is coupled to bus 200, and the plurality of processors may interact with the bus via the wrapper.

Further, the wrapper is connected to the first memory 300 and the second memory 400 through the bus 200. One of the first Memory 300 and the second Memory 400 may be a Random Access Memory (RAM), and the other may be a Read Only Memory (ROM). In other embodiments, the processor assembly 100 may also include other types of memories, which are not limited by the embodiment.

Further, the wrapper may be connected to an external device (peripheral device)500 through a bus 200. The external device 500 may be various other devices on the chip 10 except the processor assembly 100, the first memory 300 and the second memory 400 for data interaction with the processor, for example, may be other processor assemblies on the chip 10 except the processor assembly 100. The external device 500 may be a device external to the chip 10, and the external device 500 is not limited in this embodiment.

Referring to fig. 2, fig. 2 is a schematic diagram of a wrapper according to an embodiment of the present invention. The synchronous operation of multiple processors in a processor assembly according to embodiments of the present invention is illustrated and described below in conjunction with FIGS. 1 and 2, without limitation.

As shown, the wrapper in the processor assembly 100 provides the same input signal to multiple processors.

In an implementation, a clock circuit (not shown) is also disposed on the chip 10, and may be used to generate a clock signal, and the wrapper is electrically connected to the clock circuit and provides the clock signal to the plurality of processors.

Specifically, the clock signals received by the plurality of processors are clock signals of the same source, in other words, the clock signals of the plurality of processors are the same. By adopting the scheme, the attack to the clock signal can be effectively resisted.

More specifically, by adopting the detection method provided by the invention, the attack to the clock signal of any processor can be detected, but the clock signal which attacks each processor simultaneously is difficult to realize. Therefore, the scheme provided by the invention can effectively resist the attack of the external to the clock signal.

Further, a reset circuit (not shown) is disposed on the chip 10, and the reset circuit can be used for generating a reset signal. The wrapper is electrically connected to the reset circuit to provide a reset signal to the plurality of processors.

Specifically, the reset signals received by the plurality of processors are homologous reset signals. In other words, the reset signals of the plurality of processors are the same. By adopting the scheme, the attack of the outside on the reset signal can be effectively resisted.

More specifically, by adopting the detection method provided by the invention, the attack to the reset signal of any processor can be detected, but the simultaneous attack to the reset signal of each processor is difficult to realize. Therefore, the scheme provided by the invention can effectively resist the attack of the outside on the reset signal.

Further, the input signals of the plurality of processors may further include: a control signal. Wherein the control signals input to the plurality of processors are identical. In a specific implementation, the control signal may originate from other processor components on the chip 10 besides the processor component 100, or may originate from outside the chip 10, which is not limited in this embodiment.

Further, the same computer program is run on multiple processors. More specifically, boot addresses of the plurality of processors are the same.

It should be noted that, in the solution of the embodiment of the present invention, the multiple processors in the processor assembly 100 are independent from each other, that is, there is no interaction of data between the multiple processors, and each processor calculates independently.

Thus, since the input signals of the multiple processors in the processor assembly 100 are the same and the same computer program is run on the multiple processors, the multiple processors operate synchronously. Further, in the case where none of the processors in the processor assembly 100 is physically attacked, the output signals of the processors should be the same, and at this time, the wrapper may output the output signal of any one of the processors to the bus 200. If there is an inconsistency in the output signals of the processors, it can be determined that there is a physical attack on one or more of the processors in the processor assembly 100.

Referring to fig. 3, fig. 3 is a schematic flowchart of a method for detecting a physical attack in an embodiment of the present invention. The method illustrated in fig. 3 may be performed by various existing devices having data transmission and data processing capabilities.

In one particular example, this may be performed by the wrapper of FIG. 1. With this scheme, the power of the wrapper can be fully utilized, and the method shown in fig. 3 can be executed without adding special devices on the chip. In other embodiments, the detection device may also be disposed on a chip to implement the scheme shown in fig. 3, which is not limited by the embodiments of the present invention.

The method illustrated in fig. 3 may comprise the steps of:

step S31: acquiring output signals of a plurality of processors, wherein input signals of the plurality of processors are the same, and the plurality of processors run the same computer program;

step S32: and judging whether the output signals of the processors are consistent or not, and if not, determining that at least one of the processors is attacked physically.

It is understood that in a specific implementation, the method may be implemented by a software program running in a processor integrated within a chip or a chip module; alternatively, the method can be implemented in hardware or a combination of hardware and software.

In a specific implementation of step S31, output signals may be obtained from a plurality of processors, wherein the output signals may include: status signals and read and write signals.

In particular, the status signal may be used to indicate an operational status of the processor. More specifically, the operating state may be any one of: suspended, locked, idle, running normally, etc.

Further, the read and write signals may include an access address and data to be read and written. That is, the read-write signal is used to write data to be written to the access address, or to read data to be read from the access address.

In the implementation of step S32, it may be determined whether the output signals of the plurality of processors are consistent.

As shown in fig. 2, it can be determined whether the status signal of the first processor and the status signal of the second processor are consistent, and whether the read/write signal of the first processor and the read/write signal of the second processor are consistent.

With continued reference to FIG. 3, if the output signals of the plurality of processors are not consistent, it may be determined that at least one of the plurality of processors is under physical attack.

Further, after determining that at least one of the plurality of processors is physically attacked, an interrupt signal may be sent to the plurality of processors to indicate to the respective processors that at least one of the plurality of processors is physically attacked. Accordingly, each processor may respond to the interrupt signal in a preconfigured manner. The specific response mode for the interrupt signal can be set according to the actual application scenario.

Furthermore, the access addresses of the processors can be modified into preset addresses. The preset address may be a preset invalid address. More specifically, the invalid address refers to an address where data can be stored for external access or without security requirements. By adopting the scheme, the physical attack can be resisted, and the data is prevented from being stolen from the outside.

In one non-limiting example of the present invention, the processor that is under physical attack may also be determined from the output signals of the plurality of processors.

Specifically, the number of the plurality of processors may be greater than 2, the output signals of every two processors may be compared, and if there is a case where there is inconsistency between the output signal of any one processor and the output signals of at least two other processors, the any one processor may be determined to be an exception processor. The other processor refers to a processor other than any one of the processors.

For example, the number of the plurality of processors is 3, and the plurality of processors includes: the processor comprises an A processor, a B processor and a C processor, and if the output signal of the C processor is inconsistent with the output signal of the A processor and the output signal of the C processor is inconsistent with the output signal of the B processor, the C processor can be determined as an exception processor.

It should be noted that the exception handler determined by the above method is a handler with a high probability of being attacked physically. In an actual application scenario, since the difficulty of simultaneously performing a physical attack on two or more processors is high, for this reason, the exception handler determined by the above method may also be regarded as the actual processor under attack.

Furthermore, the reminding information can be sent to the terminal bound by the user, and the reminding information can be used for indicating that the processor is subjected to physical attack and indicating the abnormal processor determined by the scheme, so that reference is provided for the user to check the physical attack, and the efficiency of determining the processor actually subjected to the physical attack by the user is improved.

Further, the access address of the exception handler may be modified to the preset address, and/or an interrupt signal may be sent to the exception handler.

Accordingly, the interrupt signal may not be sent to the other processors of the plurality of processors other than the exception handler, and the access addresses of the other processors may not be modified. Therefore, the physical attack can be rapidly identified, and the normal operation of the chip can be ensured.

Therefore, the scheme provided by the embodiment of the invention can quickly identify physical attack and effectively resist the physical attack, thereby realizing effective protection of the processor and the chip.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a physical attack detection apparatus in an embodiment of the present invention. The apparatus shown in fig. 4 may include:

an obtaining module 41, configured to obtain output signals of multiple processors, where input signals of the multiple processors are the same, and the multiple processors have the same computer program running thereon;

and the judging module 42 is configured to judge whether the output signals of the plurality of processors are consistent, and if not, determine that at least one of the plurality of processors is under physical attack.

In a specific implementation, the detection device of the physical attack may correspond to a chip having a data processing function in the terminal; or to a chip module having a data processing function in the terminal, or to the terminal.

For more details about the operation principle, the operation mode, the beneficial effects, and the like of the physical attack detection apparatus shown in fig. 4, reference may be made to the above description about fig. 1 to fig. 3, which is not repeated herein.

The embodiment of the present invention further provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for detecting a physical attack are executed. The storage medium may include ROM, RAM, magnetic or optical disks, etc. The storage medium may further include a non-volatile memory (non-volatile) or a non-transitory memory (non-transient), and the like.

The embodiment of the present invention further provides a computing device, which includes a memory and a processor, where the memory stores a computer program that can be executed on the processor, and the processor executes the steps of the above-mentioned physical attack detection method when executing the computer program. The computing equipment can be a mobile phone, a computer, internet of things equipment and the like.

The embodiment of the present invention further provides a chip, which may be, for example, the chip 10 shown in fig. 1. For more about the chip, reference may be made to the description of fig. 1, and details are not repeated here. In one particular example, the chip may be an on-board chip.

It should be understood that, in the embodiment of the present application, the processor may be a Central Processing Unit (CPU), and the processor may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will also be appreciated that the memory in the embodiments of the subject application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example and not limitation, many forms of Random Access Memory (RAM) are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (enhanced SDRAM), SDRAM (SLDRAM), synchlink DRAM (SLDRAM), and direct bus RAM (DR RAM).

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. The procedures or functions according to the embodiments of the present application are wholly or partially generated when the computer instructions or the computer program are loaded or executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer program may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly.

In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and system may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative; for example, the division of the unit is only a logic function division, and there may be another division manner in actual implementation; for example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be physically included alone, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit. For example, for each device or product applied to or integrated into a chip, each module/unit included in the device or product may be implemented by hardware such as a circuit, or at least a part of the module/unit may be implemented by a software program running on a processor integrated within the chip, and the rest (if any) part of the module/unit may be implemented by hardware such as a circuit; for each device or product applied to or integrated with the chip module, each module/unit included in the device or product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules/units may be implemented by using a software program running on a processor integrated within the chip module, and the rest (if any) of the modules/units may be implemented by using hardware such as a circuit; for each device and product applied to or integrated in the terminal, each module/unit included in the device and product may be implemented by hardware such as a circuit, different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules/units may be implemented by a software program running on a processor integrated in the terminal, and the rest (if any) part of the modules/units may be implemented by hardware such as a circuit.

It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document indicates that the former and latter related objects are in an "or" relationship.

The "plurality" appearing in the embodiments of the present application means two or more.

The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for illustrating and differentiating the objects, and do not represent the order or the particular limitation of the number of the devices in the embodiments of the present application, and do not constitute any limitation to the embodiments of the present application.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A method for detecting a physical attack, the method comprising:

acquiring output signals of a plurality of processors, wherein input signals of the plurality of processors are the same, and the plurality of processors run the same computer program;

and judging whether the output signals of the processors are consistent or not, and if not, determining that at least one of the processors is attacked physically.

2. The method of claim 1, wherein the number of processors is 2.

3. The method for detecting physical attacks according to claim 1, wherein the method further comprises:

if at least one of the plurality of processors is determined to be physically attacked, sending an interrupt signal to the plurality of processors, the interrupt signal indicating physical attack;

and/or the presence of a gas in the gas,

if at least one of the plurality of processors is determined to be physically attacked, the access addresses of the plurality of processors are modified to a preset address.

4. The method for detecting physical attacks according to claim 1, wherein the method further comprises:

and determining the processors which are attacked physically in the plurality of processors according to the output signals of the plurality of processors.

5. The method of detecting a physical attack of claim 1, wherein the input signal comprises: a clock signal and a reset signal.

6. An apparatus for detecting a physical attack, the apparatus comprising:

the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring output signals of a plurality of processors, input signals of the plurality of processors are the same, and the plurality of processors run the same computer program;

and the judging module is used for judging whether the output signals of the processors are consistent or not, and if not, determining that at least one of the processors is attacked physically.

7. A storage medium having a computer program stored thereon, the computer program, when being executed by a processor, performing the steps of the method of detecting a physical attack according to any one of claims 1 to 5.

8. A computing device comprising a memory and a processor, said memory having stored thereon a computer program operable on said processor, characterized in that said processor, when executing said computer program, performs the steps of the method of detection of a physical attack according to any one of claims 1 to 5.

9. A processor assembly, comprising:

a plurality of processors, wherein input signals of the plurality of processors are the same and the plurality of processors have the same computer program running thereon;

a wrapper for performing the steps of the method of detecting a physical attack of any one of claims 1 to 5.

10. A chip comprising the processor assembly of claim 9.

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