CN114938135A

CN114938135A - Multi-mode active transient response control method applied to buck converter

Info

Publication number: CN114938135A
Application number: CN202210445598.XA
Authority: CN
Inventors: 孙伟锋; 陆天伦; 崔浩然; 张海青; 高源�; 徐申; 时龙兴
Original assignee: Southeast University-Wuxi Institute Of Integrated Circuit Technology; Southeast University
Current assignee: Southeast University-Wuxi Institute Of Integrated Circuit Technology; Southeast University
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2022-08-23

Abstract

The invention discloses a multi-mode active transient response control method applied to a buck converter, wherein the buck converter comprises a basic topology power stage and a control stage; the basic topology power stage comprises an input power Vin, an upper tube MOS1, a lower tube MOS2, an inductor L and a parasitic resistor R thereof _L Output capacitor C _O And a load R _O (ii) a The control stage includes a controller and an ATR control module. The active transient response control signal is generated by a comparison algorithm by detecting the magnitude, slope and average phase current of the output voltage. Compared with the traditional active transient response control method, the method can more quickly stabilize the output voltage overshoot generated when the load is switched from the heavy load to the light load.

Description

Multi-mode active transient response control method applied to buck converter

Technical Field

The invention belongs to the field of switching power supplies, and particularly relates to a multi-mode active transient response control method applied to a buck converter.

Background

In recent years, with the continuous progress of science and technology, various electronic devices appear in the lives of people, and various portable wearable electronic devices such as mobile phones, smart watches and tablet computers, as well as automobile electronics and medical appliances affect and improve the lives of people. The development trends of the electronic products are the same, namely, the electronic products are continuously developed towards the directions of lightness, thinness, portability and endurance, which means that the sizes of the electronic products are gradually reduced, the integration level is higher and higher, and simultaneously, the functions are richer and richer, so that higher and higher requirements are put forward for a power supply part serving as the core of the electronic products.

At present, the development trend of the switching power supply mainly focuses on high efficiency, small area, fast transient response and large driving capability, the trends mean that the power consumption and current of a chip can rise in multiples, the power supply with low voltage and large current reaching 1V/1000A level becomes a normal state, in the estimated 2022 year, the dynamic current variation can reach 800A, the slope can reach 2000A/us, the power consumption and dynamic promotion are higher and higher in power supply requirements, and how to realize the fast stabilization of output voltage during load switching is a current big problem.

At present, in a step-down DC-DC converter, the most mature technology applied to load switching is the ATR (active transient response) technology, which can effectively improve the overshoot generated when the load is switched from a heavy load to a light load, the ATR is divided into an internal ATR and an external ATR, the internal ATR is that the converter enters a high-impedance state by quickly turning off an upper tube and a lower tube of the converter when the load is switched from the heavy load to the light load, so that the output end can stop supplying power to the load, and the decreasing rate of the inductor current can be increased by the forward voltage drop of a body diode, thereby accelerating the discharging speed of an output capacitor and reducing the overshoot of the load. External ATR is generally applied to a buck converter with an extra transistor on the load side, and when the output side receives a load switching signal, the parallel transistor on the output side is turned on to let the current drain, thereby reducing the overshoot of the load.

Although the traditional ATR technology can effectively improve the overshoot generated when the load is switched from the heavy load to the light load, the subsequent fluctuation process of the output voltage after the overshoot is reduced is ignored, namely when the output voltage is reduced to the expected voltage, the output voltage cannot be kept stable immediately, the fluctuation can be generated continuously, the fluctuation can affect the working performance of an electronic product connected with a load end and the stability of the whole power supply system, so that the problem that how to reduce the fluctuation of the output voltage after ATR regulation is very important is solved, the scheme of continuously realizing ATR fine regulation by judging the comparison between the load current and the output voltage and a fixed threshold value exists in the market at present, but the problems that the response to output jump is too slow, the regulation is not timely, the control logic is more complex and the like exist, the output voltage still has larger fluctuation, and the chip on the market at present is considered to be very sensitive to the voltage, this is a significant disadvantage for DC-DC converters.

Disclosure of Invention

The invention aims to provide a multi-mode active transient response control method applied to a buck converter, and aims to solve the technical problems that the traditional ATR technology is too slow in response to output jump, not timely in adjustment, complex in control logic and large in fluctuation of output voltage.

In order to solve the technical problems, the specific technical scheme of the invention is as follows:

a multi-mode active transient response control method applied to a buck converter, the buck converter comprising a base topology power stage and a control stage;

the basic topology power stage comprises an input power Vin, an upper tube MOS1, a lower tube MOS2, an inductor L and a parasitic resistor R thereof _L An output capacitor C _O And a load R _O (ii) a The input power Vin is connected to the upper MOS1 and then divided into two paths, one path connecting the lower MOS2 to ground and the other pathThrough the inductor L to the load R _O Output capacitance C _O And a load R _O In parallel, the MOS1 stores charge, when on, the MOS1 transfers Vin to the load, and the MOS2 and the inductor L freewheel the load loop when the MOS1 is off;

the control stage comprises a controller and an ATR control module;

the multi-mode active transient response control method applied to the buck converter comprises the following steps:

step 1, AVP samples an inductive current signal, a sampling signal of reference voltage Vref and VOUT enters a controller to generate PWM signals for controlling an upper tube MOS1 and a lower tube MOS2, an ATR control module receives an output voltage sampling signal, outputs a voltage slope signal and an output current signal to generate a control signal ATRZ, the control signal ATRZ and the PWM signal participate in controlling the upper tube MOS1 and the lower tube MOS2 to form an internal ATR, and the internal ATR generates a signal to directly control and load R _O The parallel bleeder transistor MOS3 forms an external ATR;

step 2, the AVP window of the output voltage is VavpL-VavPH, when the load is switched from heavy load to light load, the stable output voltage is changed from VavpL to VavPH due to the AVP window;

step 3, detecting the slope of the output voltage, if the slope of the voltage is in a hysteresis interval from being greater than VthH to being reduced to VthL, indicating that the change of the output voltage is violent at the moment, and continuously detecting whether the condition of rough adjustment starting is met; if the output voltage is already greater than VavpM, wherein VavpM is a value between VavpL and VavpH, and the average current is greater than Ith, generating a coarse ATR signal, and if the subsequent condition is not met, continuing to return to step 3 for detection;

step 4, if the output voltage slope is not in a hysteresis interval from being greater than VthH to descending VthL, which indicates that the output voltage changes more smoothly at the moment, continuously detecting whether the condition of starting fine adjustment is met; if the output voltage is in a hysteresis interval from being larger than VavpH + d1 to being reduced to VavpH + d2, a fine-tuning ATR signal is generated, if the output voltage after one fine tuning still meets the conditions required by the fine tuning, the fine-tuning signal is continuously generated until the output voltage is lower than VavpH + d2, wherein d1 and d2 are smaller than VavpH, and d1> d 2.

Further, the ATR control module comprises five comparators, 2 pulse generators, 3 and gates and 2 or gates; the comparators comprise a first comparator C1, a second comparator C2, a third comparator C3, a fourth comparator C4, a fifth comparator C5; the pulse generators include a first pulse generator U1 and a second pulse generator U2; the AND gate comprises a first AND gate U4, a second AND gate U5 and a third AND gate U6, and the OR gate comprises a first OR gate U3 and a second OR gate U7;

the ATR control module samples output voltage slope and output voltage, output current and generates control signal ATRZ, including the following steps: VFB samples half of the output voltage, the first pulse generator U1 generates a coarse pulse of 2us when the output voltage is greater than VavpL + d3 (the specific magnitude is determined by the voltage at the reverse end of comparator C2), the first comparator C1 outputs a high level when the output voltage is greater than VavpH + d4 (the specific magnitude is determined by the voltage at the reverse end of comparator C1), such that the first and gate U4 outputs a high level during the period when the output voltage rises from VavpL + d3 to the peak and then falls to VavpH + d4, the output voltage slope is compared with the hysteresis threshold by the fourth comparator C4 when the load is switched from heavy load to light load, the fourth comparator C4 outputs a high level when the voltage slope is greater than VthH to fall to VthL, the main phase current is greater than Ith + C1 (the specific magnitude is determined by the voltage at the comparator C5), the fourth comparator C4, the fifth comparator C5 output and the first OR gate U3 output three AND phases, if the fourth comparator C4, the fifth comparator C5, the first OR gate U3 output high level at the same time, the second OR gate U7 generates the coarse tuning signal ATRZ; if the output voltage is in the hysteresis interval from greater than vavpph + d1 to vavpph + d2, the second pulse generator U2 generates a fine-tuning pulse of 250ns, and if the voltage slope is not in the hysteresis interval from greater than VthH to falling to VthL, the second and gate U5 delivers the fine-tuning pulse to the second or gate U7 to output the ATRZ signal.

The multi-mode active transient response control method applied to the buck converter has the following advantages:

1. the invention determines the ATR window by sampling three standards of output voltage, output voltage slope and main phase average current, thus the invention can more accurately and more timely detect the occurrence of load switching compared with the traditional ATR scheme by only using the output voltage standard, thereby more quickly generating ATR signal for regulation, and leading the step-down DC-DC converter adopting the scheme of the invention to have faster response speed when the load jumps.

2. The ATR control provided by the invention comprises two regulation modes, namely a rough regulation mode and a fine regulation mode, and when load jump in a larger range occurs, coarse regulation is realized, namely an ATR signal with larger pulse width is generated; when the output is still unstable after coarse adjustment or the load jumps in a small range near a steady state, fine adjustment is realized, namely a plurality of ATR signals with smaller pulse width are generated, so that the system is switched back and forth between the steady state and the ATR state (the upper tube and the lower tube are simultaneously turned off), thereby reducing the voltage fluctuation faster than the traditional ATR.

3. The ATR signal generating logic generates a coarse tuning signal by comparing the slope of the output voltage with the threshold slope, and then determines whether to generate and when to stop generating the fine tuning ATR signal by comparing the voltage magnitude with the threshold voltage.

Drawings

FIG. 1 is a circuit diagram of a buck converter of the present invention;

FIG. 2 is a flow chart of multi-mode ATR signal generation according to the present invention;

FIG. 3 is a schematic diagram of a multi-mode ATR signal generation circuit of the present invention;

FIG. 4 is a schematic of the internal ATR of the present invention;

FIG. 5 is a schematic diagram of an external ATR of the present invention;

FIG. 6 is a SIMPLIS simulation waveform of the multimode ATR of the present invention.

Detailed Description

For better understanding of the purpose, structure and function of the present invention, a multi-mode ATR (active transient response) control method applied to a BUCK converter according to the present invention will be described in further detail with reference to the accompanying drawings.

As shown in fig. 1, the buck converter includes a basic topology power stage and a control stage.

The basic topology power stage comprises an input power Vin, an upper tube MOS1, a lower tube MOS2, an inductor L and an output capacitor C _O And a load R _O . Vin is communicated with an upper tube MOS1 and then is divided into two paths, one path is connected with a lower tube MOS2 to the ground, and the other path reaches a load R through an inductor L _O Output capacitance C _O And a load R _O In parallel, storing charge, MOS1 delivers Vin to the load when on, MOS2 and inductor L freewheel the load loop when MOS1 is off.

The control stage includes a controller and an ATR control module.

AVP (adaptive voltage regulation) sampling inductance current signals, enabling sampling signals of reference voltages Vref and VOUT to enter a controller to generate PWM (pulse-width modulation) signals for controlling an upper tube MOS1 and a lower tube MOS2, enabling an ATR (auto-regressive voltage) control module to receive output voltage sampling signals, enabling output voltage slope signals and output current signals to generate control signals ATRZ, enabling the control signals ATRZ and the PWM signals to participate in controlling the upper tube MOS1 and the lower tube MOS2 to form an internal ATR, and enabling the internal ATR to generate signals to directly control and load R _O The parallel bleed transistor MOS3 forms the external ATR, and these components form a schematic of the multi-mode ATR controlled BUCK circuit of the present invention.

The second diagram shows a flow chart of multi-mode ATR signal generation, the AVP window of the output voltage of the invention is 920 mV-970 mV, when the load is switched from heavy load to light load, because of the existence of the AVP window, the steady state output voltage is changed from 920mV to 970mV, at this time, the slope of the output voltage is firstly detected, if the load rising slope is in the hysteresis interval (value after low pass filter gain) from more than 3mV to-5 mV, the change of the output voltage is sharp, it is indicated that whether the rough adjustment condition is met or not is continuously detected, if the output voltage is already more than 950mV at this time, and the average current is more than 40mV (value after low pass filter gain), the rough adjustment ATR signal is generated, if the subsequent condition is not met, the return detection is continuously performed, and the rough adjustment is started again when the output voltage meets the condition; if the output voltage slope is not in the hysteresis interval from more than 3mv to-5 mv, which indicates that the output voltage changes more smoothly, the method continues to detect whether the condition for starting fine adjustment is met, at this time, if the output voltage is in the hysteresis interval from more than 971.75mv to 970.25mv (the output voltage returns to the expected voltage level), the fine-adjustment ATR signal is generated, and if the output voltage after one fine adjustment still meets the condition for fine adjustment, the fine-adjustment signal continues to be generated until the output voltage is lower than 970.25 mv.

Fig. 3 is a specific circuit diagram of the multi-mode ATR signal generation consisting of five comparators, 2 pulse generators, 3 and gates and 2 or gates. The comparators include a first comparator C1, a second comparator C2, a third comparator C3, a fourth comparator C4, and a fifth comparator C5. The pulse generator comprises a first pulse generator U1 and a second pulse generator U2, the AND gate comprises a first AND gate U4, a second AND gate U5, a third AND gate U6, the OR gate comprises a first OR gate U3, a second OR gate U7, VFB samples half of the output voltage, the first pulse generator U1 generates a coarse regulation pulse of 2us when the output voltage is greater than 930mv, the first comparator C1 outputs a high level when the output voltage is greater than 975mv, so that the first AND gate U4 outputs a high level during the output voltage rises from 930mv to the peak and then falls to 975mv, corresponding to the process that the output voltage overshoots when the load is switched from heavy load to light load, the output voltage slope dvout _ dt is compared with a hysteresis threshold value by a hysteresis fourth comparator C4, if dvout _ is in a hysteresis interval of greater than 3mv to-5 mv, the fourth comparator C5 outputs a high level, and the output current C4 is greater than the fifth comparator C5, the fourth comparator C4, the fifth comparator C5 output and the first OR gate U3 output three AND phases, if the fourth comparator C4, the fifth comparator C5, the first OR gate U3 output high level at the same time, the second OR gate U7 generates the coarse tuning signal ATRZ; if the output voltage is in the hysteresis range from greater than 971.75mv to 970.25mv, the second pulse generator U2 generates a 250ns fine pulse, and if dvout _ dt is not in the hysteresis range from greater than 3mv to-5 mv, the second and gate U5 delivers the fine pulse to the second or gate U7 to output the ATRZ signal, so that the circuit as a whole implements the multi-mode ATR signal generation flow illustrated in fig. 2.

Fig. 4 is a schematic diagram of an internal ATR, which is composed of a control signal, an ATRZ signal, an and gate, a dead zone generator, a transmission gate and MOS1 and MOS2, the ATR control signal generated in fig. 3 and the signal generated by the controller generate signals for finally controlling the upper tube MOS1 and the lower tube MOS2 in fig. 1 after a dead zone delay through an and gate, so as to realize that the internal ATR directly closes the upper tube MOS1 and the lower tube MOS2 to reduce the overshoot effect of the load caused by heavy load switching to light load, fig. 5 is a schematic diagram of an external ATR, which is composed of an ATRZ signal, a dead zone generator, a transmission gate and a bleeder tube MOS3, and the ATRZ signal generated in fig. 3 after a delay controls the opening and closing of a bleeder charge tube MOS3 connected in parallel to the load end, so as to realize that the external ATR directly discharges the load to reduce the overshoot effect of the load caused by heavy load switching to light load.

Fig. 6 is a simulation waveform diagram of a simplex simulation of a multimode ATR, which is a simulation waveform diagram generated when a load is switched from a heavy load (300A) to a light load (50A), where I1 is a waveform of an ATR signal ATRZ, and output is an output voltage waveform, it can be seen that when a load current drops in a large range, an output voltage generates a large overshoot, at this time, the ATRZ signal generates a high-level pulse with a long time for coarse adjustment, a drain pipe which is on and off a power stage is turned on instantaneously to release charges quickly, it can be seen that an output voltage drops quickly, at this time, a change slope is slow, an ATR control logic detects the change and then generates a plurality of high-level pulses with a short time for control, so that the output voltage fluctuates quickly in a small amplitude near a target output voltage to avoid a large drop of the output voltage and then generates a large fluctuation, it can be seen that a subsequent output voltage fluctuation range is very small, and the ATR stops regulating until the generating condition of the ATR signal is not met, and the output voltage is stabilized at the target voltage. Compared with a general ATR control strategy, the multi-mode ATR control strategy can reduce the fluctuation of the output voltage when the load is switched from a heavy load to a light load more quickly.

It is to be understood that the present invention has been described with reference to certain embodiments, and that various changes in the features and embodiments, or equivalent substitutions may be made therein by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A multi-mode active transient response control method applied to a buck converter, wherein the buck converter comprises a basic topology power stage and a control stage;

the basic topology power stage comprises an input power Vin, an upper tube MOS1, a lower tube MOS2, an inductor L and a parasitic resistor R thereof _L An output capacitor C _O And a load R _O (ii) a An input power Vin is communicated with an upper tube MOS1 and then divided into two paths, one path is connected with a lower tube MOS2 to the ground, and the other path reaches a load R through an inductor L _O Output capacitance C _O And a load R _O In parallel, the MOS1 transfers Vin to a load when being conducted, and the MOS2 and the inductor L freewheel to a load loop when the MOS1 is closed;

the control stage comprises a controller and an ATR control module;

step 2, the AVP window of the output voltage is VavpL-VavpH, when the load is switched from heavy load to light load, the stable output voltage is changed from VavpL to VavpH due to the existence of the AVP window;

step 3, detecting the slope of the output voltage, and if the slope of the voltage is in a hysteresis interval from being greater than VthH to being reduced to VthL, indicating that the change of the output voltage is violent at the moment, and continuously detecting whether the condition of rough adjustment is met; if the output voltage is already greater than VavpM, wherein VavpM is a value between VavpL and VavpH, and the average current is greater than Ith, generating a coarse ATR signal, and if the subsequent condition is not met, continuing to return to step 3 for detection;

step 4, if the slope of the output voltage is not in a hysteresis interval from being greater than VthH to descending VthL, which indicates that the change of the output voltage is more gentle at the moment, continuously detecting whether the condition of starting fine adjustment is met; if the output voltage is in a hysteresis interval from being more than VavpH + d1 to being reduced to VavpH + d2, a fine-tuning ATR signal is generated, if the output voltage after one fine-tuning still meets the required condition of fine-tuning, the fine-tuning signal is continuously generated until the output voltage is lower than VavpH + d2, wherein d1 and d2 are smaller than VavpH, and d1> d 2.

2. The multi-mode active transient response control method applied to a buck converter according to claim 1, wherein the ATR control module comprises five comparators, 2 pulse generators, 3 and gates and 2 or gates; the comparators comprise a first comparator C1, a second comparator C2, a third comparator C3, a fourth comparator C4, a fifth comparator C5; the pulse generator comprises a first pulse generator U1 and a second pulse generator U2; the AND gate comprises a first AND gate U4, a second AND gate U5 and a third AND gate U6, and the OR gate comprises a first OR gate U3 and a second OR gate U7;

the ATR control module samples output voltage slope and output voltage, output current and generates control signal ATRZ, including the following steps: VFB samples half of the output voltage, first pulse generator U1 generates a coarse pulse of 2us when the output voltage is greater than VavpL + d3, the first comparator C1 outputs a high level when the output voltage is greater than vavpph + d4, so that the first and gate U4 outputs a high level in the process of the output voltage rising from VavpL + d3 to a peak value and then falling to vavpph + d4, corresponding to the process that the output voltage generates overshoot when the load is switched from heavy load to light load, the slope of the output voltage is compared with a hysteresis threshold value through a hysteresis fourth comparator C4, if the slope of the voltage is in a hysteresis interval from being greater than VthH to being reduced to VthL, the fourth comparator C4 outputs high level, if the current of a main phase is greater than Ith + C1, the fifth comparator C5 outputs high level, the fourth comparator C4 and the fifth comparator C5 output phase and the first OR gate U3 output phase, and if the fourth comparator C4, the fifth comparator C5 and the first OR gate U3 output high level simultaneously, a coarse tuning signal ATRZ is generated through the second OR gate U7; if the output voltage is in the hysteresis interval from greater than vavpph + d1 to vavpph + d2, the second pulse generator U2 generates a fine-tuning pulse of 250ns, and if the voltage slope is not in the hysteresis interval from greater than VthH to falling to VthL, the second and gate U5 delivers the fine-tuning pulse to the second or gate U7 to output the ATRZ signal.