CN114937738A - Three-dimensional phase change memory based on vertical electrode and preparation method - Google Patents

Three-dimensional phase change memory based on vertical electrode and preparation method Download PDF

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Publication number
CN114937738A
CN114937738A CN202210585419.2A CN202210585419A CN114937738A CN 114937738 A CN114937738 A CN 114937738A CN 202210585419 A CN202210585419 A CN 202210585419A CN 114937738 A CN114937738 A CN 114937738A
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layer
silicon dioxide
phase change
word line
line electrode
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缪向水
王位国
童浩
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/023—Formation of the switching material, e.g. layer deposition by chemical vapor deposition, e.g. MOCVD, ALD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices

Abstract

The invention discloses a three-dimensional phase change memory based on a vertical electrode and a preparation method thereof, wherein the three-dimensional phase change memory comprises: the word line structure comprises a first silicon dioxide layer, a first word line electrode layer, a second silicon dioxide layer, a second word line electrode layer, a third silicon dioxide layer, a third word line electrode layer, a fourth silicon dioxide layer and a fifth silicon dioxide layer which are sequentially arranged from bottom to top, a first through hole vertically arranged in the fifth silicon dioxide layer, a second through hole vertically arranged and a bit line electrode; the bit line electrode extends to the surface of the phase change memory structure through the first through via. In the invention, all the memory units in the same vertical direction share the same bit line electrode, the word line electrode of each memory unit is in the horizontal direction, the functional layer of each memory unit is the functional layer part of the shared bit line electrode opposite to the corresponding word line electrode, and only by increasing the number of layers of the word line electrode layer and the isolation layer, the functional layer only needs to be deposited once, thereby reducing the process complexity.

Description

Three-dimensional phase change memory based on vertical electrode and preparation method
Technical Field
The invention belongs to the field of memories, and particularly relates to a three-dimensional phase change memory based on a vertical electrode and a preparation method thereof.
Background
Phase Change Memory (PCM), a type of nonvolatile memory, is expected to replace flash memory as one of the next generation mainstream memory technologies. In order to improve the storage density and cost competitiveness, the current three-dimensional phase change memory (3D PCM) using three-dimensional stacking is generally concerned by the industry, and the current 3D PCM scheme proposed by Intel et al mainly uses a three-dimensional horizontal stacking method based on a cross-point structure, i.e. each memory cell and the upper and lower adjacent word lines and bit lines are all horizontally arranged, this way, also called horizontal stacking, is simple and easy to implement, but when the number of stacked layers is large, the cost is too high due to excessive photoetching times and etching times, the surface unevenness problem and the side wall covering problem are gradually aggravated, and an inevitable stacking layer number limit exists due to process restriction, in addition, the outstanding thermal crosstalk problem of PCM also limits the further increase of storage density, so a new three-dimensional phase change memory structure and a preparation method thereof are needed.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a three-dimensional phase change memory based on a vertical electrode and a preparation method thereof, and aims to solve the problems of complex structure, high process difficulty and thermal crosstalk when a plurality of stacked layers are formed due to the adoption of a horizontal stacking structure of the three-dimensional phase change memory in the prior art.
The invention provides a three-dimensional phase change memory based on a vertical electrode, which comprises: the word line structure comprises a first silicon dioxide layer, a first word line electrode layer, a second silicon dioxide layer, a second word line electrode layer, a third silicon dioxide layer, a third word line electrode layer, a fourth silicon dioxide layer and a fifth silicon dioxide layer which are sequentially arranged from bottom to top, a first through hole vertically arranged in the center of the fifth silicon dioxide layer, a second through hole vertically arranged in the center of a combination body formed by the first word line electrode layer, the second silicon dioxide layer, the second word line electrode layer, the third silicon dioxide layer, the third word line electrode layer and the fourth silicon dioxide layer, and a bit line electrode; and the bit line electrode extends to the surface of the three-dimensional phase change memory structure through the first through hole.
Furthermore, the second through hole is filled with multiple layers of materials in a sleeve shape, the first carbon layer, the phase change unit layer, the second carbon layer, the gate layer and the third carbon layer are sequentially arranged from outside to inside, and the inner walls of the first carbon layer and the second through hole are tightly connected together.
Furthermore, the first word line electrode layer and the second silicon dioxide layer are periodically repeated in the vertical direction as required, and the number of times of repetition is the same as the number of memory cell layers required by the three-dimensional phase change memory.
Further, all the memory cells in the same vertical direction share the same bit line electrode.
Furthermore, the word line electrode of each memory cell is arranged in the horizontal direction, and the phase change unit layer and the gate layer in each memory cell are the functional layer parts of the common bit line electrode and the corresponding word line electrode.
The invention also provides a preparation method of the three-dimensional phase change memory, which comprises the following steps:
(1) growing a bottom electrode metal material on a silicon substrate by utilizing magnetron sputtering;
(2) growing SiO on the bottom electrode metal prepared in the step (1) by utilizing PECVD 2 ；
(3) Alternately growing the bottom electrode metal material and the SiO by repeating the step (1) and the step (2) 2 Until the number of layers required by the target is reached;
(4) carrying out ultraviolet lithography on the wafer prepared in the step (3) to form a columnar hole structure, etching a through hole, and then stripping off the photoresist;
(5) carrying out ultraviolet alignment on the upper electrode with the hole shape on the columnar hole structure prepared in the step (4), developing the photoresist only, and not stripping the photoresist temporarily, wherein the columnar hole structure prepared in the step (4) is positioned in the center of the upper electrode with the square hole;
(6) sequentially depositing a carbon layer, a phase change unit layer, a carbon layer, a gate tube layer, a carbon layer and an upper electrode layer by magnetron sputtering;
(7) stripping the photoresist spun in the step (5);
(8) carrying out ultraviolet photoetching and etching a groove to expose the bottom electrode metal on the uppermost layer;
(9) and (4) repeating the step (8) for the same repetition times as the step (3), wherein the etching depth of each time is deeper than that of the previous time, the groove position is closer to the edge of the upper electrode than that of the previous time, and all layers of bottom electrode metal are exposed in sequence.
Wherein, the column pore structure is square pore structure or circular pore structure. The hole-shaped upper electrode is a square hole or a round hole.
Furthermore, when the carbon layer, the phase change unit layer, the carbon layer, the gate tube layer, the carbon layer and the electrode layer are sequentially deposited by magnetron sputtering, in order to prevent the photoresist from being damaged by overhigh energy, the deposition needs to be carried out for a period of time and stopped for a period of time.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
(1) in the three-dimensional phase change memory structure provided by the invention, all the memory cells in the same vertical direction share the same bit line electrode, the word line electrode of each memory cell is in the horizontal direction, and the functional layer (the phase change unit and the gate tube unit) of each memory cell is the functional layer part of the shared bit line electrode opposite to the corresponding word line electrode, so that when the three-dimensional phase change memory is realized, only the number of layers of the word line electrode layer and the isolation layer needs to be increased, the functional layer (the phase change unit and the gate tube unit) only needs to be deposited once, and the process complexity of the three-dimensional phase change memory is reduced.
(2) The three-dimensional phase change memory structure provided by the invention can increase the number of the storage unit layers of the three-dimensional phase change memory only by increasing the number of the word line electrode layers and the isolation layers.
(3) According to the three-dimensional phase change memory structure provided by the invention, when the memory unit is operated, the current flows in the horizontal direction, so that more heat is distributed in the horizontal direction, and less heat is distributed in the vertical direction, therefore, the problem of thermal crosstalk between units can be reduced, the problem of thermal crosstalk between adjacent memory units can be effectively inhibited, and the data reliability of the three-dimensional phase change memory is improved.
Drawings
FIG. 1 is a structural diagram of a three-dimensional phase change memory based on vertical electrodes according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for fabricating a three-dimensional phase change memory based on vertical electrodes according to an embodiment of the present invention;
FIG. 3 is a graph illustrating resistance characteristics of a first layer of cells of a three-layer vertical electrode-based three-dimensional phase change memory according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating resistance characteristics of a second layer of cells of a three-layer vertical electrode-based three-dimensional phase change memory according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating resistance characteristics of a third layer of cells of a three-layer vertical electrode-based three-dimensional phase change memory according to an embodiment of the present invention;
fig. 6 is a structural diagram of a three-layer horizontally stacked structure-based 3D PCM provided in an embodiment of the present invention;
fig. 7 is a graph of a time variation of an unselected cell temperature Tpcm and a number of crystallized copies (θ PCM) adjacent to a selected memory cell in a three-layer horizontally stacked structure-based 3D PCM structure according to an embodiment of the present invention;
FIG. 8 is a simulation diagram of thermal crosstalk of a three-dimensional phase change memory based on vertical electrodes according to an embodiment of the present invention.
In the figure: 1 is a first silicon dioxide layer, 2 is a first word line electrode layer, 3 is a second silicon dioxide layer, 4 is a second word line electrode layer, 5 is a third silicon dioxide layer, 6 is a third word line electrode layer, 7 is a fourth silicon dioxide layer, 8 is a fifth silicon dioxide layer, 9 is a bit line electrode, 10 is a third carbon layer, 11 is a gate layer, 12 is a second carbon layer, 13 is a phase change unit layer, and 14 is a first carbon layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a structural diagram of a three-dimensional phase change memory based on vertical electrodes according to an embodiment of the present invention, in which a first silicon dioxide layer 1 is disposed at a lowermost layer, an assembly formed by sequentially and repeatedly growing a first word line electrode layer 2 and a second silicon dioxide layer 3 is disposed above the first silicon dioxide layer 1, how many memory cells of the three-dimensional phase change memory need to be repeatedly grown, a second through via is disposed in the assembly, the second through via is formed by filling multiple layers of materials in a sleeve shape, a first carbon layer 14, a phase change unit layer 13, a second carbon layer 12, a gate layer 11, a third carbon layer 10, and a bit line electrode 9 are sequentially disposed from outside to inside, the materials of the layers are tightly adhered together, inner walls of the first carbon layer 14 and the second through via are tightly connected together, a fifth silicon dioxide layer 8 is disposed above the assembly, and a first through via is disposed in the fifth silicon dioxide layer 8, the bit line electrode 9 extends through the first through via in the fifth silicon dioxide layer 8 to the structure surface.
The three-dimensional phase change memory based on the vertical electrode provided by the embodiment of the invention comprises a first silicon dioxide layer 1, a first word line electrode layer 2, a second silicon dioxide layer 3, a second word line electrode layer 4, a third silicon dioxide layer 5, a third word line electrode layer 6, a fourth silicon dioxide layer 7, a fifth silicon dioxide layer 8, a bit line electrode 9, a third carbon layer 10, a gate layer 11, a second carbon layer 12, a phase change unit layer 13 and a first carbon layer 14, wherein the first word line electrode layer 2 is arranged above the first silicon dioxide layer 1, the second silicon dioxide layer 3 is arranged above the first word line electrode layer 2, the second word line electrode layer 4 is arranged above the second silicon dioxide layer 3, the third silicon dioxide layer 5 is arranged above the second word line electrode layer 4, the third word line electrode layer 6 is arranged above the third silicon dioxide layer 5, and the fourth silicon dioxide layer 7 is arranged above the third word line electrode layer 6, a fifth silicon dioxide layer 8 is arranged above the fourth silicon dioxide layer 7, and a first through hole is formed in the fifth silicon dioxide layer 8; a second through hole is formed in a combination body formed by the first word line electrode layer 2, the second silicon dioxide layer 3, the second word line electrode layer 4, the third silicon dioxide layer 5, the third word line electrode layer 6 and the fourth silicon dioxide layer 7, the second through hole is filled with multiple layers of materials in a sleeve shape, a first carbon layer 14, a phase change unit layer 13, a second carbon layer 12, a gate tube layer 11, a third carbon layer 10 and a bit line electrode 9 are sequentially arranged from outside to inside, inner walls of the first carbon layer 14 and the second through hole are tightly connected together, and the bit line electrode 9 extends to the surface of the structure through the first through hole of the fifth silicon dioxide layer 8.
The first word line electrode layer 2 and the second silicon dioxide layer 3 may be periodically repeated in the vertical direction as required, and the number of times of repetition is the same as the number of memory cell layers required by the three-dimensional phase change memory.
In the prior art of the three-dimensional phase change memory, each memory cell is composed of a phase change cell and a gate tube cell which are connected in series, and each memory cell is positioned at the intersection of a word line and a bit line, therefore, when the memory cell is operated, current flows through the memory cell in the vertical direction, heat is mainly diffused in the vertical direction, and thermal crosstalk is generated on the memory cells adjacent to the vertical direction, the phase change memory provided by the invention is based on a vertical electrode structure, all the memory cells in the same vertical direction share the same bit line electrode, the word line electrode of each memory cell is in the horizontal direction, the functional layer (the phase change cell and the gate tube cell) of each memory cell is the functional layer part of the shared bit line electrode opposite to the corresponding word line electrode, current flows through the memory cell in the horizontal direction, and heat is mainly diffused in the horizontal direction, therefore, thermal crosstalk cannot be generated on adjacent memory units in the vertical direction, and the phase change memory provided by the invention only needs to deposit the functional layer (the phase change unit and the gate tube unit) once, so that the process is greatly simplified, and the manufacturing cost of the three-dimensional phase change memory is greatly increased.
Fig. 2 shows a method for manufacturing a three-dimensional phase change memory based on a vertical electrode according to an embodiment of the present invention, which includes the following steps:
(1) firstly, growing a bottom electrode metal material on a silicon substrate by utilizing magnetron sputtering;
(2) growing SiO on the bottom electrode metal material prepared in the step (1) by utilizing PECVD 2 ；
(3) Repeating the above two steps to alternately grow the bottom electrode and SiO 2 Until reaching the target layer number;
(4) performing ultraviolet lithography on the structure prepared in the step to form a columnar hole structure and etch a through hole, wherein the etching limit is to ensure that the electrode material at the bottommost layer is etched, slight over-etching can be generated, and then stripping the photoresist; wherein the cylindrical hole can be a square hole or a circular hole.
(5) Carrying out ultraviolet alignment on the hole-shaped electrode again and ensuring that the columnar hole structure prepared in the step (4) is located in the center of the square hole, and then developing without removing photoresist; the porous electrode can be a square hole electrode or a round hole electrode;
(6) and carrying out magnetron sputtering on the carbon layer, the phase change unit layer, the carbon layer, the gate layer, the carbon layer and the upper electrode layer in sequence, wherein a method of stopping 100s is adopted in order to prevent the photoresist from being damaged by overhigh energy during sputtering. Then stripping the photoresist spun in the step (5);
(7) carrying out ultraviolet photoetching and etching a groove in the area of the square hole electrode close to the columnar hole structure, so that the bottom electrode metal on the uppermost layer is exposed;
(8) and (4) repeating the step (7) for the same times as the step (3), wherein the etching depth of each time is deeper than that of the previous time, the position of the groove is closer to the edge of the upper electrode than that of the previous time, and all layers of bottom electrode metal are exposed in sequence.
In the prior art of the preparation process of the three-dimensional phase change memory, a porous structure is required to be etched and a functional layer (a phase change unit and a gate tube unit) is filled in the porous structure when each layer of storage unit is prepared.
In order to further explain the three-dimensional phase change memory based on the vertical electrode and the preparation method thereof provided by the embodiment of the invention, the following detailed description is further provided in combination with the preferred embodiment:
example 1:
the three-layer three-dimensional phase change memory based on the vertical electrode is prepared according to the following steps:
(1) growing metal W50 nm on a silicon substrate by magnetron sputtering;
(2) growing 100nm SiO on the tungsten electrode prepared in the step (1) by utilizing PECVD 2 ；
(3) Repeating the step (1) and the step (2) twice to obtain 6 layers of alternately grown metal W and SiO 2 ；
(4) Ultraviolet light is used for etching a cylindrical hole structure and a through hole, the metal tungsten at the bottom layer is etched through to generate slight over etching, and then the photoresist is stripped;
(5) carrying out ultraviolet alignment on the square hole electrode again and ensuring that the cylindrical hole structure prepared in the step (4) is located at the center of the square hole, and then developing without removing photoresist;
(6) magnetron sputtering 10nmC, 70nmGST225, 10nm C, 30nmGeTe in sequence 6 10nm C and 50nmW, and a method of stopping 100s during sputtering is adopted. Then stripping the photoresist spun in the step (5);
(7) carrying out ultraviolet photoetching and etching a groove in the area of the square hole electrode close to the columnar hole structure, so that the bottom electrode metal on the uppermost layer is exposed;
(8) and (4) repeating the step (7) for the same times as the step (3), wherein the etching depth of each time is deeper than that of the previous time, the position of the groove is closer to the edge of the upper electrode than that of the previous time, and all layers of bottom electrode metal are exposed in sequence.
Through the steps, the three-layer three-dimensional phase change memory based on the vertical electrode can be prepared, SET electric pulse and RESET electric pulse tests are respectively applied to the three layers of units, the resistance characteristic of the first layer of units is shown in figure 3, the resistance characteristic of the second layer of units is shown in figure 4, and the resistance characteristic of the third layer of units is shown in figure 5.
The three-dimensional phase change memory structure obtained by the preparation method only needs to deposit the phase change unit and the gating tube material once, so that the process complexity of the three-dimensional phase change memory is reduced. Meanwhile, the number of the storage unit layers of the three-dimensional phase change memory can be increased only by increasing the number of the word line electrode layers and the isolation layers. In addition, the problem of thermal crosstalk between adjacent storage units can be effectively suppressed, and the data reliability of the three-dimensional phase change memory is improved.
FIG. 6 shows a conventional 3D PCM proposed by Intel et al, which is based on a horizontally stacked structure in which heat generated from a selected cell is diffused toward unselected cells to generate thermal crosstalk when a SET operation is performed on the selected cell, and as shown in FIG. 7, the unselected cell temperature T adjacent to the selected memory cell pcm And fraction of crystals (. theta.) pcm ) With the change of time, it can be seen that, since the PCM can be in the crystalline state only by raising the temperature to 400K or more, the heat dissipated from the selected cell can raise the temperature of the third layer cell PCM to a certain amount (about 25%) of crystals in a partial region exceeding 400K, that is, the cell resistance is lowered, and the "0" state cannot be well maintained.
Fig. 8 is a simulation diagram of thermal crosstalk of a three-dimensional phase change memory based on vertical electrodes, in which for a selected region, the fraction of crystalline transition is 97.863% as calculated by probe integration, it can be considered that the selected region has completely undergone the transition from the amorphous state to the crystalline state, data "1" is written into a memory cell, and the phase change of unselected cells of the first layer and the third layer is not caused by the temperature change, that is, the PCM in the unselected region is still in the amorphous high-resistance state during the application of the SET pulse voltage. This is because the direction of the applied voltage current is horizontal under the vertical electrode structure, and thus the heat is diffused much more in the horizontal direction than in the vertical direction. In summary, for the vertical electrode stack structure, the selected cell can perfectly reproduce the SET operation crystallization transition process, and the thermal crosstalk has negligible effect on the unselected cells.
It will be understood by those skilled in the art that the foregoing is only an exemplary embodiment of the present invention, and is not intended to limit the invention to the particular forms disclosed, since various modifications, substitutions and improvements within the spirit and scope of the invention are possible and within the scope of the appended claims.

Claims (9)

1. A three-dimensional phase change memory based on vertical electrodes, the three-dimensional phase change memory comprising: the word line structure comprises a first silicon dioxide layer (1), a first word line electrode layer (2), a second silicon dioxide layer (3), a second word line electrode layer (4), a third silicon dioxide layer (5), a third word line electrode layer (6), a fourth silicon dioxide layer (7) and a fifth silicon dioxide layer (8) which are sequentially arranged from bottom to top, a first through hole vertically arranged at the center of the fifth silicon dioxide layer (8), a second through hole vertically arranged at the center of an assembly consisting of the first word line electrode layer (2), the second silicon dioxide layer (3), the second word line electrode layer (4), the third silicon dioxide layer (5), the third word line electrode layer (6) and the fourth silicon dioxide layer (7), and a bit line electrode (9); the bit line electrode (9) extends to the surface of the three-dimensional phase change memory structure through the first through via.
2. The three-dimensional phase-change memory of claim 1, wherein the second through via is filled with a plurality of layers of materials in a sleeve shape, and comprises a first carbon layer (14), a phase-change unit layer (13), a second carbon layer (12), a gate layer (11) and a third carbon layer (10) from outside to inside, and the first carbon layer (14) and the inner wall of the second through via are tightly connected together.
3. The three-dimensional phase change memory according to claim 1 or 2, wherein the first word line electrode layer (2) and the second silicon dioxide layer (3) are periodically repeated in a vertical direction as required, and the number of times of repetition is the same as the number of memory cell layers required by the three-dimensional phase change memory.
4. The three-dimensional phase change memory of claim 3, wherein all memory cells in a same vertical direction share a same bit line electrode.
5. The three-dimensional phase-change memory of claim 3 or 4, wherein the word line electrode of each memory cell is arranged in a horizontal direction, and the phase-change cell layer (13) and the gate layer (11) in each memory cell are functional layer parts with shared bit line electrodes opposite to the corresponding word line electrodes.
6. A method for preparing a three-dimensional phase change memory based on any one of claims 1-5, comprising the following steps:
(1) growing a bottom electrode metal material on a silicon substrate by utilizing magnetron sputtering;
(2) growing SiO on the bottom electrode metal prepared in the step (1) by utilizing PECVD 2 ；
(3) Alternately growing the bottom electrode metal material and the SiO by repeating the step (1) and the step (2) 2 Until the number of layers required by the target is grown;
(4) carrying out ultraviolet lithography on the wafer prepared in the step (3) to form a columnar hole structure, etching a through hole, and then stripping off the photoresist;
(5) carrying out ultraviolet alignment on the porous upper electrode on the columnar pore structure prepared in the step (4), developing the photoresist only, and not stripping the photoresist, wherein the columnar pore structure prepared in the step (4) is positioned in the center of the square pore upper electrode;
(6) sequentially depositing a carbon layer, a phase change unit layer, a carbon layer, a gate tube layer, a carbon layer and an upper electrode layer by magnetron sputtering;
(7) stripping the photoresist spun in the step (5);
(8) carrying out ultraviolet photoetching and etching a groove to expose the bottom electrode metal on the uppermost layer;
(9) and (4) repeating the step (8) for the same repetition times as the step (3), wherein the etching depth of each time is deeper than that of the previous time, the groove position is closer to the edge of the upper electrode than that of the previous time, and all layers of bottom electrode metal are exposed in sequence.
7. The method of claim 6, wherein the columnar pore structure is a square pore structure or a circular pore structure.
8. The method according to claim 6, wherein the porous upper electrode is a square hole or a circular hole.
9. The method according to any one of claims 6 to 8, wherein a period of time is required and stopped to prevent the photoresist from being damaged due to excessive energy when the carbon layer, the phase change unit layer, the carbon layer, the gate layer, the carbon layer and the electrode layer are sequentially deposited by magnetron sputtering.
CN202210585419.2A 2022-05-22 2022-05-22 Three-dimensional phase change memory based on vertical electrode and preparation method Pending CN114937738A (en)

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