CN1149374A - Multiplexer system using constant bit rate encoders - Google Patents
Multiplexer system using constant bit rate encoders Download PDFInfo
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Abstract
A multiplexer system includes a multiplexer having plural inputs and an output, plural channel processors each having a control input, a data input for receiving an input signal, a complexity output for providing a signal representing the complexity of an associated input data signal, and a data output for providing a constant bit rate data signal to an associated input of the multipler; and a bit rate allocator responsive to the complexity representing signals for providing bit rate control signals to the associated control inputs of the channel processors as a function of the complexity representing signals, such that a bit rate of an output data signal from a channel processor is a function of the complexity of an associated input data signal and to the combined of the input data signals.
Description
The present invention relates to a kind of being used for gives the position dynamic assignment multiplex system of having made Constant Bit Rate coded data passage accordingly in a multiplexed data flow.
Sometimes need be from the plurality of data source in data transmission system, or passage, transmit data from a position to the another location.In this case, be combined at headend station usually, promptly become single data flow by multipath conversion from the data of passage.This multiplexed data flow is sent to the station, rear end in the transmission line such as lead, optical fiber or radio link one class then, to separate from the passage of the data of multiplexed data stream at this, be that multichannel is decomposed, offer the recipient of expection then.
For example, can propagate into corresponding television receiver in the user family through a satellite circuit from some vision signals that may be each signal source of TV network feed, TV station or other video signal source.One satellite circuit as example comprises the Digital Transmission path of can per second transmitting 24 megabits (Mbps).For efficient and the purposes maximum that makes this circuit, the plurality of video signal demand is shared this circuit.For example, may wish at least six channel video signals, to share above-mentioned satellite link.
A kind of known method that is used to realize the transmission of this passage is to utilize variable bit rate (VBR) encoder to the corresponding video signal encoding from passage, then the resulting encoded video signal of multiplexing.One VBR encoder produces has the not successive frame of the digital coding video of isotopic number, and this depends on the complexity on the room and time of image of vision signal representative.More complicated sight and/or movable sight need more position that they are encoded than the simple sight of less activity on the space on the space.
Suppose, statistically say, will be from the average combined bit rate of all VBR encoders less than the maximum bit rate of transmission link, even can in a burst that supplies to transmit, provide a large amount of figure places at single channel encoder of any given time.Therefore, this device is called as statmux.Yet, there is a finite probability, promptly will be above the maximum bit rate of transmission link from the instantaneous combination bit rate of all passages, this causes losing of station, rear end data.In certain embodiments, add upper bumper for each passage or multiplexed data stream.But, still there is a kind of finite probability, promptly those buffers will overflow, and this causes losing of station, rear end data once more.
The known method that the another kind of attempting to solve some problem of VBR encoder is carried out multiplexed function is that each passage all uses Constant Bit Rate (CBR) encoder.In this system, will offer the CBR encoder from the vision signal of each passage.The CBR encoder produces the digitally coded bit stream that representative offers its vision signal with predetermined Constant Bit Rate.For producing the Constant Bit Rate signal, the CBR encoder is constantly changed the quantification progression that vision signal is encoded.Utilize less quantized level to need less position to represent these levels, and reduced the required total bit of expression vision signal.Otherwise, utilize more quantized level to need more position to represent these levels, and increased the required total bit of presentation video signal.
The right quantity of quantization level depends on the complexity of current frame of just encoding.The CBR encoder with the quantification progression that increases to having image encoding, to produce predetermined bit rate than low spatial and time complexity.On the contrary, for the figure place of being distributed to having the image encoding of higher spatial and/or time complexity, quantize progression and be reduced.
Yet the quantized level in the code signal of change representative image causes the respective change on the picture quality of being reproduced by code signal.Utilize less quantized level and for utilizing more quantized level, cause a low-qualityer reproduced image.Therefore, in a CBR encoder, represent on the space and/or on the time more the vision signal of complex image be encoded in such a way, promptly not too the quality of complex image is low for the mass ratio of reproduced image.
But,, therefore simplified from the multiplex control of the vision signal of some this encoders because the CBR encoder produces a Constant Bit Rate.Each encoder is by the bit rate that distributes to represent the quota of its total utilized transmission link bit rate in advance.A kind of known distribution method distributes the moiety of the total bit rate of transmission link to give each encoder.Yet, represent the vision signal of different program categories itself to have different complexity.For example, the video channel of transmission Basketball Match has higher complexity than the channel that transmits panel of expert discussion.Therefore, the quality of the image that reproduces from the encoded video signal of representing Basketball Match will be than the quality low (in fact may be lower) from the image of represent the encoded video signal reproduction that panel of expert discusses.
The another kind of distribution method of attempting to address this problem is to give each CBR encoder according to the different bit rate of desired image complexity distribution of signal to be encoded.Like this, the channel discussed than transmission panel of expert of the channel allocation that can give the transmission Basketball Match total bit rate of the transmission link of vast scale more.This distribution method may cause more approaching the equating of picture quality of reproducing from the code signal of representing basketball match and panel of expert that the two is discussed.
Also having a kind of known distribution method is to distribute the ratio of the total bit rate of transmission link to give channel according to signal supplier's payment.This supplier pays many more to transmission channel, the ratio of the total bit rate of transmission link of distributing to this channel is big more, and the better quality of the image that reproduces from the code signal by this channel.
Yet the inventor has realized that the complexity of vision signal can not always specify in advance.For example, news broadcast comprises and has the very sight of low-complexity, and (for example, a newsreader is sitting in after one and reads news) intercuts has the very sight of high complexity (for example Basketball Match video is sheared).If this video channel has distributed the total bit rate of a high proportion of transmission link in advance, then the Basketball Match sight may reproduce with acceptable quality, but can the ether high quality of newsreader's sight or is in other words used than needed more position to be encoded.On the other hand, if distributed the total bit rate of transmission link of low ratio for this video channel, then newsreader's sight may utilize rational figure place to reproduce with acceptable quality, but the bit rate that is distributed may be not enough to reproduce the Basketball Match sight with acceptable quality.
The inventor recognizes that also on average, each video source can use the mode identical with above-mentioned news broadcast to characterize, and promptly almost each vision signal with commercial value all comprises the sight of the high complexity that intercuts the low-complexity sight.They recognize that also the sight of different complexity is incoherent in time.And they find that also in any given frame period, the image of different channel has different complexity, and these complexity variations also are incoherent in time.
It is found that best present image complexity according to these passages gives different passages with the bit rate dynamic assignment.The current complexity that just is being transmitted image of all passages is given each passage corresponding to the present image complexity of this passage and the relation of all channel image total complexities with the pro rate of the total bit rate of transmission link in some way by valuation.
The purpose of this invention is to provide a kind of multiplex system, it comprises: a plurality of data signal sources and the multiplexer with a plurality of inputs and an output.In a plurality of channel processors each comprises: the data input pin that is coupled to a corresponding data signal source; Produce the complexity output of the signal of data-signal complexity on the representative data input; The control input end; And data output end that is coupled to a respective input of multiplexer.Signal on this data output end response control input end produces an encoded signals with the Constant Bit Rate group.Bit rate distributor has many to relevant input and output sides, each to channel processor in corresponding one be associated.The input of every centering is coupled to the complexity output of related channel program processor.The output of every centering is coupled to the control input end of related channel program processor and produces bit rate quota signal, so that the combinatorial complexity of signal representative is relevant on the input of the complexity of signal representative on the input of the bit rate of signal on the related channel program processor data output and this centering and all these centerings.
The multiplex system branch ligancy of working is in this way given various passages, makes that the quality of the reproduced image of interior all passages of cycle is approximately identical at any time.It further optimizes the quality of whole reproduced image.The passage of transmission high complexity image will dynamically be distributed a higher bit rate in this time cycle in a time cycle, but when the complexity of this image becomes low, the bit rate of distributing to this passage will reduce, and be assigned to the channel of other transmission higher complexity image.
Fig. 1 is the block diagram according to multiplex system of the present invention;
Fig. 2 is the block diagram that can be used in the channel processor in the multiplex system shown in Figure 1;
Fig. 3 is the block diagram that can be used in the mpeg encoder part in the channel processor shown in Figure 2;
Fig. 4 is the block diagram that can be used in the bit rate distributor in the multiplex system shown in Figure 1;
Fig. 5 is the more detailed block diagram that can be used in the complexity analyzing device in the channel processor shown in Figure 2; And
Fig. 6,7 and 8 is expression sequential charts to the sampling of complexity information.
Fig. 1 is the block diagram in conjunction with multiplex system of the present invention.In Fig. 1, all signal paths all are expressed as single-signal-line.But, those skilled in the art will be appreciated that represented signal path can transmit multistation digital signal, or parallel convey, signal path can be made up of a plurality of holding wires in this case, or serial transfer, signal path can be the forms data line and/or comprise data and clock cable in this case.From this figure, deleted for simplicity and understood other control and clock signal path that the present invention has nothing to do.
In Fig. 1, a plurality of inputs 5 are coupled to the source (not shown) of the vision signal (passage 1-passage K) that will transmit together on a data link.These a plurality of inputs 5 are connected to the corresponding data input of corresponding a plurality of channel processors 10.Each data output end of a plurality of channel processors 10 is connected to multiplexer (MUX) 20 corresponding data input 1-K.The data output end of multiplexer 20 is connected to the output 15 of multiplex system.Output 15 is connected to the application circuit (not shown) that is used for transmitting multiplexed data flow (multiplexed data) on transmission link.
In a plurality of channel processors 10 each also comprises a complexity output and a control input end.The corresponding complexity output of each is connected to the corresponding complexity input of bit rate distributor 30 in a plurality of channel processors, and the corresponding quota output of bit rate distributor 30 is connected to the corresponding control input end of a plurality of channel processors 10.
During work, each channel processor receives the signal of representing next quota period allocated to give its bit rate in its control input end.This channel processor will be encoded to digitally encoded signal with the bit rate that distributes at the signal in next quota cycle of its data input pin then.Encoded data signals offers the corresponding input of multiplexer 20.Multiplexer 20 is operated in known manner, will being multiplexed data flow from the signal combination of all channel processors.Still in a known way multiplexed data flow is offered the circuit that comprises the data link that is used to transmit then.
In cataloged procedure, channel processor 10 produces the be encoded signal of codec complexity of signal of expression at its complexity output.Bit rate distributor 30 receives the signal from the complexity output of channel processor 10, and dynamically regulates the bit rate quota in next quota cycle in a plurality of channel processors 10 according to all complexity signals.In a preferred embodiment, complicated signal is distributed higher bit rate relatively than not too complicated signal dynamics.The distinct methods of determining the vision signal complexity and distributing bit rate according to this complexity is described below.
Fig. 2 is the block diagram that can be used on the channel processor in the multiplex system shown in Figure 1.In Fig. 2, represent with identical label with the similar parts of parts among Fig. 1, and be not explained in detail hereinafter.Data input pin 5 is connected to the video signal source (not shown) in Fig. 2.Data input pin 5 is connected to the data input pin and the complexity analyzing device 16 of constant bit rate encoders (CBR) 14.The data output end of CBR encoder 14 is connected to the input of multiplexer (MUX) 20 (Fig. 1).The control input end of channel processor 10 (" control ") is connected to the quota input Q of CBR encoder 10.The output of complexity analyzing device 16 is connected to the complexity output (" complexity ") of channel processor 10.
During work, complexity analyzing device 16 is analyzed the complexity of the vision signal of data input pin 5.Output at complexity analyzing device 16 produces the signal of representing the input signal complexity.This complexity representative signal is provided to bit rate distributor 30 (Fig. 1).Respond this complexity signal (and those signals of other channel processor 10), bit rate distributor 30 provides the signal of representing the bit rate of distributing to this channel processor 10 to this channel processor 10 control input end (" control ") of (with other channel processor 10).CBR encoder 14 provides data path at its data input pin and generation between the data output end with the output signal of Constant Bit Rate coding.Set Constant Bit Rate according to the signal that is input to quota input Q from bit rate distributor 30 from the control input end (" control ") of channel processor 10.
Might complexity analyzing device 16 at the circuit that carries out also using when it is analyzed in the CBR encoder 14.In this case, as shown in phantom in Figure 2, data directly offer complexity analyzing device 16 in CBR encoder 14.This data of CBR encoder 14 can be replenished the data from input 5, or substitute it fully, and the complexity analyzing device directly is not connected with data input pin 5 in this case.
In a preferred embodiment, each CBR encoder 14 is the standard announced according to Motion Picture Experts Group (MPEG) encoders to video signal compression and coding, is referred to as mpeg encoder.Fig. 3 is the block diagram of the part of expression one mpeg encoder 14.Below the known tip assemblies of mpeg encoder 14 will be described in detail.Mpeg encoder is comprised with understand other parts that the present invention has nothing to do, left out them for simplicity in the figure.
In Fig. 3, the data input pin 5 of mpeg encoder 14 (" data input ") is connected to video signal source (not shown) to be compressed and coding.Input 5 is connected to the input of frame buffer 41.Frame buffer 41 comprises a plurality of frame period buffers or delay line and a plurality of output, and this output produces each signal of the part of different but temporarily adjacent frame of expression or image.A plurality of outputs of frame buffer 41 are connected to the corresponding input of motion estimator 42.The output of motion estimator is connected to discrete cosine transform (DCT) circuit 43.The output of DCT circuit 43 is connected to the data input pin of variable quantization device (Qu) circuit 46.The output of variable quantization device circuit 46 is connected to the input of variable length coder (VLC) 47.The output of VLC47 is connected to the input of output buffer 48.The data output end of output buffer 48 is connected to the data output end (" data output ") of mpeg encoder 14.The data output end of mpeg encoder 14 (" data output ") is connected to the corresponding input of multiplexer 20 (Fig. 1).
The state output end of output buffer 48 is connected to the state input of bit rate adjuster 49.The control output end of bit rate adjuster 49 is connected to the control input end of variable quantization device 46.The quota input Q of mpeg encoder 14 is connected to the corresponding quota output of bit rate distributor 30.The quota input Q of mpeg encoder 14 is connected to the control input end of adjuster 49.
In when work, mpeg encoder 14 operate in a known way, so as to its input next by norm the vision signal in cycle compress with the determined bit rate of the signal of its Q input and encode.In following example, the mpeg encoder to the encoding video signal that is divided into the group of being made up of 12 images or frame (GOP) is described.Yet should understand the image among the GOP or the quantity of frame may change.In addition, in following example, suppose that the bit rate of each mpeg encoder is assigned as every GOP renewal once, promptly the quota cycle is the GOP cycle.But, will also be understood that quota also may be different in the cycle, itself in addition can change in time.
In DCT circuit 43, according to the mpeg standard document, take advantage of 16 row macro blocks and be divided into piece (four luminance block that six 8 pixels are taken advantage of 8 row from 16 pixels of the spatial data of I frame from the differences in motion value signal of P frame and B frame, and the chrominance block of two double samplings), be called macro block at the remainder of this application.Each macro block is carried out discrete cosine transform.Resulting 8 take advantage of 8 DCT coefficients to offer variable quantization device 46 subsequently.8 take advantage of 8 coefficients be quantized, with zigzag order scanning and be provided to VLC47.DCT coefficient after the quantification utilizes the run-length encoding method to encode in VLC47 with other supplementary of representing GOP (with the relating to parameters of coding GOP), and is provided to output buffer 48.
Known control VLC47 output bit rate and to keep the institute of mpeg encoder 14 to distribute the direct mode of Constant Bit Rate thus be to control the quantification progression that is used to quantize each DCT coefficient block in the variable quantization device 46 (or in other words, quantization step).The control signal that offers variable quantization device 46 from bit rate adjuster 49 is carried out this controlled function.At one is that quota from the cycle between the continuous bit rate quota update signal of bit rate distributor 30 (Fig. 1) is in the cycle, bit rate adjuster 49 offers control signal variable quantization device 46 in known manner, it will change among the GOP per 16 and take advantage of 16 macro blocks to be carried out the quantification progression of quantification, so as to keep this quota cycle distribute bit rate.In following described mode, according to the codec complexity value of the vision signal of every passage in a plurality of passages, the bit rate of bit rate adjuster 49 is distributed in each GOP cycle and changes in this example.
In a preferred embodiment, bit rate distributor 30 (Fig. 1) is to have the computer system that is connected to the connector of various circuit blocks in a plurality of channel processors 10.Fig. 4 is the hardware block diagram that constitutes bit rate distributor 30.In Fig. 4, microprocessor (μ P) 31 is connected to read/writable memory device (RAM) 32 by computer system bus 35, read-only memory (ROM) 33 and I/O (I/O) controller 34.Also have other computer system part,, do not illustrate in the drawings in order to simplify such as mass storage device and user terminal.I/O controller 34 has a plurality of a plurality of outputs (" by norm ") that are connected to the input (" complexity ") of the corresponding complexity output of a plurality of channel processors 10 (Fig. 1) and are connected to the corresponding quota input of a plurality of channel processors 10.
For each image of GOP or all macro blocks in the frame, be used for determining that the best approach of the codec complexity of the vision signal of encoding with mpeg encoder 14 (Fig. 3) is to utilize per 16 to take advantage of the quantitative calibration factor of 16 macro blocks (to be marked as Q
MB) and the figure place of this macro block that is used to encode (be marked as T
MB).Fig. 5 is the bit rate adjuster 49 of mpeg encoder 14 (Fig. 3) and produces the block diagram of representing the complexity analyzing device 16 (Fig. 2) of signal according to the codec complexity of this method.For simplifying this figure, various clocks and control signal have been deleted among Fig. 5.Yet those signals that need and their required sequential and voltage characteristic are intelligible.
Complexity analyzing device 16 shown in Figure 5 is examples that only are used to as shown in phantom in Figure 2 from the complexity analyzing device of the information of CBR encoder 14.In Fig. 5, bit rate adjuster 49 has the state input T of the state output end that is connected to output buffer 48 (Fig. 3)
MBThe control output end Q of bit rate adjuster 49
MBBe connected to the control input end of variable quantization device 46 (Fig. 3).Bit rate adjuster 49 also has the control input end (Q) of the corresponding quota output that is connected to bit rate distributor 30 (Fig. 1).
The state input T of bit rate adjuster 49
MBBe also connected to the first input end of first adder 92.The output of first adder 92 is connected to the input of first latch 93.The output of first latch 93 is connected to the first input end of multiplier 94 and second input of first adder 92.The output of multiplier 94 is connected to the input of second latch 95.The output of second latch 95 is connected to codec complexity output X
PICCodec complexity output X
PICBe connected to the corresponding complexity input of bit rate distributor 30 (Fig. 1).
The control output end Q of bit rate adjuster 49
MBAlso be coupled to the first input end of second adder 96.The output of second adder 96 is coupled to the input of the 3rd latch 97.The output of the 3rd latch 97 is coupled to the molecule input N of divider 98 and second input of second adder 96.The output of divider 98 is coupled to second input of multiplier 94.Register 99 has the output that is coupled to divider 98 denominator input D.
During work, for each macro block, bit rate adjuster 49 produces the quantitative calibration factor signal Q of variable quantization device 46 in known manner according to present bit rate quota and the figure place that is used for previous image encoding
MB, receive expression from output buffer 48 then and be used for figure place T this macroblock coding
MBSignal.Variable quantization device 46 (Fig. 3) is according to the quantitative calibration factor Q
MBQuantize the DCT coefficient in each macro block.The quantitative calibration factor Q
MBRepresent quantization step, or the percentage of the whole dynamic range of DCT coefficient in each quantized level.The Q of big value
MBThere is bigger quantization step in expression, and therefore, quantized level is less.Otherwise, the Q of little value
MBThere is less quantization step in expression, and therefore, quantized level is more.In a preferred embodiment, Q
MBIt is one five integer (having the numerical value between 1 to 31).
The average quantization scale factor of all macro blocks (is marked as Q in a complete image or frame
PIC) be calculated as follows.In the beginning of each frame or image, responding a reset signal (not shown) is clearly zero with latch 93 and 97.The combination of second adder 96 and the 3rd latch 97 as an accumulator job so that continuously will be from the macro block quantitative calibration factor Q of bit rate adjuster 49
MBSummation.Simultaneously, the combination of the first adder 92 and first latch 93 as accumulator work with continuously to so far being used for figure place summation to image or frame coding.
All macro blocks in handling frame or image (are indicated as N
MBQuantity) after, latch 97 comprises all macro block quantitative calibration factor Q that bit rate adjuster 49 produces
MBSum, latch 93 comprise all T that are used for image or frame coding
PICSum.Divider 98 produces all macro block quantitative calibration factor Q in image or the frame
MBSum is by macroblock number N in image or the frame
MBThe merchant who removes.This merchant is the average quantization scale factor Q in this frame or the image
PICMultiplier 94 produces Q
PICAnd T
PICLong-pending, it (is indicated as X for the codec complexity of this image
PIC), i.e. X
PIC=T
PIC* Q
PICWhen image or frame end, the response clock signal (not shown) is with codec complexity signal X
PICBe latched in second latch 95.Repeat above-mentioned circulation for each image in the vision signal of just encoding or frame then.
Then with codec complexity X
PICBe provided to the complexity input of the I/O controller 34 of bit rate distributor 30 (Fig. 4) from latch 95, remain processing, to obtain the codec complexity of GOP.The codec complexity of GOP (is indicated as X
GOP) be the X of all images among this GOP
PICAnd.(square journey (1)).
μ P31 is as retrieving each X from I/O controller 34
PICValue and in GOP on all frames or the image to the accumulator of their summations.
The total maintenance of the quantity of frame or image (being indicated as N) is constant among the GOP.When N is constant, can on the basis of mobile window, calculate X
GOP, add the codec complexity value X of last image
PIC, and deduct among the GOP codec complexity of image the earliest.In this case, the X that after each frame or image, can obtain upgrading
GOPValue.But N can change.If N changes, then the X of the GOP of corresponding redetermination
GOPMust pass through codec complexity value X from the new quantity of former image among the redetermination GOP
PICThe summation and calculated, as equation (1).
As mentioned above, different passages are possible with different frames or image rate operation, and for example, standard video frame rates (in the U.S.) is per second 29.97 frames, and it is per second 24 frames for film image, and it is per second 15 frames for cartoon.Also having a kind of may be image or the frame that different passages have varying number among the GOP.Therefore, might have the different GOP time cycles by different passages.In order under this condition, accurately to divide coordination to give passage, by every passage (is marked as GOP from the GOP complexity value of equation (1) divided by GOP time cycle of this passage
Time), in this case the GOP codec complexity value of a plurality of passages in bit rate distributor 30 by time normalization.(square journey (2)).
Normalized then GOP codec complexity value (is marked as Xnorm
GOP) be used in different passages, dividing coordination (bit) to count.To discuss the sampling sequential and the generation of value by norm of the complexity value of this system below in more detail.
Return referring to Fig. 5, as mentioned above, for each macro block, bit rate adjuster 49 produces the quantitative calibration factor signal Q of variable quantization device 46
MB, receive expression from output buffer 48 then and be used for figure place T this macroblock coding
MBSignal.These signals also can directly offer the I/O controller 34 in the bit rate distributor 30 (Fig. 4).The codec complexity value that but μ P31 internal calculation is suitable then (from equation (1) or equation (1) and (2)).
And, in order to simplify transmission, can carry out no-load voltage ratio to the codec complexity value of each image Xpic and calculate.In a preferred embodiment, this value is become eight-digit number behind multiplier 94.Then the value after this no-load voltage ratio is sent to bit rate distributor 30 (Fig. 4).Owing to other reason,, might wish that also this computer system is kept at the image complexity value Xpic of a file for example in the mass storage (not shown) such as allowing under the situation that N changes calculation code complexity value again.8 Xpic values of storing one hour will take 108 kilobytes (kB) for normal video, take 86kB for film.
In the following discussion, X
iRepresent current obtainable X from the i channel processor
GOP(if all passages have the same GOP time cycle) or Xnorm
GOPIn suitable one.Bit rate distributor 30 (Fig. 1) is according to the codec complexity value X that comes all K channel processor of a plurality of channel processors 10 of self-forming
iProduce corresponding quota (Q) signal of the distribution that can put in place in the transmission link of representing next quota cycle.Scheduled transmission link bit rate (being marked as R) from multiplexer 20 (Fig. 1) output distributes in a plurality of channel processors 10, and therefore i channel processor receives and be indicated as R
iBit rate distribute.
Be used for distributing the bit rate of transmission link to be for a kind of method of different passages, according to the current obtainable codec complexity X in previous GOP cycle of all channel processors 10 (Fig. 1)
i(on mobile window basis, linear distribution as mentioned above).In the method, each processor i receives the same ratio R of total bit rate capacity R
iAs this encoder X
iCodec complexity to provide total coding complexity of all encoders.(square journey (3)).Yet, have been found that to exist the lower limit bit rate to distribute, distribute the quality of following reproduced image to descend suddenly at this bit rate.In addition, in the embodiment shown, the bit rate in next quota cycle distributes the complexity that depends on from previous GOP to measure.Like this, if the scene change of existence from the simple image to the complicated image, because the distribution of new sight is based on previous, simple sight, it may be not enough that branch is used in the position that new, complicated sight is encoded.
Be used for distributing the bit rate of transmission link to guarantee the minimum bit rate of each encoder i is distributed RG for the other method of different passages
i, and distribute remaining bit linearly as equation (3).(square journey (4)).Depend on the expection total complexity of the video by channel transfer and/or the passage price that the vision signal supplier is proposed, every passage can have the minimum bit rate of different assurances.
Also have and a kind ofly be used for distributing the position of transmission link to provide weighted factor P for every encoder i for the method for different passages
i, and according to codec complexity value X
iUse weighted factor P
iValue after the weighting is done the position pari passu and is distributed.(square journey (5)).As the assurance smallest allocation method of equation (4), weighted factor P
iMay depend on the expection total complexity of the vision signal by channel transfer and/or the passage price that the vision signal supplier is proposed.
The method for optimizing that divides coordination to give different passages in transmission link is the combining of smallest allocation method of weight assignment method and the assurance of equation (4) of equation (5).In this method, guarantee smallest allocation, and on the basis of weighting ratio, distribute remaining position every passage.(square journey (6)).As mentioned above, the smallest allocation of assurance and weighted factor may depend on the expection total complexity of the vision signal by channel transfer and/or the passage price that the vision signal supplier is proposed.
Might distribute R according to the further selected position of other parameter of system
iFor example, found to exist a upper limit bit rate apportioning cost, can't see the improvement of reproduced picture quality more than the value at this.Therefore, to distribute be waste to the transmission link meta in the position that surpasses this upper limit apportioning cost.In addition, the operator of transmission link can implement maximum bit rate distribution R to every passage
Max(it can react above-mentioned upper limit bit rate apportioning cost) and/or minimum bit rate distribute R
Min
In addition, for make bit rate control fluctuation may be minimum and make the stability of bit rate control maximum, the bit rate from a quota cycle to next quota cycle of passage distributes, can apply and increase α and or reduce the maximal increment of β.As mentioned above, the maximal increment that the numerical value of upper limit bit rate apportioning cost, minimum and maximum bit rate distribute and increase and reduce, can be different for different passages, and can be depending on the expection total complexity of the vision signal by this channel transfer and/or vision signal supplier's passage price.In addition, increase and the minimum and maximum increment that reduces might dynamically change according to the empty or full degree of buffer in the passage.
And bit rate that also can further selected distribution is so that provide buffer management, for example guarantees that the input buffer of the output buffer of CBR encoder 10 (Fig. 1) and corresponding receiver decoder (not shown) can overflow or underflow.If control coded buffer size E does not then need tangible buffer management as shown in inequality (7), wherein D is the decoding buffer sizes of fixing.If select the coded buffer size according to inequality (7), bit rate distributes can be from R
MinChange to R
MaxAnd the overflow or the underflow of the buffer that can not cause encoding or decode.But this method has too limited the size of coded buffer, has therefore too limited the flexibility of rate controlled.
A kind of buffer management scheme of replacement is current, the instantaneous bit rate that is suitable for and utilize buffer management, rather than preset parameter R
MinAnd R
MaxBecause selecting the decoding buffer sizes can handle with maximum rate R
MaxThe data of transmission, the bit rate distribution always can increase (to the maximum R of system
Max), and the decoding buffer is overflowed.Yet, have the instantaneous minimum bit rate that must keep, to guarantee that the data in coded buffer were transferred to the decoding buffer before its decode time.Therefore, must dynamic calculation guarantee to decode buffer not the minimum bit rate of underflow distribute.
In dynamic calculation should the minimum bit rate be distributed, divide timing when reducing bit rate, must consider that new definite coded buffer is big or small and in some aforementioned time quantum, be placed on data volume in the coded buffer.Be appointed as E
nThe new coded buffer size of determining of n frame determine that according to equation (8) wherein Δ is the system delay time, be that frame of video is when arriving encoder and the constant time delay of this frame between when being presented on the decoder; D is the decoding buffer sizes of fixing; And R
NewBe that the new bit rate that proposes distributes.This buffer sizes is guaranteed will not have overflow or underflow in the Code And Decode buffer under the stable state that new bit rate distributes.
But, as mentioned above,, then there is the change-over period that equals system delay time Δ if the bit rate of proposition distribution newly reduces, wherein may have too many position and in coded buffer, consequently can not successfully arrive decoder than lower rate transmissions with new.Be used for a kind of suggesting method that the bit rate of selected new proposition distributes and be at first the volume check of the system delay time Δ previous frame that is indicated as Г is indicated as the actual figure place of putting into coded buffer (buffer is saturated) of e.The saturated number of largest buffer with former Г frame (is indicated as e then
Max, Г) with the new coded buffer size E that determines that obtains by equation (8)
nCompare.Guarantee that then the bit rate that reduces of minimum that successfully is transferred to the passage i of receiver decoder from all of former Г frame distributes R
ReduceProvide by equation (9).
If this restriction puts on multiplexer system, then after having calculated bit rate according to equation (3), (4), (5) or (6) and distributing, check that these bit rate branches are equipped with and determine whether they drop in the current upper and lower bound of this passage.At first, the upper and lower bound of every passage i is determined.Any quota cycle k (is expressed as R
iThe upper limit [k]) upper limit bit rate distribution is following middle minimum: the maximum on the quota cycle k-1 allowed to increase distribution in the past; Distribute the limit with maximum bit rate.(square journey (10)).
The lower limit bit rate of any quota cycle k distributes R
i Lower limit[k] is following middle maximum: minimum bit rate distributes the limit; Minimum on the quota cycle k-1 allowed the distribution that reduces and reduced bit rate by the minimum that equation (9) obtains and distribute in the past.(square journey (11)).Carry out the adjustment that the passage bit rate distributes then.
If any passage distribute bit rate to surpass arbitrary limit value, then the bit rate of this passage distributes and is set to this limit value, and redistributes available residue bit rate in other passage.For example, if as calculating with equation (3), (4), (5) or (6), distribute to the upper limit of the bit rate of a passage i greater than this passage, calculate as equation (10), then the bit rate of passage i is set at this upper limit R
i The upper limitIf instead the lower limit that bit rate is calculated less than equation (11) then is set at bit rate this lower limit R
i Lower limit(square journey (12)).
If any bit rate of the qualification operation change of equation (10), (11) and (12) distributes, then in the passage that does not limit, redistribute remaining utilized bit rate according to equation (3), (4), (5) or (6).The limit in relative then equation (10), (11) and (12) is checked these passages once more.Repeating this circulation distributes up to finishing all bit rates.In the above-described embodiments, the codec complexity cycle is to move on the window basis GOP cycle that image is one by one determined one, and it is that the variation from a quota cycle to next quota cycle generally speaking should less enough time intervals during bit rate in the passage distributed.Therefore, equation (10), (11) and (12) should seldom be quoted.
If passage just operate with the different GOP time cycles, the sequential of codec complexity sampling and be complicated based on the generation of the updated space rate quota of codec complexity, exists two kinds of generation precision encoding complexity sample and this situation under the methods of bit rate quota allocation.In first method, calculate the constant quota cycle by this way, promptly each passage has the quota cycle of equal amount in every GOP.In the method, sampling number and quota cycle can change from channel-to-channel among every GOP, and still, for any passage, this sampling and the quantity in quota cycle are constant in the GOP.In the second approach, get a sample, whenever any passage begins to produce new the distribution once new GOP, and consideration is from the length computation of the time cycle of the current sampling of sampling the in the past figure place with new quota allocation.
Fig. 7 is that expression utilizes the sequential chart that first method is sampled and quota upgrades in system.In order to simplify this figure, only show two passages.In Fig. 7, passage 1 is the example of a passage of the normal video of the frame rate (in the U.S.) of transmission with per second 30 frames.Passage 2 is examples of a passage of the film of the frame rate of transmission with per second 24 frames.Suppose that each GOP of each passage has 12 frames.Passage 1 per 0.4 second beginning one new GOP like this, or 2.5 GOP of per second, and passage 2 began a new GOP or 2 GOP of per second in per 0.5 second.Selected sampling rate is per 0.1 second sample.Therefore, in passage 1, in each GOP, exist four samples and quota to upgrade, in passage 2, in each GOP, exist five samples and quota to upgrade.Represent sample time ts with vertical dotted line.Because the time cycle Δ t between the sample is constant (0.1 second), above-mentioned equation (3) divides timing to be used to equation (12) at the bit rate that calculates next sampling period with not doing any change.These bit rates distribute and can add up and be used in the channel processor 10 (Fig. 1) according to the known arrangement that is referred to as " mark and funnel (token and leaky bucket) ".
Fig. 8 is the sequential chart that expression utilizes codec complexity sample value in the system of above-mentioned second method and quota to upgrade.Each passage shown in Fig. 8 is propagated identical signal with Fig. 7.In Fig. 8, when no matter when arbitrary passage begins a new GOP, obtain sample from the codec complexity value of all passages.Produce new the distribution according to these sample values with from the time cycle Δ t that last sample begins.These sampling times are expressed as vertical dotted line t1-t8 in Fig. 8, t2 wherein, and t3, t4, t6 and t8 are corresponding to the beginning of GOP in the passage 1, and t1, t3, t5 and t7 are corresponding to the beginning of GOP in the passage 2.Though t3 represents the sampling time corresponding to the beginning of GOP in passage 1 and the passage 2, the requirement that does not exist this to occur constantly.
At each sampling time, to the present encoding complexity value in all passages (from former GOP, can be on mobile window basis one by one image ground obtain) sample.Equation (3) to equation (12) can be used for calculating next bit rate quota ratio, but when the actual number of bits of determining to can be used for distributing, the time quantum Δ t that begins from last sample must take in.In order suitably to compensate different sample cycles, obtainable bit rate R total in equation (3) to (12) substitutes with the figure place (being appointed as C) that can be used for distributing, and it is the product that always can obtain bit rate R and the Δ t of sample cycle, i.e. C=R Δ t.Then equation (3) is distributed to each channel processor 10 (Fig. 1) to the figure place that equation (12) calculates, it utilizes " mark and funnel " scheme to add up as mentioned above and uses the position of being distributed.When the vision signal from different passages 5 has different GOP during the time cycle, any in above-mentioned two kinds of methods will accurately distribute bit rate to give each channel processor 10.
If all passages are with identical frame rate work, and have identical frame number in a GOP, promptly all passages have identical GOP time cycle GOP
TimeThen can simplify the sampling sequential of codec complexity value and the generation of different passage updated space rate quotas.Fig. 6 is a codec complexity sample and the sequential chart that upgrades sequential by norm in this system of expression.In Fig. 6, each horizontal line is corresponding to respective channel 1-K.Begin the moment of the coding of I frame from the upwardly extending short vertical line representative of horizontal line from this passage, it is considered to the beginning of the GOP of this passage.The time cycle GOP of GOP
TimeIn all passages, equate, but as can be seen, the time started of the GOP of each passage is different.In fact, have found that the GOP of each passage preferably has different zero-times, the coding of I frame can be not overlapping like this.This complexity that has increased through different passages changes.
Found that these frames are inessential from different GOP as long as consider I frame, P frame and the B frame of similar number when calculation code complexity value.Therefore, as with shown in the solid line that extends through all channel time axles, can side by side obtain the sample of codec complexity value any time in GOP from all passages.Can produce renewal and transmission backward channel processor 10 (Fig. 1) of the bit rate quota of all passages then from this sample.
According to the above-mentioned multiplex system of having put system description in the lump.But.A plurality of channel processors 10 can be placed on the position far away of off normal rate distributor 30 and multiplexer 20.In a kind of like this system, between encoder and bit rate distributor, set up communication link.In this case, some bit position that transmits between processor 10 and multiplexer can be exclusively used in the complexity transmission of Information of processor.
Claims (22)
1, a kind of data multiplexing system comprises:
Multiplexer (20) with a plurality of inputs and an output;
A plurality of channel processors (1), each comprises: a control input end, an input that is used for receiving input data signal, an output that is used to provide the signal of the complexity of representing the input data signal of being correlated with is used to provide the output of Constant Bit Rate data-signal to the relevant input of described multiplexer with one; And
The bit rate distributor (3) of a described complexity representative signal of response, be used for the bit rate control signal is offered the relevant control input end of described channel processor as the function of described complexity representative signal so that from the bit rate of the data-signal of channel processor output be relevant input data signal complexity function and corresponding to the combinatorial complexity of described input data signal.
2, a kind of multiplex system comprises:
A plurality of data signal sources (5);
A multiplexer (20) has a plurality of inputs (1-K) and an output (15);
A plurality of channel processors (10), each comprises: be coupled to corresponding one in the data signal source (a 5) data input; Produce a complexity output of the signal of data-signal complexity on the representative data input, a control input end, and corresponding one data output end in input (1-K) that is coupled to multiplexer (20), the signal on this data output end response control input end produces an encoded signals with the Constant Bit Rate group;
A bit rate distributor (30), have many to relevant input and output side, each to channel processor in corresponding one be associated, the input of every centering is coupled to the complexity output of related channel program processor, be coupled to the control input end of related channel program processor with the output of every centering and produce bit rate quota signal, thus on the bit rate of signal on related channel program processor (10) data output end and relevant input on the input of the complexity of signal representative and all these centerings the combinatorial complexity of signal representative relevant.
3, multiplex system as claimed in claim 2, wherein: bit rate distributor (30) produces corresponding positions rate quota signal on the output of every pair of relevant input and output side, will receive quota signal than the higher relatively bit rate of the channel processor with relatively low complexity signal (10) so that have the channel processor (10) of the signal of a relative higher complexity at its data input pin.
4, multiplex system as claimed in claim 3, wherein:
Multiplexer (20) produces the signal with predetermined Constant Bit Rate at its output (15); And
Produce corresponding bit rate quota signal on the output of bit rate distributor (30) in every pair of relevant input and output side, so that each channel processor (10) is assigned with the predetermined constant bit rate of a certain ratio, its equal by the complexity of the signal representative on the relevant input of every centering with by the combinatorial complexity of the signal representative on the input all these centerings ratio.
5, multiplex system as claimed in claim 3, wherein:
Multiplexer (20) produces the signal with a predetermined constant bit rate at its output;
Each channel processor (10) is assigned a corresponding predetermined minimum bit rate; And
Produce corresponding bit rate quota signal on the output of bit rate distributor (30) in every pair of relevant input and output side, so that each channel processor (10) is assigned with the predetermined minimum bit rate of appointment, and further be assigned the residue bit rate ratio, this residue bit rate equals the predetermined constant bit rate less than the previous predetermined minimum bit rate that distributes, this ratio of further distributing equal by the complexity of the signal representative on the relevant input of this centering with by the combinatorial complexity of the signal representative on the input all these centerings ratio.
6, multiplex system as claimed in claim 3, wherein:
Multiplexer (20) produces the signal with a predetermined constant bit rate at its output (15);
Each channel processor (10) is assigned a corresponding predetermined weight factor; And
Produce corresponding bit rate quota signal on the output of bit rate distributor (30) in every pair of relevant input and output side, so that each channel processor is assigned with the ratio of predetermined constant bit rate, its equal the signal representative on the complexity of the signal representative on the relevant input of this centering and input all these centerings combinatorial complexity ratio, with the predetermined weight factor weighting that is assigned to the related channel program processor.
7, multiplex system as claimed in claim 3, wherein:
Multiplexer (20) produces the signal with a predetermined constant bit rate at its output (15);
Each channel processor (10) is assigned a corresponding predetermined minimum bit rate and a predetermined weight factor; And
Produce corresponding bit rate quota signal on the output of bit rate distributor (30) in every pair of relevant input and output side, so that each channel processor is assigned with the predetermined minimum bit rate of appointment, and further be assigned the residue bit rate ratio, this residue bit rate equals the predetermined constant bit rate less than the previous predetermined minimum bit rate that distributes, the ratio that should further distribute equal the signal representative on the complexity of the signal representative on the relevant input of this centering and input all these centerings combinatorial complexity ratio, with the predetermined weight factor weighting that is assigned to the related channel program processor.
8, multiplex system as claimed in claim 3, wherein:
Each channel processor (10) is designated to have a corresponding predetermined bit rate to distribute the limit; And
After producing the corresponding positions rate quota signal that distributes bit rate to give respective channel processor (10), bit rate distributor (30) distributes corresponding bit rate with the corresponding predetermined bit rate distribution limit compares, if and a certain bit rate distributes the predetermined bit rate that surpasses an appointment to distribute the limit, then produce the bit rate quota signal that a predetermined bit rate of representative distributes the limit, replace the bit rate of previously generated related channel program processor to distribute.
9, it is that maximum bit rate is distributed that multiplex system as claimed in claim 8, wherein predetermined bit rate distribute the limit.
10, it is that minimum bit rate distributes that multiplex system as claimed in claim 8, wherein predetermined bit rate distribute the limit.
11, multiplex system as claimed in claim 3, wherein:
Each channel processor (10) is designated to have a corresponding predetermined bit rate to distribute the increment limit; And
Produce represent related channel program processor (10) distribute bit rate corresponding positions rate by norm after the signal, bit rate distributor (30) distributes corresponding bit rate and is compared by the corresponding bit rate distribution of the last corresponding positions rate quota signal representative that is right after, to determine that corresponding bit rate distributes increment, if and the predetermined bit rate that a certain bit rate distributes increment to surpass an appointment distributes the increment limit, then produce a representative by the bit rate quota signal that the represented bit rate of last corresponding positions rate quota signal that is right after that has changed the predetermined bit rate distribution increment limit distributes, replace the bit rate of previously generated related channel program processor to distribute.
12, multiplex system as claimed in claim 11, it is the maximal increment that bit rate increases that wherein predetermined bit rate distributes the increment limit.
13, multiplex system as claimed in claim 11, it is the maximal increment that bit rate reduces that wherein predetermined bit rate distributes the increment limit
14, multiplex system as claimed in claim 3, wherein:
Each channel processor (10) comprises that one has the output buffer (48) of the buffer capacity that temporarily stores data of giving multiplexer (20) to be supplied in the predetermined time cycle; And
Produce represent related channel program processor (10) distribute bit rate corresponding positions rate by norm after the signal, bit rate distributor (30) distributes corresponding bit rate and is compared by the corresponding bit rate distribution of back to back last corresponding positions rate quota signal representative, if and the bit rate distribution reduces, whether determine temporarily to be stored in data in the output buffer of related channel program processor will be in the predetermined time cycle distributes with the bit rate that reduces and offer multiplexer (20), then produce the bit rate quota signal that a new bit rate of representative distributes if not, this new bit rate distributes in the data predetermined time cycle in the output buffer that will allow temporarily to be stored in the related channel program processor and offers multiplexer (20), replaces the bit rate of previously generated related channel program processor to distribute.
15, multiplex system as claimed in claim 2, each in wherein a plurality of channel processors (10) comprises:
A constant bit rate encoders (14), have the data input pin (5) that is coupling in channel processor (10) and the data path between the data output end, with a quota input (Q) that is coupling in the control input end (" control ") of channel processor (10), be used to produce code signal; And
A complexity analyzing device (16) is coupling between the data input pin (5) and complexity output (" complexity ") of channel processor (10), is used to analyze the complexity that data input pin (5) is gone up signal, and produces complexity representative signal.
16, multiplex system as claimed in claim 15, wherein:
Constant bit rate encoders (14) comprises:
A variable quantization device (46) is coupling in the data path of constant bit rate encoders (14) and has control input end (Q
MB), be used for generation and have according to control input end (Q
MB) the quantized signal of quantization step of signal definition; And
Bit rate adjuster (49) is coupling in channel processor (10) data output end (T
MB) with the control input end (Q of variable quantization device (49)
MB) between, be used for according at the bit rate of the code signal of constant bit rate encoders (14) output (" data output ") with at constant bit rate encoders (14) the signal change quantization step of input (Q) by norm; And wherein:
Complexity analyzing device (16) comprises:
Complexity is determined circuit (92-99), has the control input end (Q that is coupled to variable quantization device (46)
MB) respective input, output (" data output ") with constant bit rate encoders, be used to produce complexity representative signal (Xpic), itself and average quantization step-length and relevant at the bit rate of the code signal of constant bit rate encoders output (" data output ").
17, multiplex system as claimed in claim 16, wherein complexity determines that circuit (92-99) produces complexity representative signal (Xpic), it is directly and average quantization step-length (Q
MB) and at the bit rate (T of the code signal of constant bit rate encoders output (" data output ")
MB) be directly proportional.
18, multiplex system as claimed in claim 17, wherein complexity determines that circuit (92-99) produces complexity representative signal (Xpic), it is average quantization step-length (Q
MB) with bit rate (T at the code signal of constant bit rate encoders output (" data output ")
MB) product.
19, multiplex system as claimed in claim 2, wherein:
Each data signal source (5) produces a data-signal, and this data-signal is a vision signal that comprises the consecutive image group, and every group of image comprises the frame of predetermined quantity;
Each channel processor (10) produces one time complexity representative signal at least during each consecutive image group; And
Bit rate distributor (30) response complexity representative signal produces bit rate quota signal at least one time during each consecutive image group.
20, multiplex system as claimed in claim 19, each in wherein a plurality of channel processors (10) comprises:
A constant bit rate encoders (14), have the data input pin (5) that is coupling in channel processor and the data path between the data output end, with a quota input (Q) that is coupling in the control input end (" control ") of channel processor (10), be used to produce code signal; And
A complexity analyzing device (16) is coupling between the data input pin (5) and complexity output (" complexity ") of channel processor (10), is used to analyze the complexity that data input pin (5) is gone up signal, and produces complexity representative signal.
21, multiplex system as claimed in claim 20, wherein:
Constant bit rate encoders (14) comprises:
A variable quantization device (46) is coupling in the data path of constant bit rate encoders (14) and has control input end (Q
MB), be used to produce the quantized signal that has according to the quantization step of the quantization step signal definition of control input end; And
Bit rate adjuster (49) is coupling in the control input end (Q of channel processor (10) data output end (" data output ") and variable quantization device (46)
MB) between, and has a bit rate control input end (Q) of being coupled to the output of relevant input and output side centering from bit rate distributor (30), be used for according at the bit rate of the code signal of constant bit rate encoders output (" data output ") with at the signal of bit rate control input end (Q), at the control input end (Q of variable quantization device (46)
MB) produce the quantification step size signal with the control quantization step; And wherein:
Complexity analyzing device (16) comprises:
Complexity is determined circuit (92-99), has the control input end (Q that is coupled to variable quantization device (46)
MB) respective input, output (" data output ") with constant bit rate encoders, be used to produce complexity representative signal (Xpic), itself and average quantization step-length and relevant at the bit rate of the code signal of constant bit rate encoders (14) output (" data output ").
22, multiplex system as claimed in claim 21, wherein:
Constant bit rate encoders (14) is divided into predetermined quantity (N according to Motion Picture Experts Group (MPEG) standard operation with each consecutive image in the vision signal of its data input pin (5)
MB) macro block, and sequentially with predetermined quantity (N
MB) each block encoding in the macro block is the position (T of respective number
MB) to produce a series of image encoded at its data output end (" data output ");
Bit rate adjuster (49) is predetermined quantity (N
MB) each piece in the macro block produces corresponding quantization step length command signal (Q
MB); And
Complexity determines that circuit (92-99) comprises:
Be coupled to first accumulator (92,93) of constant bit rate encoders data output end (" data output "), be used for corresponding each coded macroblocks and constant bit rate encoders (14) data output end (" data output ") gone up the corresponding figure place (T that produces
MB) summation, to produce the total bit (Tpic) in each of coding consecutive image;
Be coupled in second accumulator (96,97) of bit rate adjuster (49), be used for corresponding quantification step size signal (Q each each macro block of consecutive image
MB) summation;
Be coupled in the average circuit (98,99) of second accumulator (96,97), be used for calculating at each consecutive image predetermined quantity (N
MB) the average quantization step-length of macro block, to produce the average quantization step size signal (Q of each consecutive image
MB);
Multiplier (94) is coupled to first accumulator (92,93) and average circuit (98,99), is used for total bit (Tpic) be multiply by average quantization step size signal (Q
MB), to produce the image complexity signal (Xpic) of each consecutive image; And
The 3rd accumulator (30) is to the respective image complexity signal summation of each image in the image sets, to produce complexity representative signal (X
GOP)
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Cited By (2)
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CN105898384A (en) * | 2016-04-26 | 2016-08-24 | 广州盈可视电子科技有限公司 | Method and apparatus for controlling streaming video mixing frame rate |
CN110245756A (en) * | 2019-06-14 | 2019-09-17 | 第四范式(北京)技术有限公司 | Method for handling the programming device of data group and handling data group |
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US5134476A (en) * | 1990-03-30 | 1992-07-28 | At&T Bell Laboratories | Video signal encoding with bit rate control |
US5115309A (en) * | 1990-09-10 | 1992-05-19 | At&T Bell Laboratories | Method and apparatus for dynamic channel bandwidth allocation among multiple parallel video coders |
US5231484A (en) * | 1991-11-08 | 1993-07-27 | International Business Machines Corporation | Motion video compression system with adaptive bit allocation and quantization |
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CN105898384A (en) * | 2016-04-26 | 2016-08-24 | 广州盈可视电子科技有限公司 | Method and apparatus for controlling streaming video mixing frame rate |
CN105898384B (en) * | 2016-04-26 | 2019-03-22 | 广州盈可视电子科技有限公司 | A kind of method and apparatus of streaming media video mixing frame per second control |
CN110245756A (en) * | 2019-06-14 | 2019-09-17 | 第四范式(北京)技术有限公司 | Method for handling the programming device of data group and handling data group |
CN110245756B (en) * | 2019-06-14 | 2021-10-26 | 第四范式(北京)技术有限公司 | Programmable device for processing data sets and method for processing data sets |
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