CN114937431A

CN114937431A - Scanning driving circuit, display panel and display device

Info

Publication number: CN114937431A
Application number: CN202210611773.8A
Authority: CN
Inventors: 徐辽; 叶利丹
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2022-08-23

Abstract

The embodiment of the application discloses a scanning driving circuit, which comprises n scanning driving units which are sequentially arranged and cascaded, wherein each scanning driving unit receives a clock signal and outputs a scanning signal under the control of the clock signal. In one frame of image display period, each scanning signal comprises two scanning pulses separated by a preset time length, so as to control the corresponding pixel unit to receive the image display data in the time period corresponding to the two scanning pulses. When the scanning drive circuit disclosed by the application enables the display panel with the high refresh rate to display images, the charging time of the pixel unit is prolonged, the pixel unit has sufficient time to receive image display data, the display stability of the pixel unit is ensured, and the pixel charging process is optimized. The embodiment of the application also discloses a display panel and a display device comprising the scanning driving circuit.

Description

Scanning driving circuit, display panel and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a scan driving circuit, a display panel, and a display device.

Background

Less Gate Driver Less (GDL) technology is to use the original array process of the lcd panel to fabricate the driving Circuit of the horizontal scanning line on the substrate around the display area, so that it can replace the external Integrated Circuit (IC) to complete the driving of the horizontal scanning line. The GDL technology can reduce the welding process of the external IC, and can make the liquid crystal display panel more suitable for manufacturing narrow-frame or frameless display products.

The Dual Line Gate (DLG) technology means that two adjacent rows of scan lines are simultaneously turned on and output the same data, that is, two rows of pixel units receive the same image display data, and at this time, the resolution is reduced and the refresh rate is increased. However, the refresh rate increases, and the precharge time of the pixel decreases, which causes the sustain voltage of the pixel to decrease, and causes the pixel display to be abnormal.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present application provides a scan driving circuit for maintaining stable pixel voltage.

A scanning drive circuit comprises n scanning drive units and M clock signals which are sequentially arranged and cascaded, wherein n and M are integers larger than or equal to 1, each scanning drive unit receives one clock signal and outputs one scanning signal under the control of the clock signal, and the scanning signals are used for being output to scanning lines in a display area and controlling pixel units correspondingly connected to the scanning lines to receive image display data so as to execute image display. In one frame of image display period, the clock signal controls each scanning driving unit to output scanning signals, each scanning signal comprises two scanning pulses separated by a preset time length, and therefore the corresponding pixel unit is controlled to receive image display data in a time period corresponding to the two scanning pulses.

Optionally, the voltage of the scan pulse is used to start the pixel unit and receive the image display data, the scan pulse lasts for a first duration, and the clock signal comprises a plurality of consecutive pulses, each of which lasts for the first duration.

Optionally, the display region includes a plurality of scan lines arranged along a first direction, a plurality of data lines arranged along a second direction, the second direction is perpendicular to the first direction, a plurality of pixel units arranged in an array are arranged in rows along the first direction and connected to one of the scan lines to receive a scan signal, and a plurality of pixel units are arranged in columns along the second direction and connected to one of the data lines to receive image display data. The ith clock signal in the M clock signals has the same phase with the (i + 1) th clock signal, i is more than or equal to 1 and less than M, i is an odd number, the two clock signals with the same phase control the corresponding scanning driving units to simultaneously output scanning signals, and the two scanning signals simultaneously output control the corresponding two rows of pixel units to receive the same image display data.

Optionally, the display period of the one frame image has a first display duration (F), the first duration being 2 × F/n.

Optionally, the kth scan driving unit receives the kth-4 scan signal output by the kth-4 scan driving unit to control the kth scan driving unit to output the kth scan signal. The Kth scanning driving unit receives the Kth +8 scanning signal output by the Kth +8 scanning driving unit to control the Kth scanning driving unit to stop outputting the Kth scanning signal, wherein K is more than or equal to 5 and less than or equal to n.

Optionally, the kth scan driving unit includes a pull-up control module, a pull-up module, and a first node, and the pull-up control module and the pull-up module are electrically connected to the first node. The pull-up control module receives a K-4 scanning signal output by the K-4 scanning driving unit, and pulls up the voltage of the first node to a first potential under the control of the K-4 scanning signal, and when the voltage of the first node is the first potential, the pull-up module receives a clock signal and outputs the K scanning signal from the scanning signal output end.

Optionally, the kth scan driving unit further includes a pull-down control module and a pull-down module, the pull-down control module is electrically connected to the first node and the low-voltage potential terminal, and the pull-down module is electrically connected to the scan signal output terminal and the low-voltage potential terminal. The pull-down control module receives a K +8 th scanning signal output by the K +8 th scanning driving unit and pulls down the voltage of the first node to a second potential under the control of the K +8 th scanning signal. The pull-down module is used for receiving a K +8 th scanning signal output by the K +8 th scanning driving unit, and controlling the scanning signal output end to be connected with the low-voltage potential end under the control of the K +8 th scanning signal so as to control the K th scanning signal to stop outputting.

Optionally, the pull-up control module includes a first transistor, a gate and a source of the first transistor are connected to the kth-4 th level transmission signal, and a drain of the first transistor is electrically connected to the first node. The pull-up module comprises a second transistor, wherein the grid electrode of the second transistor is electrically connected to the first node, the source electrode of the second transistor is connected to the clock signal, and the drain electrode of the second transistor is electrically connected to the scanning signal output end. The pull-down control module comprises a third transistor, wherein the grid electrode of the third transistor is connected with the K +8 th scanning signal, the source electrode is electrically connected with the first node, and the drain electrode is electrically connected with the low-voltage potential end. The pull-down module comprises a fourth transistor, wherein the grid electrode of the fourth transistor is connected with a +8 th scanning signal, the source electrode of the fourth transistor is connected with the output end of the scanning signal, and the drain electrode of the fourth transistor is connected with the low-voltage potential end.

Optionally, the scan driving unit further includes a voltage stabilizing capacitor, and one end of the voltage stabilizing capacitor is connected to the first node, and the other end of the voltage stabilizing capacitor is connected to the scan signal output end, so as to control the scan signal output to be stable.

The application also provides a display panel, including being a plurality of pixel units of matrix arrangement and aforementioned scanning drive circuit, scanning drive circuit is according to the grid output control signal that shows control circuit output, and cooperation data drive circuit basis the source output control signal that shows control circuit output and the data signal drive of output pixel unit carries out image display.

The application also provides a display device, including braced frame, power module and aforementioned display panel, the power module carries out image display for display panel and provides mains voltage, and display panel and power module are fixed in braced frame.

Compared with the prior art, the scanning driving circuit provided by the application has the advantages that when the display panel with the high refresh rate is used for displaying images, the charging time of the pixel unit is prolonged, the pixel unit has sufficient time to receive image display data, the display stability of the pixel unit is ensured, and the pixel charging process is optimized.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display device according to a first embodiment of the present application;

fig. 2 is a schematic side view of a display module shown in fig. 1 according to a second embodiment of the present disclosure;

FIG. 3 is a schematic view of a planar layout structure of the display module shown in FIG. 2;

fig. 4 is a schematic circuit diagram of a scan driving circuit shown in fig. 3 according to a third embodiment of the present disclosure;

FIG. 5 is an equivalent circuit diagram of the GDL unit in FIG. 4;

FIG. 6 is a schematic diagram of a cascade of GDL units of FIG. 4;

FIG. 7 is a timing diagram of output of scan signals of a dual-line gate circuit according to a fourth embodiment of the present application;

fig. 8 is a timing diagram of output of scanning signals of a two-line gate circuit according to a fifth embodiment of the present application.

Description of reference numerals: display device-100, display module-10, data drive circuit-11, scanning drive circuit-12, display panel-13, display control circuit-14, pixel unit-15, backlight module-17, first direction-F1, second direction-F2, scanning lines-G1-Gn, data lines-S1-Sm, horizontal synchronizing signal-Hsyn, vertical synchronizing signal-Vsyn, gate output control signal-Cg, source output control signal-Cs, clock signal-CLK, scanning drive unit-140, scanning signals-G (1) -G (n), power supply module-20, support frame-30, array substrate-131, liquid crystal layer-132, color film substrate-133, pull-up control module-141, pull-up module-142, The driving circuit comprises a pull-down control module-143, a pull-down module-144, a first node-Q (N), a voltage stabilizing capacitor-C (N), a scanning signal output end-GOUT, a first transistor-T1, a second transistor-T2, a third transistor-T3, a fourth transistor-T4, a first charging time period-T1, a second charging time period-T2, a starting signal-STV and a low-voltage potential-Vss.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments that can be implemented by the application. The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). Directional phrases referred to in this application, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer to the orientation of the appended drawings and are therefore used in a better and clearer sense of description and understanding of the present application, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be considered limiting of the present application.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art. It should be noted that the terms "first", "second", and the like in the description and claims of the present application and in the drawings are used for distinguishing different objects and not for describing a particular order.

Furthermore, the terms "comprises," "comprising," "includes," "including," or "including," when used in this application, specify the presence of stated features, operations, elements, and/or the like, but do not limit one or more other features, operations, elements, and/or the like. Furthermore, the terms "comprises" or "comprising" mean that there are corresponding features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device 100 according to a first embodiment of the present application. The display device 100 includes a display module 10, a power module 20 and a supporting frame 30, the display module 10 and the power module 20 are fixed to the supporting frame 30, and the power module 20 is disposed on the back of the display module 10, which is the non-display surface of the display module 10. The power module 20 is used for providing a power voltage for the display module 10 to display images, and the supporting frame 30 provides fixing and protecting functions for the display module 10 and the power module 20.

Referring to fig. 2, fig. 2 is a schematic side view of a display module 10 shown in fig. 1 according to a second embodiment of the present disclosure.

The display Module 10 includes a display panel 13 and a backlight Module 17 (BM), wherein the backlight Module 17 is used for providing light for display to the display panel 13, and the display panel 13 emits corresponding light according to an image signal to be displayed to perform image display. That is, the power module 20 can be used to provide a power voltage for the display panel 13 to display images, and the supporting frame 30 provides fixing and protecting functions for the display panel 13 and the power module 20.

The display module 10 further includes other elements or components, such as a signal processor module and a signal sensing module.

In an exemplary embodiment, the display panel 13 may be a liquid crystal display panel, and may also be other types of display panels, which are not shown in this application.

Taking the liquid crystal display panel AS an example, the display panel 13 includes an Array Substrate (AS) 131, a Color filter substrate (CF) 133, and a liquid crystal layer 132 sandwiched between the Array substrate 131 and the Color filter substrate 133. The driving elements disposed on the array substrate 131 and the color filter substrate 133 generate corresponding electric fields according to the Data signals Data, so as to drive the liquid crystal molecules in the liquid crystal layer 132 to rotate at an angle to emit light rays with corresponding brightness, thereby performing image display.

Referring to fig. 3, fig. 3 is a schematic plan layout structure of the display module 10 in fig. 2.

As shown in fig. 3, the display region of the display panel 13 includes a plurality of scan lines (Gate lines) G1 to Gn extending in the first direction F1 and a plurality of data lines (Source lines) S1 to Sm extending in the second direction F2, which are arranged in a grid pattern. The first direction F1 and the second direction F2 are perpendicular to each other.

The intersections of the plurality of scan lines G1-Gn and the plurality of data lines S1-Sm are each provided with a plurality of pixel cells 15 arranged in an array, the pixel cells 15 arranged in a row along the first direction F1 and connected to one of the scan lines to receive a scan signal, and the pixel cells 15 arranged in a column along the second direction F2 and connected to one of the data lines to receive the image display data. In this embodiment, the pixel units 15 are represented by P11-P1 m, P21-P2 m, … …, Pn 1-Pnm, respectively.

The scan lines G1 to Gn are connected to the scan driving circuit 12 and receive scan signals from the scan driving circuit 12, and the Data lines S1 to Sm are connected to the Data driving circuit 11 and convert image signals or Data signals (Data) held and transmitted in a gray scale format supplied from the Data driving circuit 11 into corresponding analog voltage values.

The pixel unit 15 receives the Data voltages corresponding to the gray levels in the Data signals Data provided from the Data lines S1 to Sm for a predetermined period of time under the control of the scan lines G1 to Gn, and accordingly drives the liquid crystal layer 132 to deflect a corresponding angle, so that the received backlight emits light rays with corresponding brightness according to the deflected corresponding angle, and image display is performed by emitting the light rays with corresponding brightness according to the image signals.

The display module 10 further includes a data driving circuit 11, a scan driving circuit 12, and a display control circuit 14. The display control circuit 14 receives an original Data signal representing image information, a clock signal CLK for synchronization, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn from an external signal source of the display module 10, and outputs a gate output control signal Cg for controlling the scan driving circuit 12, a source output control signal Cs for controlling the Data driving circuit 11, and an adjustment Data signal Data representing image information. In this embodiment, the display control circuit 14 performs Data adjustment processing on the original Data signal to obtain an adjusted Data signal Data, and transmits the adjusted Data signal Data to the Data driving circuit 11.

The scanning drive circuit 12 receives the gate output control signal Cg outputted from the display control circuit 14, and outputs scanning signals to the scanning lines G1 to Gn. The Data drive circuit 11 receives the source output control signal Cs output from the display control circuit 14, and outputs Data signals Data for driving element execution image display in each pixel unit 15 in the display panel 13 to the respective Data lines S1 to Sm. The Data signal Data supplied to the display panel 13 is a gray scale voltage in an analog form. The scan driving circuit 12 outputs a scan signal, outputs an image signal from the data driving circuit 11, and can apply a voltage corresponding to a data signal for driving to the driving element in the pixel unit 15 to drive the liquid crystal molecules to perform image display. The scan driving circuit 12 is disposed in a non-display region of the display panel 13, and controls the pixel units 15 disposed in the display panel 13 to display an image.

Referring to fig. 4, fig. 4 is a schematic circuit structure diagram of the scan driving circuit 12 shown in fig. 3 according to a third embodiment of the present disclosure. As shown in fig. 4, the scan driving circuit 12 includes n cascaded scan driving units 140, M clock signals CLK1-CLKM, a start signal STV, and a low voltage potential VSS, where n and M are integers greater than or equal to 1. The scan driving unit 140 is hereinafter denoted by a GDL unit for convenience of description.

Each of the n GDL units correspondingly outputs a scanning signal to a scanning line in the display module 10, and in the process of displaying a frame of image, the n GDL units correspondingly output n scanning signals, which are G (1) -G (n), respectively.

In the present embodiment, taking eight clock signals as an example, i.e., M is 8, the first clock signal CLK 1-the eighth clock signal CLK8 are used to provide scanning driving timing for the GDL unit output driving signals. The start signal STV output by the display control circuit 14 is the enable start signal of the first GDL unit GDL1, and the other GDL units receive the scan signal output by the cascaded GDL units as the start signal. The low voltage potential VSS is used to provide a low voltage for the nodes and signals in the GDL cell.

In an exemplary embodiment, the scan driving circuit 12 may also be controlled by other number of clock signals, and the application is not limited thereto.

Referring to fig. 5, fig. 5 is an equivalent circuit diagram of the GDL unit in fig. 4. As shown in fig. 5, taking the kth GDL unit as an example, where K is greater than or equal to 5 and less than or equal to n, the kth GDL unit includes a pull-up control module 141, a pull-up module 142, a pull-down control module 143, a pull-down module 144, a first node q (K), and a voltage stabilizing capacitor c (K).

The pull-up control module 141 is connected to the first node q (K) and receives the K-4 th scan signal G (K-4) output by the K-4 th GDL unit. The potential of the first node Q (K) is pulled up to the first potential by the K-4 th scanning signal G (K-4).

The pull-up module 142 receives an ith clock signal CLK (i) (1 ≦ i ≦ M), a first node Q (K), and an output node GOUT, and when the voltage of the first node Q (K) is a first potential, is configured to receive the ith clock signal CLK (i) and control the scanning signal output terminal GOUT to output a K-th scan signal G (K), where the first potential is at a high level.

The pull-down control module 143 is connected to the K +8 th scan signal G (K +8), the first node q (K), and the low voltage potential VSS, and is configured to pull down the potential of the first node q (K) to a second potential under the control of the K +8 th scan signal G (K +8), where the second potential is the low voltage potential VSS.

The pull-down module 144 is connected to the K +8 th scan signal G (K +8) and the scan signal output terminal GOUT, and controls the scan signal output terminal GOUT to be connected to the low voltage potential terminal VSS under the control of the K +8 th scan signal G (K +8) to control the K-th scan signal G (K) to stop outputting.

The voltage stabilizing capacitor c (K) is connected between the first node q (K) and the scanning signal output terminal GOUT, and due to the arrangement of the voltage stabilizing capacitor c (K), when the pull-up control module 141 stops pulling up the voltage of the first node q (K), the voltage of the first node q (K) is maintained for a period of time to control the output of the kth scanning signal to be complete, so that the output of the kth scanning signal g (K) is stable.

Specifically, the pull-up control module 141 includes a first transistor T1, a gate and a source of the first transistor T1 are connected to an input terminal (not shown) of the K-4 th scan signal G (K-4), and a drain of the first transistor T1 is electrically connected to the first node q (K). The pull-up module 142 includes a second transistor T2, a source of the second transistor T2 receives an ith clock signal clk (i), a gate of the second transistor is connected to the first node q (k), and a drain of the second transistor is connected to the scan signal output terminal GOUT. The pull-down control module 143 includes a third transistor T3, a source of the third transistor T3 is connected to a first node q (K), a gate thereof is connected to an output terminal (not shown) of the K +8 th scan signal G (K +8), and a drain thereof is connected to the low voltage potential VSS. The pull-down module 144 includes a fourth transistor T4, the source of the fourth transistor T4 is connected to the output terminal GOUT of the scan signal, the gate is connected to the output terminal (not shown) of the K +8 th scan signal G (K +8), and the drain is connected to the low voltage potential VSS.

Referring to fig. 6, fig. 6 is a schematic diagram of a cascade of GDL units shown in fig. 4. As shown in FIG. 6, taking the Kth GDL unit as an example, where K is greater than or equal to 5 and less than or equal to n, the Kth GDL unit outputs the Kth scan signal G (K) for pulling up the node voltage in the Kth +4 GDL unit, so as to control the Kth +4 GDL unit to output the Kth +4 scan signal G (K +4), and at the same time, for pulling down the node voltage in the Kth-8 GDL unit, so as to control the Kth-8 GDL unit to stop outputting the Kth-8 scan signal G (K-8).

Taking the 9 th GDL unit GDL9 as an example, the 9 th GDL unit GDL9 outputs the 9 th scan signal G (9) for pulling up the node voltage in the 13 th GDL unit GDL13, so as to control the 13 th GDL unit GDL13 to output the 13 th scan signal G (13), and simultaneously, for pulling down the node voltage in the 1 st GDL unit GDL1 to stop outputting the 1 st scan signal G (1).

That is, the Kth GDL unit receives the K-4 th scan signal G (K-4) and the K +8 th scan signal G (K +8) at the same time, receives the K-4 th scan signal G (K-4) outputted by the K-4 th scan signal for pulling up the node voltage in the Kth GDL unit to control and output the K scan signal G (K), receives the K +8 th scan signal G (K +8) outputted by the K +8 th scan driving unit for pulling down the node voltage in the Kth GDL unit to control the Kth GDL unit to stop outputting the K scan signal G (K).

Taking the 5 th GDL unit GDL5 as an example, the 5 th GDL unit receives the 1 st scan signal G (1) and the 13 th scan signal G (13) at the same time, receives the 1 st scan signal G (1) for pulling up the node voltage in the 5 th GDL unit to control the 5 th scan signal G (5) to be output, receives the 13 th scan signal G (13) for pulling down the node voltage in the 5 th GDL unit to control the 5 th GDL unit to stop outputting the 5 th scan signal G (5).

The scanning signal of the current GDL unit is controlled to be pulled down by the scanning signals output by 8 GDL units at intervals, so that the scanning signal output by the current GDL unit has longer time, and the pixel controlled by the current scanning signal has enough pre-charging time to receive the Data signal Data.

Referring to fig. 7, fig. 7 is a timing diagram of output of scan signals of a two-line gate circuit according to a fourth embodiment of the present application. As shown in fig. 7, a Dual Line Gate (DLG) circuit means that two adjacent rows of scan lines are simultaneously turned on and output the same data, that is, two rows of pixels display the same content, for example, in a 4K (3840 × 2160) display panel, each frame of image originally needs to scan 2160 rows in total, that is, scan 2160 times, and scan 60 frames of images in one second, that is, the refresh rate is 60Hz, whereas with the DLG technology, only 1080 times of scanning is needed, and half the time in one second is reduced, so that 120 frames of images can be scanned, that is, the refresh rate is 120Hz, and the refresh rate during image display is improved.

However, the refresh rate is increased, which results in a decrease in the time for the pixel unit to receive the Data signal Data. Specifically, when 60Hz refresh is adopted, that is, 60 frames of images are displayed one second, the image display duration for one frame is 1/60s, the time for scanning one row of pixel cells in the 4K display panel is H1F/2160, H1 7.4us, and the pixel cell precharge time is 2H1 14.8um, that is, the pixel cell precharge time is 14.8 us. When the refresh is performed at 120Hz, the time for scanning a row of pixel cells is H2-3.7 um, and the pixel cell pre-charge time is 2H 2-7.4 us, i.e. the pixel cell pre-charge time is 7.4 us. At this time, the actual pre-charge time of the pixel unit is reduced by half, so that the pre-charge time of the pixel unit is reduced, the sustain voltage of the pixel unit is reduced, and the pixel display is abnormal.

Referring to fig. 8, fig. 8 is a timing diagram of output of scan signals of a dual-line gate circuit according to a fifth embodiment of the present disclosure. As shown in fig. 8, the scan driving circuit 12 outputs scan signals by using DLG technology, that is, two adjacent rows of scan signals control corresponding two adjacent rows of pixel units to receive the same data. When the M clock signals control the output of the scanning signals, the phase of the ith clock signal CLKi is the same as that of the (i + 1) th clock signal CLKi +1, wherein i is more than or equal to 1 and less than M, and i is an odd number, the two clock signals with the same phase control the corresponding scanning driving units to simultaneously output the scanning signals, and the two scanning signals simultaneously output control the corresponding two rows of pixel units to receive the same image display data.

Taking eight clock signals CLK as an example for control, among the eight clock signals, the first clock signal CLK1 has the same phase as the second clock signal CLK2, and two scanning signals are controlled to be output simultaneously to control the two corresponding rows of pixel cells to receive the same image display data. The third clock signal CLK3 has the same phase as the fourth clock signal CLK4, and controls the two scan signals to be output simultaneously to control the two corresponding rows of pixel cells to receive the same image display data. The fifth clock signal CLK5 is in the same phase as the sixth clock signal CLK6, and controls the two scan signals to be output simultaneously to control the corresponding two rows of pixel cells to receive the same image display data. The seventh clock signal CLK7 is in the same phase as the eighth clock signal CLK8, and controls the two scan signals to be output simultaneously to control the corresponding two rows of pixel cells to receive the same image display data. The two clock signals with the same phase control the corresponding scanning driving units to simultaneously output scanning signals, and the two scanning signals simultaneously output control the corresponding two rows of pixel units to receive the same image display data. In one frame of image display period, the clock signal CLK controls each scan driving unit to output a corresponding scan signal, where each scan signal includes two scan pulses separated by a preset duration, so as to control the corresponding pixel unit to receive image display data in a time period corresponding to the two scan pulses. The scanning pulse is used for starting the pixel units of the corresponding row and receiving image display data, the duration of one scanning pulse is a first duration 2H, 2H is 7.4um, the total duration of the scanning pulse of one scanning signal is 4H, and 4H is 14.8 um. The clock signal CLK controls the output of the scan signal, which also outputs a pulse signal having a duration of 4H.

For example, taking the 1 st scan signal G (1) as an example, the 1 st scan signal is pulled down by the 9 th scan signal G (9), so that the 1 st scan signal has two scan pulses, the first row of pixel cells are controlled to receive the corresponding Data signal Data by the two scan pulses, the first row of pixel cells are charged for 2H, i.e., 7.4us, in the first charging period t1, i.e., the first pulse period, and the first row of pixel cells are charged for 2H, i.e., 7.4us, in the second charging period t2, i.e., the second pulse period, so that the total charging time of the first row of pixel cells is 4H, i.e., 14.8 s.

In an exemplary embodiment, the scan driving circuit 12 may also be used in other display modules with a high refresh rate to optimize the pixel display effect of the display module, which is not limited in this application.

The scanning driving circuit 12 provided by the embodiment of the application enables the pixel unit to have sufficient time to receive the Data signal Data when the display module utilizes the DLG technology to increase the refresh rate from 60Hz to 120Hz, thereby avoiding the pixel charging abnormality caused by adopting the DLG technology to refresh, ensuring the display stability of the pixel unit and optimizing the pixel charging process.

It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.

Claims

1. A scanning drive circuit comprises n scanning drive units and M clock signals which are sequentially arranged and cascaded, wherein n and M are integers larger than or equal to 1, each scanning drive unit receives one clock signal and outputs one scanning signal under the control of the clock signal, and the scanning signals are used for being output to scanning lines in a display area and controlling pixel units correspondingly connected to the scanning lines to receive image display data so as to execute image display;

the scanning driving method is characterized in that in a frame image display period, the clock signal controls each scanning driving unit to output the scanning signal, each scanning signal comprises two scanning pulses which are separated by a preset time length, and the corresponding pixel unit is controlled to receive the image display data in a time period corresponding to the two scanning pulses.

2. The scan drive circuit of claim 1,

the voltage of the scanning pulse is used for starting the pixel unit and receiving the image display data, the scanning pulse lasts for a first duration, and the clock signal comprises a plurality of continuous pulses, wherein each pulse lasts for the first duration.

3. The scan drive circuit of claim 2,

the display area comprises a plurality of scanning lines arranged along a first direction, a plurality of data lines arranged along a second direction, the second direction is perpendicular to the first direction, a plurality of pixel units arranged in an array are arranged in a row along the first direction and connected to one of the scanning lines to receive the scanning signals, and a plurality of pixel units are arranged in a column along the second direction and connected to one of the data lines to receive the image display data;

the ith clock signal in the M clock signals has the same phase as the (i + 1) th clock signal, i is more than or equal to 1 and less than M, and i is an odd number; the two clock signals with the same phase control the corresponding scanning driving units to output the scanning signals at the same time, and the two scanning signals output at the same time control the corresponding two rows of pixel units to receive the same image display data.

4. The scan drive circuit of claim 3,

the Kth scanning driving unit receives the Kth-4 scanning signal output by the Kth-4 scanning driving unit to control the Kth scanning driving unit to output the Kth scanning signal;

the Kth scanning driving unit receives the Kth +8 scanning signal output by the Kth +8 scanning driving unit to control the Kth scanning driving unit to stop outputting the Kth scanning signal, wherein K is more than or equal to 5 and less than or equal to n.

5. The scan driving circuit according to claim 4, wherein the kth scan driving unit comprises a pull-up control module, a pull-up module and a first node, the pull-up control module and the pull-up module being electrically connected to the first node;

the pull-up control module receives a K-4 th scanning signal output by the K-4 th scanning driving unit and pulls up the voltage of the first node to a first potential under the control of the K-4 th scanning signal,

and when the voltage of the first node is the first potential, the pull-up module receives the clock signal and outputs a Kth scanning signal from a scanning signal output end.

6. The scan driving circuit according to claim 5, wherein the kth scan driving unit further comprises a pull-down control module and a pull-down module, the pull-down control module is electrically connected to the first node and a low voltage potential terminal, and the pull-down module is electrically connected to the scan signal output terminal and the low voltage potential terminal;

the pull-down control module receives a K +8 th scanning signal output by the K +8 th scanning driving unit and pulls down the voltage of the first node to a second potential under the control of the K +8 th scanning signal;

the pull-down module is used for receiving a K +8 th scanning signal output by the K +8 th scanning driving unit, and controlling the scanning signal output end to be connected with the low-voltage potential end under the control of the K +8 th scanning signal so as to control the K scanning signal to stop outputting.

7. The scan driver circuit of claim 6,

the pull-up control module comprises a first transistor, a grid electrode and a source electrode of the first transistor are connected with a K-4 level transmission signal, and a drain electrode is electrically connected to the first node;

the pull-up module comprises a second transistor, wherein the grid electrode of the second transistor is electrically connected to the first node, the source electrode of the second transistor is connected to the clock signal, and the drain electrode of the second transistor is electrically connected to the scanning signal output end;

the pull-down control module comprises a third transistor, wherein the grid electrode of the third transistor is accessed with a K +8 th scanning signal, the source electrode of the third transistor is electrically connected with the first node, and the drain electrode of the third transistor is electrically connected with the low-voltage potential end;

the pull-down module comprises a fourth transistor, wherein the grid electrode of the fourth transistor is connected with a +8 th scanning signal, the source electrode of the fourth transistor is connected with the scanning signal output end, and the drain electrode of the fourth transistor is connected with the low-voltage potential end.

8. The scan driving circuit according to claim 7, wherein the scan driving unit further comprises a voltage stabilizing capacitor having one end connected to the first node and the other end connected to the scan signal output terminal for controlling the scan signal output to be stable.

9. A display panel, comprising a plurality of pixel units arranged in a matrix and the scan driving circuit as claimed in any one of claims 1 to 8, wherein the scan driving circuit drives the pixel units to display images according to the gate output control signal outputted by the display control circuit and the data signal outputted by the data driving circuit according to the source output control signal outputted by the display control circuit.

10. A display device, comprising a supporting frame, a power module and the display panel of claim 9, wherein the power module provides a power voltage for the display panel to display images, and the display panel and the power module are fixed to the supporting frame.