CN114935676A - Digital circuit and method for preprocessing trigger data based on FPGA - Google Patents
Digital circuit and method for preprocessing trigger data based on FPGA Download PDFInfo
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Abstract
The invention discloses a digital circuit and a method for preprocessing trigger data based on FPGA, wherein the digital circuit comprises: the ADC and the digital comparison module, wherein the output end of the ADC is coupled with the digital comparison module, the digital comparison module comprises a plurality of digital comparators, and reference level values are arranged in the digital comparators: a high trigger level, a low trigger level, a high hysteresis voltage VH and a low hysteresis voltage VL; the low hysteresis voltage VL is used as a low hysteresis voltage VL which is common to the low trigger level and the high trigger level, and the high hysteresis voltage VH is used as a high hysteresis voltage VH which is common to the low trigger level and the high trigger level; the invention improves the triggering efficiency by preprocessing the data points which are output by the digital comparator and can not obtain the level value.
Description
Technical Field
The invention relates to the technical field of trigger data, in particular to a digital circuit and a method for preprocessing trigger data based on an FPGA (field programmable gate array).
Background
After the signal of the digital oscilloscope is input, the signal is divided into two paths, and one path can be stored and recorded after being sampled and quantized by the ADC; the other path can generate a starting signal to control sampling storage through a trigger;
referring to fig. 1, since the resolution of the ADC is multi-bit, when the sampled waveform has relatively large noise or the rise time is very long, the number of points near the trigger acquired by the ADC will have a certain data jitter near the trigger, which causes noise to appear on the rising edge and the falling edge of the square wave compared by the digital comparison, and causes misjudgment to appear on the rising edge and the falling edge of the waveform to cause misjudgment on the trigger edge;
when noise is processed, one method at present needs to repeatedly calculate data before the preprocessed data through processing the data, and when the data volume acquired by the ADC is large, the calculation scale is large and the number of required digital comparators is large, so that the efficiency of preprocessing the data is low, and a large amount of software and hardware resources are wasted.
The prior art can not meet the requirements of people at the present stage, and the prior art is urgently needed to be reformed based on the current situation.
Disclosure of Invention
The present invention aims to provide a digital circuit and method for preprocessing trigger data based on an FPGA, so as to solve the problems in the background art.
On one hand, the invention provides a digital circuit for preprocessing trigger data based on FPGA, which comprises: ADC, digital comparison module, multi-stage data calculation processing unit;
the ADC output end is coupled with the digital comparison module, and the digital comparison module comprises a plurality of digital comparators;
preferably, a reference level value is set in the digital comparator: the high-hysteresis trigger circuit comprises a high trigger level, a low trigger level, a high hysteresis voltage VH and a low hysteresis voltage VL, wherein the low hysteresis voltage VL is used as a low hysteresis voltage VL which is common to the low trigger level and the high trigger level, and the high hysteresis voltage VH is used as a high hysteresis voltage VH which is common to the low trigger level and the high trigger level;
the ADC collects data and then sequentially transmits the data to each digital comparator, the data are compared with reference level values in the digital comparators and then output to the multi-stage data calculation processing units, the multi-stage data calculation processing units are set according to data quantity collected by the ADC at the same time, namely the number of the multi-stage data calculation processing units is the same as the data quantity collected by the ADC at the same time, for example, 8 levels are arranged in each multi-stage data calculation processing unit, and each data bit is processed respectively; the multi-stage data calculation processing unit outputs high level or low level after processing the relevant bits of the data.
On the other hand, the invention provides another technical scheme as follows, namely a method for preprocessing trigger data based on FPGA, which preprocesses data of each bit, uses a production line to complete calculation and reduces the calculation scale, and the specific method comprises the following steps:
step 1: reducing the reference level value, and directly comparing the data acquired by the ADC with the reference trigger level value;
preferably, the low hysteresis voltage VL at the low trigger level is also used as the low hysteresis voltage VL at the high trigger level, and the high hysteresis voltage VH at the high trigger level is also used as the high hysteresis voltage VH at the low trigger level, so that only 4 trigger level values exist: the high trigger level, the low trigger level, the high hysteresis voltage VH and the low hysteresis voltage VL are adopted, so that only 4 hysteresis comparators are needed for processing;
after data collected by the ADC enter a digital comparator, the data are directly compared with a set reference level value, if the data are greater than a high hysteresis voltage VH of a high trigger level, a level 1 can be directly assigned, and if the data are less than a low hysteresis voltage VL of a low trigger level, a level 0 can be directly assigned;
step 2: preprocessing the relevant bits of the trigger data, recoding, and dividing data which can obtain the determined position and data which can not obtain the determined position:
preferably, step 2 includes step 201: for the data which can obtain the determined position after being compared by a digital comparator, the highest bit code is 1;
for the data point of the high hysteresis voltage VH which is greater than the high trigger level, marking as the trigger high level, setting as level 1 and coding as 110;
recording a data point of a low hysteresis voltage VL which is smaller than the low trigger level as a trigger low level, setting the data point as a level 0 and coding the data point as 100;
for data of a high hysteresis voltage VH smaller than a high trigger level and a low hysteresis voltage VL larger than a low trigger level, the data passes through the high trigger level but does not reach the threshold of the low hysteresis voltage VL of the low trigger level, the low level needs to be maintained, which is defined as a mark 0 and is coded as 101;
for data of a low hysteresis voltage VL greater than a low trigger level and a high hysteresis voltage VH less than a high trigger level, a threshold of the high hysteresis voltage VH, which has passed the low trigger level but has not passed the high trigger level, needs to be maintained at a high level, is defined as a flag 1, and is coded as 111;
preferably, step 2 further comprises 202: for the data which cannot obtain the determined position after being compared by the digital comparator, the level value cannot be directly obtained, and the data needs to be preprocessed and coded, wherein the coding is as follows:
if the data point in a period has no over-high level or low level, defining that the level value of the data point is only related to the level value of the previous data point, and keeping the state of the previous period, and encoding the level value to be 000;
if the level of the data point in one period is too high, the level value of the data point is only related to the level value of the previous data point, the state of the previous period is maintained, and the code is 001;
if the data point in a period has a too low level, defining that the level value of the data point is only related to the level value of the previous data point, keeping the state of the previous period and coding the level value into 010;
for a data point in a period, if an overhigh level and an overlow level occur, defining that the level value of the data point is only related to the level value of the previous data point, keeping the state of the previous period, and encoding to be 011;
and step 3: 2-bit encoding the position of the input waveform;
when the data value is smaller than the low hysteresis voltage VL of the low trigger level, the code is set to 00 and defined as level 0, namely the trigger level is low level;
when the data value is larger than the high hysteresis voltage VH of the high trigger level, the code is set as 10 and defined as level 1, namely the trigger level is high level;
when the data value is greater than the high hysteresis voltage VH of the low trigger level and less than the high trigger level, the code is 11, and the data value is defined as mark 1, namely the threshold of the high hysteresis voltage VH which has passed the low trigger level but has not passed the high trigger level needs to be kept at the high level;
when the data value is less than the high trigger level and greater than the low hysteresis voltage VL of the low trigger level, the code is 01, and the data value is defined as a flag 0, that is, the high trigger level has been passed, but the threshold of the low hysteresis voltage VL to the low trigger level does not exist, and the low level needs to be maintained;
and 4, step 4: and (4) comparing the three-bit code in the step (2) with the two-bit code in the step (3) to obtain two-bit level output.
The invention has the following beneficial effects:
on one hand, the invention is provided with a multi-stage data calculation processing unit for preprocessing each stage of data points, and for telling the ADC to collect 40 data points at the same time, the calculation amount is reduced by 2 30 To 2 31 The triggering efficiency is effectively improved;
on the other hand, the invention adopts a pipeline calculation method, reduces the reference level value, reduces the 6 trigger level values into 4 trigger level values, and recodes the preprocessed data points, thereby not only reducing the calculation scale, but also enabling the output square wave to be smoother and effectively eliminating the jitter.
Drawings
FIG. 1 is a schematic diagram of noise generation near a trigger level;
FIG. 2 is a diagram illustrating encoding of data according to the present invention;
FIG. 3 is a comparison of noise jittered square waves before and after processing data according to the present invention;
FIG. 4 is a more schematic illustration of noise dithering;
FIG. 5 is a block diagram illustrating the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the invention without making any creative effort, shall fall within the protection scope of the invention.
Referring to fig. 5, the present invention provides a digital circuit and method for preprocessing trigger data based on FPGA,
the method comprises the following steps: ADC, digital comparison module, multi-stage data calculation processing unit;
the ADC output end is coupled with the digital comparison module, the digital comparison module comprises a plurality of digital comparators, and reference level values are arranged in the digital comparators: the ADC acquires data and then sequentially transmits the data to each digital comparator, the data is compared with a reference level value in the digital comparator and then output to the multi-stage data calculation processing unit, the multi-stage data calculation processing unit is set according to the data quantity acquired by the ADC at the same time, namely the number of the multi-stage data calculation processing unit is the same as the data quantity acquired by the ADC at the same time, for example, 8 data acquired by the ADC at the same time, the multi-stage data calculation processing unit is provided with 8 stages and respectively processes each data bit; the multi-stage data calculation processing unit outputs high level or low level after processing the relevant bits of the data.
The current ADC can realize the simultaneous processing of a plurality of data points, and can simultaneously process 40 data points at most;
in the following, the embodiment that the ADC outputs 8 data points at the same time is taken, and the ADC can operate in a single-channel mode and a dual-channel mode;
the order in which data points are acquired in single channel mode is 12345678;
in the dual channel mode, the order in which channel 1 acquires data points is 1234; lane 2 acquires data points in order 5678;
if the trigger level value needs to be calculated, the relationship bit of the data point needs to be calculated, and the relationship bit when the data point is processed by adopting the pipeline is as follows:
it can be seen that the relationship bit of the data point of channel 1 is related to the data point itself and all data points before the data point, the relationship bit of channel 2 from the 1 st data point to the 4 th data point is related to the data point itself and one data point before the data point, but the relationship bit of channel 2 from the 5 th data point to the 8 th data point is related to the data point itself and the 5 th data point before the data point; for example, the 8 th data point of channel 1 is associated with each of the 1 st, 2 nd, 3 rd, 4 th, 5 th, 6 th, 7 th and 8 th data points, the 4 th data point of channel 2 is associated with each of the 1 st, 2 nd, 3 rd and 4 th data points, and the 8 th data point of channel 2 is associated with each of the 5 th, 6 th, 7 th and 8 th data points, so that the amount of calculation for processing data is 2 9 ；
Because each bit code is a 2-bit identifier, each channel data code is a trigger data identifier with 16 bits, wherein 8 times 2 in the operation process;
compressing the 16-bit trigger data identifier into an 8-bit trigger data identifier for output; specifically, only the high bit of the trigger data point code is taken during output, and the low bit of the trigger data point code is not taken, so that the 16-bit trigger data identifier can be compressed into an 8-bit trigger data identifier for output, and at the moment, the triggered bit width is the same as the number of points of the ADC;
for example, in the dual channel mode:
the trigger data is:
15_____14_____13_____12_____11_____10_____9_____8_____7_____6_____5_____4____ _3_____2_____1_____0
the trigger output data is: 8_____________7_____________6____________5___________4___________3___________ 2___________1
Single channel mode:
the data before triggering are: 4/3/2/1
The trigger data bits are: 87654321
The trigger data is:
15_____14_____13_____12_____11_____10_____9_____8_____7_____6_____5_____4____ _3_____2_____1_____0
the trigger output data is: 8_____________7_____________6____________5___________4___________3___________ 2___________ 1;
in this embodiment, 8 data points are used, and if 40 data points are used, the calculation scale for processing data can reach 2 according to the above relation bits 41 And the number of required digital comparators is too large, and if the FPGA adopts a parallel computing circuit with too large scale, the computing speed of the FPGA is influenced.
In order to reduce the number of computing circuits, namely reduce the using area of an FPGA and improve the transportation rate of the FPGA, the invention provides a method for preprocessing trigger data based on the FPGA, which preprocesses data of each bit, completes calculation by using a production line and reduces the calculation scale, and the specific method comprises the following steps:
step 1: reducing the reference level value, and directly comparing the data acquired by the ADC with the reference trigger level value;
in order to judge the false judgment of the rising edge and the falling edge of the waveform, the digital comparator is respectively provided with reference levels which comprise: high trigger level and low trigger level, and high trigger level and low trigger level all set up high hysteresis voltage VH and low hysteresis voltage VL from top to bottom, so, when handling ADC sample data at present, be equivalent to using 6 trigger level values: 6 hysteresis comparators are needed for processing by a high trigger level, a low trigger level, a high hysteresis voltage VH of the high trigger level, a low hysteresis voltage VL of the high trigger level, a high hysteresis voltage VH of the low trigger level and a low hysteresis voltage VL of the low trigger level;
in order to save the resources of the hysteresis comparator, the low hysteresis voltage VL at the low trigger level is also used as the low hysteresis voltage VL at the high trigger level, and the high hysteresis voltage VH at the high trigger level is also used as the high hysteresis voltage VH at the low trigger level, so that only 4 trigger level values exist: high trigger level, low trigger level, high hysteresis voltage VH and low hysteresis voltage VL, so only 4 hysteresis comparator processes are needed.
Referring to fig. 2, T2 and T3 are respectively a low trigger level and a high trigger level, T1 is a low hysteresis voltage VL common to the low trigger level and the high trigger level, and T4 is a high hysteresis voltage VH common to the low trigger level and the high trigger level;
after data acquired by the ADC enter a digital comparator, the data are directly compared with a set reference level value, if the data are greater than a high hysteresis voltage VH of a high trigger level, a level 1 can be directly assigned, and if the data are less than a low hysteresis voltage VL of a low trigger level, a level 0 can be directly assigned;
step 2: preprocessing the relevant bits of the trigger data, recoding, and dividing data which can obtain the determined position and data which can not obtain the determined position:
201: for the data which can obtain the determined position after being compared by a digital comparator, the highest bit code is 1;
for data points of the high hysteresis voltage VH larger than the high trigger level, marking as trigger high level, setting as level 1 and coding as 110;
recording a data point of a low hysteresis voltage VL which is smaller than the low trigger level as a trigger low level, setting the data point as a level 0 and coding the data point as 100;
for data of a high hysteresis voltage VH smaller than a high trigger level and a low hysteresis voltage VL larger than a low trigger level, the data having passed the high trigger level but not having a threshold of the low hysteresis voltage VL to the low trigger level, the low level needs to be maintained, defined as a flag 0, and encoded as 101;
for data of a low hysteresis voltage VL greater than a low trigger level and a high hysteresis voltage VH smaller than a high trigger level, and a threshold of the high hysteresis voltage VH, which passes the low trigger level but does not pass the high trigger level, a high level needs to be maintained, is defined as a flag 1, and is coded as 111;
example 1: referring to fig. 2, the first data and the second data are greater than the high hysteresis voltage VH of the high trigger level, and are encoded as 110; the third data and the fourth data have passed the high trigger level but have not reached the threshold of the low hysteresis voltage VL of the low trigger level, and are coded as 101; the thresholds of the high hysteresis voltage VH, for which the fifth data and the sixth data have passed the low trigger level but have not passed the too high trigger level, are coded as 111; the seventh data and the eighth data are less than the low hysteresis voltage VL of the low trigger level and are coded as 100;
202: for the data which can not obtain the determined position after being compared by the digital comparator, the level value can not be directly obtained, and the data needs to be preprocessed and encoded, wherein the encoding is as follows:
if the data point in a period has no over-high level or low level, defining that the level value of the data point is only related to the level value of the previous data point, and keeping the state of the previous period, then coding the level value as 000;
if the level of the data point in one period is too high, the level value of the data point is only related to the level value of the previous data point, the state of the previous period is maintained, and the code is 001;
if the level of the data point in a period is too low, defining that the level value of the data point is only related to the level value of the previous data point, keeping the state of the previous period and coding the level value into 010;
for a data point in a period, if an overhigh level and an overlow level occur, defining that the level value of the data point is only related to the level value of the previous data point, keeping the state of the previous period, and encoding to be 011;
example 2: taking the ADC to process 8 data simultaneously as an example, the data processed in the first cycle is 12345678, and the data processed in the second cycle is 910111213141516; for step 201, the first data 9 of the second cycle is related to the last data 8 of the first cycle, the last data 8 of the first cycle is related to the previous data 7, and so on, the second data 2 of the first cycle is related to the previous data 1.
Example 3: first, calculating a first bit data "1", if the first bit data "1" can obtain a determined position, the highest bit of the data is coded as 1, and according to step 201, it can be known that, for the data that can obtain the determined position, first, whether the first data "1" is greater than a high hysteresis voltage VH of a high trigger level or less than a low hysteresis voltage VL of a low trigger level is determined, if the first data "1" is greater than the high hysteresis voltage VH of the high trigger level, the first data "1" is a high level, and if the first data "1" is less than the low hysteresis voltage VL of the low trigger level, the first data "1" is a low level; then the subsequent data "2", "3", "4", "5", "6", "7" and "8" are all related to the level of the previous data after being encoded in step 201;
when the first data "1" is at high level, the subsequent data "2", "3", "4", "5", "6", "7" and "8" are not at low hysteresis voltage VL less than the low trigger level, then all are high level, and only when the later data has low hysteresis voltage VL less than the low trigger level, the change occurs through the trigger level again, for example, the fifth data "5" appears to have a low hysteresis voltage VL less than the low trigger level, the data "2", "3", "4" are high levels maintained as the data "1", however, when the sixth data "6" passes the trigger level again, since the fifth data "5" appears to have a low hysteresis voltage VL less than the low trigger level, so the sixth data "6" becomes low level and the data "7", "8" also follow to low level;
when the first data is at low level, the data "2", "3", "4", "5", "6", "7" and "8" following the subsequent data are all at low level as long as the high hysteresis voltage VH which is excessively larger than the high trigger level does not appear, and only when the data "2", "3", "4", "5", "6", "7" and "8" following the subsequent data appear to be at high hysteresis voltage VH which is excessively larger than the high trigger level, the data are changed again through the trigger level; for example, if the fifth data "5" has a high hysteresis voltage VH that is too large for a high trigger level, the data "2", "3", "4" are low levels that remain the same as the data "1", but when the sixth data "6" has passed the trigger level again, the sixth data "6" becomes high level since the fifth data "5" has a high hysteresis voltage VH that is too large for a high trigger level, and the data "7", "8" also follow to become high level;
if the first bit data "1" cannot obtain the specified position, the level value cannot be known, and step 3 is performed on the data at which the specified position cannot be obtained.
And step 3: 2-bit encoding the position of the input waveform;
when the data value is smaller than the low hysteresis voltage VL of the low trigger level, the code is set to 00, and is defined as level 0, that is, the trigger level is the low level, specifically, referring to fig. 2, T1 is the low hysteresis voltage VL of the low trigger level, and when the data value is smaller than the trigger level value corresponding to T1, that is, when the sampled data value is below T1, all the codes are 00;
when the data value is greater than the high hysteresis voltage VH of the high trigger level, the code is set to 10, and is defined as level 1, that is, the trigger level is the high level, specifically, referring to fig. 2, T4 is the high hysteresis voltage VH of the high trigger level, and when the data value is greater than the high hysteresis voltage VH of the high trigger level, that is, when the sampled data value is above T4, all the codes are 10;
when the data value is greater than the high hysteresis voltage VH of the low trigger level and less than the high trigger level, the code is 11, and the data value is defined as mark 1, namely the threshold of the high hysteresis voltage VH which has passed the low trigger level but has not passed the high trigger level needs to be kept at the high level; specifically, T2 is a low trigger level value, and T4 is a high hysteresis voltage VH of a high trigger level, and when the data value is greater than T2 and smaller than T4, all codes are 11;
when the data value is less than the high trigger level and greater than the low hysteresis voltage VL of the low trigger level, the code is 01, and the data value is defined as a flag 0, that is, the high trigger level has been passed, but the threshold of the low hysteresis voltage VL to the low trigger level does not exist, and the low level needs to be maintained; specifically, T3 is a high trigger level value, and T1 is a low hysteresis voltage VL of a low trigger level, and when the data value is less than T3 and greater than T1, all codes are 01;
and 4, step 4: comparing and calculating the three-bit code in the step 2 with the two-bit code in the step 3 to obtain two-bit level output; the calculation process is as follows:
the difference value table for comparing and calculating the three-bit code and the two-bit code is as follows:
finally, each data is calculated to be 5-bit input and 2-bit output, and the calculation amount is 2 5 Even if 40 pieces of data are counted, the calculation scale is 2 5 ×40＝5×2 8 And 2 are 41 Compared with the calculation scale, the calculation amount is reduced by 2 30 To 2 31 。
In an embodiment, referring to fig. 3, a T1 square wave-T4 square wave is a square wave pattern in the prior art, and data points near the trigger of the ADC when acquiring a high trigger level (T3), a low trigger level (T2), a high hysteresis voltage VH (T4), and a low hysteresis voltage VL (T1) have a certain data jitter, so that the rising edge of the compared square wave and the falling edge of the square wave have noise, and the T1 square wave-T4 square wave has jitter; for a low trigger level (T2), the level of the first data point near the low trigger level (T2) is changed by the encoding, as can be seen from the T2' square wave in the figure, when the first data point (a) near the low trigger level (T2) is acquired, the first data point is changed from low level to high level, and the later data point (B, C) is always high level as long as the condition that the later data point is not higher than the high hysteresis voltage VH (T4) is not existed, the level change is not allowed to occur by the recoding of the invention; when the voltage is higher than the high hysteresis voltage VH (T4), data (D) near the low trigger level (T2) are collected again to change from high level to low level, and as long as the data point in the future is not less than the low hysteresis voltage VL (T1), the data point (E, F) is not allowed to change in level, and it can be seen in the figure that the T2 'square wave is a smooth square wave without jitter compared with the T2 square wave, the T2 square wave is jittered at the data point B, C, E, F, and the T2' square wave is not jittered at the data point B, C, E, F; for the high trigger level (T3), the processing manner of the T3' square wave in the figure is the same as that of the low trigger level (T2), and is not described herein again;
for easy understanding, referring to fig. 4, if 40 data points are collected by the high-speed ADC at the same time, the jitter will be more severe, and even more noise will appear as shown in the figure, and the smooth square wave without jitter, such as the T2 'square wave and the T3' square wave shown in the figure N, can still be obtained through the processing of the present invention, so that the jitter is effectively eliminated.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the embodiments and/or modifications of the invention can be made, and equivalents and modifications of some features of the invention can be made without departing from the spirit and scope of the invention.
Claims (9)
1. A digital circuit for preprocessing trigger data based on an FPGA, comprising: ADC, digital comparison module, the ADC output couples digital comparison module, and digital comparison module includes a plurality of digital comparator, its characterized in that: the triggering efficiency is improved by preprocessing the data points which are output by the digital comparator and cannot obtain the level value;
the digital comparator is internally provided with a reference level value: a high trigger level, a low trigger level, a high hysteresis voltage VH and a low hysteresis voltage VL; and the number of the first and second electrodes,
the low hysteresis voltage VL is used as a low hysteresis voltage VL which is common to the low trigger level and the high trigger level, and the high hysteresis voltage VH is used as a high hysteresis voltage VH which is common to the low trigger level and the high trigger level;
the digital circuit also comprises a multi-stage data calculation processing unit, and the number of the multi-stage data calculation processing unit is the same as the data volume acquired by the ADC at the same time;
the multi-stage data calculation processing unit outputs high level or low level after processing the relevant bit of the data.
2. The digital circuit for preprocessing trigger data based on the FPGA as recited in claim 1, wherein: after the data is compared with the reference level value in the digital comparator, the directly obtained data of the high level or the low level value is directly output;
and uniformly outputting the data which cannot directly obtain the level value to a multi-stage data calculation processing unit for preprocessing.
3. A method for preprocessing trigger data based on FPGA is characterized in that: reducing 6 trigger level values to 4 trigger level values by adopting a pipeline calculation method, recoding the preprocessed data points, and reducing the calculation scale;
the method comprises the following specific steps:
step 1: reducing the reference level value, and directly comparing the data acquired by the ADC with the reference trigger level value;
step 2: preprocessing the relevant bits of the trigger data, recoding, and dividing data which can obtain the determined position and data which can not obtain the determined position;
and step 3: 2-bit encoding the position of the input waveform;
and 4, step 4: and (4) comparing the three-bit code in the step (2) with the two-bit code in the step (3) to obtain two-bit level output.
4. The FPGA-based method of preprocessing trigger data of claim 3, wherein: in step 1, the low hysteresis voltage VL at the low trigger level is also used as the low hysteresis voltage VL at the high trigger level, the high hysteresis voltage VH at the high trigger level is also used as the high hysteresis voltage VH at the low trigger level, and the high hysteresis voltage VH at the low trigger level and the low hysteresis voltage VL at the high trigger level are removed.
5. The FPGA-based method of preprocessing trigger data of claim 3, wherein: in step 1, after data acquired by the ADC enters the digital comparator, the data is first directly compared with a set reference level value, and if the data is greater than the high hysteresis voltage VH of the high trigger level, the data may be directly assigned to level 1, and if the data is less than the low hysteresis voltage VL of the low trigger level, the data may be directly assigned to level 0.
6. The method for preprocessing trigger data based on FPGA according to claim 3, wherein the step 2 comprises the steps of: for the data which can obtain the determined position after being compared by a digital comparator, the highest bit code is 1;
for the data point of the high hysteresis voltage VH which is greater than the high trigger level, marking as the trigger high level, setting as level 1 and coding as 110;
recording a data point of a low hysteresis voltage VL which is smaller than the low trigger level as a trigger low level, setting the data point as a level 0 and coding the data point as 100;
for data of a high hysteresis voltage VH smaller than a high trigger level and a low hysteresis voltage VL larger than a low trigger level, the data passes through the high trigger level but does not reach the threshold of the low hysteresis voltage VL of the low trigger level, the low level needs to be maintained, which is defined as a mark 0 and is coded as 101;
for data with a low hysteresis voltage VL greater than the low trigger level and a high hysteresis voltage VH less than the high trigger level, and the threshold of the high hysteresis voltage VH where the low trigger level has been passed but the high trigger level has not been passed, it is necessary to maintain the high level, defined as flag 1, and encoded as 111.
7. The FPGA-based method of preprocessing trigger data of claim 3, wherein: the step 2 further comprises 202: for the data which can not obtain the determined position after being compared by the digital comparator, the level value can not be directly obtained, and the data are preprocessed and coded, wherein the coding is as follows:
if the data point in a period has no over-high level or low level, defining that the level value of the data point is only related to the level value of the previous data point, and keeping the state of the previous period, then coding the level value as 000;
if the data point in a period has an excessively high level, defining that the level value of the data point is only related to the level value of the previous data point, keeping the state of the previous period and encoding the data point to be 001;
if the level of the data point in a period is too low, defining that the level value of the data point is only related to the level value of the previous data point, keeping the state of the previous period and coding the level value into 010;
for a data point in a period, both too high and too low, the level value defining the data point is only related to the level value of the previous data point, and the state of the previous period is maintained, and the code is 011.
8. The FPGA-based method of preprocessing trigger data of claim 3, wherein: in the step 3:
when the data is less than the low hysteresis voltage VL of the low trigger level, the code is set to 00 and defined as level 0;
when the data is larger than a high hysteresis voltage VH of a high trigger level, the code is set as 10 and defined as a level 1;
when the data passes through the threshold of the high hysteresis voltage VH of the low trigger level but does not have the excessively high trigger level, the high level needs to be kept, and the data is all coded as 11;
when the data has passed the high trigger level but there is no threshold for the low hysteresis voltage VL to the low trigger level, it needs to remain low, all encoded as 01.
9. The FPGA-based method of preprocessing trigger data of claim 3, wherein: in the step 4: the difference value table for comparing and calculating the three-bit code and the two-bit code is as follows:
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