CN114928365A - Method and device for signal processing - Google Patents
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Abstract
The application provides a method and a device for signal processing, and relates to the technical field of communication. The method comprises the following steps: the method includes the steps of performing down-conversion on an obtained first mixing digital signal by using a local oscillator signal of a first frequency to obtain a first real part component and a first imaginary part component, performing low-pass filtering on the first real part component and the first imaginary part component respectively to obtain a real part component of a digital signal of a third frequency and an imaginary part component of the digital signal of the third frequency, and obtaining a digital signal corresponding to the first frequency according to the real part component of the digital signal of the third frequency and the imaginary part component of the digital signal of the third frequency. Based on similar processing, a digital signal corresponding to the second frequency can be obtained. By adopting the frequency selection in the software, the dynamic configuration can be realized, the applicable scenes are wider, and the problem that two groups of fixed hardware frequency selection networks are required to be respectively designed for the digital signal with the first frequency and the digital signal with the second frequency is avoided, so that the cost of hardware devices is saved.
Description
Technical Field
The present application belongs to the field of communications technologies, and in particular, to a method and an apparatus for signal processing.
Background
In the current communication mode, multi-frequency point communication is adopted, namely the same data is transmitted under different frequency points, when interference exists, although the data under one frequency point is easy to cause communication abnormity due to interference, the data under the other frequency point can be normally communicated without interference, and therefore the multi-frequency point communication is more reliable than the single frequency point communication. For the multi-frequency point communication mode, signals of different frequency points correspond to different groups of hardware devices, so that a receiving end can respectively complete the processing process of the signals of the received multi-frequency point signals on a plurality of groups of hardware devices. Although the receiving end physically isolates the signals of each frequency point in the multi-frequency-point signals through different sets of hardware devices, the defects are that the number of required hardware device sets is increased, the cost is increased, and particularly, the more frequency points, the more hardware device sets are required, and the cost is also higher.
Disclosure of Invention
The application provides a method and a device for signal processing, which can reduce the cost of hardware devices.
In order to achieve the above object, in a first aspect, there is provided a method for signal processing, which is applied to a first device and includes:
a first mixed digital signal is obtained, the first mixed digital signal including a digital signal at a first frequency and a digital signal at a second frequency.
The first mixing digital signal is down-converted according to the local oscillator signal of the first frequency to obtain a first real component and a first imaginary component, the first real component includes a real component of the digital signal of the third frequency corresponding to the digital signal of the first frequency and a real component of the digital signal of the fourth frequency corresponding to the digital signal of the second frequency, and the first imaginary component includes an imaginary component of the digital signal of the third frequency and an imaginary component of the digital signal of the fourth frequency.
And performing low-pass filtering processing on the first real part component to obtain a real part component of the digital signal of the third frequency.
And carrying out low-pass filtering processing on the first imaginary component to obtain the imaginary component of the digital signal of the third frequency.
And performing down-conversion processing on the first mixing digital signal according to a local oscillator signal of a second frequency to obtain a second real part component and a second imaginary part component, wherein the second real part component comprises a real part component of a digital signal of a fifth frequency corresponding to the digital signal of the first frequency and a real part component of a digital signal of a sixth frequency corresponding to the digital signal of the second frequency, and the second imaginary part component comprises an imaginary part component of the digital signal of the fifth frequency and an imaginary part component of the digital signal of the sixth frequency.
And performing low-pass filtering processing on the second real part component to obtain a real part component of the digital signal of the sixth frequency.
And performing low-pass filtering processing on the second imaginary component to obtain an imaginary component of the digital signal of the sixth frequency.
Optionally, the passband cutoff frequency of the low pass filter corresponding to the low pass filtering process is half of the interval between the first frequency and the second frequency.
Optionally, obtaining a first mixed digital signal comprises:
and receiving the multi-frequency-point analog signal from the second equipment, and performing down-conversion and analog-digital conversion processing on the multi-frequency-point analog signal to obtain a second mixing digital signal.
And carrying out digital DC removal and digital automatic gain control processing on the second mixing digital signal to obtain a first mixing digital signal.
Optionally, the first device is a Field-Programmable Gate Array (FPGA).
Optionally, the third frequency is zero.
Optionally, the sixth frequency is zero.
Optionally, the multi-Frequency-point analog signal received from the second device is a Continuous Phase Frequency Shift Keying (CPFSK) modulated signal of the multi-Frequency point.
In a second aspect, an embodiment of the present application provides an apparatus for signal processing, including:
the acquisition unit is used for acquiring a first mixing digital signal, and the first mixing digital signal comprises a digital signal of a first frequency and a digital signal of a second frequency.
The processing unit is configured to perform down-conversion processing on the first mixing digital signal according to the local oscillator signal of the first frequency to obtain a first real component and a first imaginary component, where the first real component includes a real component of a digital signal of a third frequency corresponding to the digital signal of the first frequency and a real component of a digital signal of a fourth frequency corresponding to the digital signal of the second frequency, and the first imaginary component includes an imaginary component of the digital signal of the third frequency and an imaginary component of the digital signal of the fourth frequency.
The processing unit is further configured to perform low-pass filtering processing on the first real component to obtain a real component of the digital signal of a third frequency.
The processing unit is further configured to perform low-pass filtering processing on the first imaginary component to obtain an imaginary component of the digital signal of the third frequency.
The processing unit is further configured to perform a down-conversion process on the first mixing digital signal according to the local oscillator signal of the second frequency to obtain a second real component and a second imaginary component, where the second real component includes a real component of a digital signal of a fifth frequency corresponding to the digital signal of the first frequency and a real component of a digital signal of a sixth frequency corresponding to the digital signal of the second frequency, and the second imaginary component includes an imaginary component of the digital signal of the fifth frequency and an imaginary component of the digital signal of the sixth frequency.
The processing unit is further configured to perform low-pass filtering processing on the second real component to obtain a real component of the digital signal at the sixth frequency.
The processing unit is further configured to perform low-pass filtering processing on the second imaginary component to obtain an imaginary component of the digital signal at the sixth frequency.
In a third aspect, an embodiment of the present application provides an apparatus for signal processing, including a processor, coupled to a memory, where the processor is configured to execute a computer program or instructions stored in the memory to implement the method of the first aspect or any implementation manner of the first aspect.
In a fourth aspect, an embodiment of the present application provides a computer storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the method of the first aspect or any implementation manner of the first aspect.
Compared with the prior art, the embodiment of the application has the advantages that: according to the method, the first device carries out down-conversion on the obtained first mixing digital signal by using the local oscillator signal of the first frequency to obtain the first real part component and the first imaginary part component, carries out low-pass filtering on the first real part component to obtain the real part component of the digital signal of the third frequency, and carries out low-pass filtering on the first imaginary part component to obtain the imaginary part component of the digital signal of the third frequency. Based on similar processing, a digital signal corresponding to the second frequency can be obtained. Therefore, the digital signal corresponding to the first frequency and the digital signal corresponding to the second frequency can be separated, and the need of respectively designing two groups of fixed hardware frequency selection networks for the digital signal of the first frequency and the digital signal of the second frequency is avoided, so that the cost of hardware devices can be saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic diagram of a signal processing process according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a method for signal processing according to an embodiment of the present application;
fig. 3 is a schematic diagram of another signal processing process provided in an embodiment of the present application;
fig. 4 is a schematic block diagram of an apparatus for signal processing according to an embodiment of the present disclosure;
fig. 5 is a schematic block diagram of another apparatus for signal processing according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be described in detail below with reference to the embodiments of the present application.
It should be understood that the modes, situations, categories and divisions of the embodiments of the present application are for convenience only and do not limit the present application, and the features of the various modes, categories, situations and embodiments can be combined without contradiction.
It should also be understood that "first", "second", "third", "fourth", "fifth" and "sixth" in the embodiments of the present application are only for distinguishing and do not limit the present application in any way. It should also be understood that, in the embodiments of the present application, the size of the serial number in each process does not mean the execution sequence of the steps, and the execution sequence of the steps is determined by the internal logic thereof, and does not form any limitation on the execution process of the embodiments of the present application.
For the multi-frequency point communication mode, conventionally, a process of processing received multi-frequency point signals on multiple sets of hardware devices is respectively adopted, and although a receiving end physically isolates the signals of each frequency point in the multi-frequency point signals through different sets of hardware devices, the defects are that the number of sets of required hardware devices is increased, and the cost is increased. For example, the multi-frequency point signal in the multi-frequency point communication system is a modulated signal in the CPFSK modulation system.
In the following description, taking signals at two frequency points as an example, as shown in fig. 1, a receiving end needs two sets of hardware devices, where one set of hardware devices includes: an antenna 1, a down Converter 1, a filter 1, an Analog to Digital Converter (ADC) 1, and a Low-Voltage Differential Signaling (LVDS) 1. Another set of hardware devices includes: antenna 2, down-conversion 2, filter 2, ADC2, and LVDS 2.
The specific treatment process comprises the following steps: the antenna 1 receives signals of two frequency points, and the signals of two frequency points include the signal of frequency point 1 and the signal of frequency point 2, and down 1 module of down-conversion carries out down conversion to the signal of two frequency points and handles, obtains the intermediate frequency mixing analog signal of two frequency points, with intermediate frequency mixing analog signal input filter 1, the intermediate frequency analog signal that filter 1 output frequency point 1 corresponds, then the ADC1 module samples the intermediate frequency analog signal that frequency point 1 corresponds and obtains the digital signal that frequency point 1 corresponds. Subsequently, the Digital signal corresponding to the frequency point 1 is accessed into the FPGA through the LVDS1 interface, and Digital dc removal and Digital automatic gain control processing and Digital Down Conversion (DDC) processing are performed in the FPGA.
The antenna 2 receives the signals of the two frequency points, the down-conversion 2 module performs down-conversion processing on the signals of the two frequency points to obtain intermediate frequency mixing analog signals of the two frequency points, the intermediate frequency mixing analog signals are input into the filter 2, the filter 2 outputs the intermediate frequency analog signals corresponding to the frequency points 2, and then the ADC2 module samples the intermediate frequency analog signals corresponding to the frequency points 2 to obtain digital signals corresponding to the frequency points 2. And then, the digital signal corresponding to the frequency point 2 is accessed into the FPGA through an LVDS2 interface, and digital de-DC and digital automatic gain control processing and DDC processing are carried out in the FPGA.
For example, the signals of the two frequency points are CPFSK modulation signals, the signal of the frequency point 1 is a CPFSK modulation signal of the frequency point 1, and the signal of the frequency point 2 is a CPFSK modulation signal of the frequency point 2.
The design physically isolates the signals of the two frequency points on a hardware device without mutual interference. But the disadvantage is that two fixed hardware frequency-selecting networks are needed, and the cost of the required hardware devices is increased. In addition, digital de-direct current and digital automatic gain control processing are respectively carried out on the digital signals corresponding to the two frequency points in the FPGA, so that the calculation flow is complex.
Based on the above problem, the present application provides a method and an apparatus for signal processing, where a first device performs down-conversion on an acquired first mixing digital signal by using a local oscillator signal of a first frequency to obtain a first real component and a first imaginary component, performs low-pass filtering on the first real component to obtain a real component of a digital signal of a third frequency, and performs low-pass filtering on the first imaginary component to obtain an imaginary component of the digital signal of the third frequency, and because the third frequency is a frequency after the down-conversion of the first frequency, a digital signal corresponding to the first frequency can be obtained according to the real component of the digital signal of the third frequency and the imaginary component of the digital signal of the third frequency. Based on similar processing, a digital signal corresponding to the second frequency can be obtained. Therefore, the digital signal corresponding to the first frequency and the digital signal corresponding to the second frequency can be separated, and the need of respectively designing two fixed hardware frequency selection networks for the digital signal of the first frequency and the digital signal of the second frequency is avoided, so that the cost of hardware devices can be saved.
The technical means of the present application will be described in detail with specific examples.
Fig. 2 is a schematic diagram of a method for signal processing according to an embodiment of the present application, and as shown in fig. 2, the method may be applied to a first device, and the method 200 may include the following steps:
s210, the first device obtains a first mixed digital signal, where the first mixed digital signal includes a digital signal of a first frequency and a digital signal of a second frequency.
Optionally, S210 includes: the first device receives the multi-frequency point analog signal from the second device, performs down-conversion and analog-digital conversion processing on the multi-frequency point analog signal to obtain a second mixing digital signal, and performs digital de-DC and digital automatic gain control processing on the second mixing digital signal to obtain a first mixing digital signal.
Optionally, the first device is a device comprising an FPGA.
Optionally, the multi-frequency point analog signal is a multi-frequency point CPFSK modulated signal.
S220, the first device performs down-conversion processing on the first mixing digital signal according to the local oscillator signal of the first frequency to obtain a first real component and a first imaginary component, where the first real component includes a real component of a digital signal of a third frequency corresponding to the digital signal of the first frequency and a real component of a digital signal of a fourth frequency corresponding to the digital signal of the second frequency, and the first imaginary component includes an imaginary component of the digital signal of the third frequency and an imaginary component of the digital signal of the fourth frequency.
Optionally, S220 includes: the local oscillator signal of the first frequency is a sine signal and a cosine signal which are generated according to a first Direct Digital Synthesizer (DDS) and have the first frequency.
Optionally, the frequency obtained by performing down-conversion processing on the first frequency is a third frequency.
Optionally, the first real component further comprises a real component of a frequency-2 multiplied signal corresponding to the first mixed digital signal.
Optionally, the first imaginary component further comprises an imaginary component of a frequency-2 multiplied signal corresponding to the first mixed digital signal.
Alternatively, the real component In the embodiment of the present application may be replaced with an In-phase (I) component. For example, the first real component may be replaced with a first homogeneous I component; for another example, the real component of the digital signal of the third frequency may be replaced with the in-phase I component of the digital signal of the third frequency.
Alternatively, the imaginary component in the embodiment of the present application may be replaced with a Quadrature (Q) component. For example, the first imaginary component may be replaced with a first quadrature Q component; for another example, the imaginary component of the digital signal of the third frequency may be replaced with the quadrature Q component of the digital signal of the third frequency.
Alternatively, the third frequency may be zero.
And S230, the first device performs low-pass filtering processing on the first real component to obtain a real component of the digital signal of the third frequency.
Alternatively, in S230, the low-pass filtering process filters out the real component of the digital signal of the fourth frequency, and retains the real component of the digital signal of the third frequency.
Optionally, in the case that the first real component further includes a real component of a frequency-2 multiplication signal corresponding to the first mixed digital signal, the real component of the frequency-2 multiplication signal corresponding to the first mixed digital signal and the real component of the digital signal of the fourth frequency are filtered out in S230, and the real component of the digital signal of the third frequency is retained.
Alternatively, the passband cutoff frequency of the low pass filter corresponding to the low pass filtering process in S230 is greater than 0 and smaller than the first frequency and the second frequency interval.
Alternatively, the passband cutoff frequency of the low pass filter corresponding to the low pass filtering process in S230 is one-half of the first frequency and the second frequency interval.
S240, the first device performs low-pass filtering on the first imaginary component to obtain an imaginary component of the digital signal of the third frequency.
Alternatively, in S240, the low-pass filtering process filters out the imaginary component of the digital signal of the fourth frequency, and retains the imaginary component of the digital signal of the third frequency.
Optionally, in the case that the first imaginary component further includes an imaginary component of the frequency-2 multiplication signal corresponding to the first mixed digital signal, the imaginary component of the frequency-2 multiplication signal corresponding to the first mixed digital signal and the imaginary component of the digital signal of the fourth frequency are filtered out in S240, and the imaginary component of the digital signal of the third frequency is retained.
Alternatively, the passband cutoff frequency of the low pass filter corresponding to the low pass filtering process in S240 is greater than 0 and smaller than the first frequency and the second frequency interval.
Alternatively, the passband cutoff frequency of the low pass filter corresponding to the low pass filtering process in S240 is one-half of the first frequency and the second frequency interval.
It should be noted that the execution sequence of S230 and S240 is not limited at all, and S230 may be performed before or after S240 or simultaneously.
Optionally, after S230 and S240, the first device may obtain the digital signal corresponding to the first frequency according to the real component of the digital signal of the third frequency and the imaginary component of the digital signal of the third frequency, where the digital signal of the third frequency is a digital signal after down-conversion of the digital signal of the first frequency.
S250, the first device performs a down-conversion process on the first mixing digital signal according to the local oscillator signal of the second frequency to obtain a second real component and a second imaginary component, where the second real component includes a real component of a digital signal of a fifth frequency corresponding to the digital signal of the first frequency and a real component of a digital signal of a sixth frequency corresponding to the digital signal of the second frequency, and the second imaginary component includes an imaginary component of the digital signal of the fifth frequency and an imaginary component of the digital signal of the sixth frequency.
Optionally, S250 includes: the local oscillator signal of the second frequency is a sine signal and a cosine signal which are generated according to the second DDS and have the second frequency.
Optionally, the frequency obtained by performing the down-conversion processing on the second frequency is a sixth frequency.
Optionally, the second real component further comprises a real component of a frequency-2 multiplied signal corresponding to the first mixed digital signal.
Optionally, the second imaginary component further comprises an imaginary component of the frequency-2 multiplied signal corresponding to the first mixed digital signal.
Alternatively, the real component in the embodiment of the present application may be replaced with an I component. For example, the second real component may be replaced with a second in-phase I component; for another example, the real component of the digital signal of the sixth frequency may be replaced with the in-phase I component of the digital signal of the sixth frequency.
Alternatively, the imaginary component in the embodiment of the present application may be replaced with the Q component. For example, the second imaginary component may be replaced with a second quadrature Q component; for another example, the imaginary component of the digital signal of the sixth frequency may be replaced with the quadrature Q component of the digital signal of the sixth frequency.
Alternatively, the sixth frequency may be zero.
And S260, the first device performs low-pass filtering processing on the second real part component to obtain a real part component of the digital signal of the sixth frequency.
Alternatively, in S260, the low-pass filtering process filters out the real component of the digital signal of the fifth frequency, and retains the real component of the digital signal of the sixth frequency.
Optionally, in the case that the second real component further includes a real component of the frequency-2 multiplication signal corresponding to the first mixed digital signal, the real component of the frequency-2 multiplication signal corresponding to the first mixed digital signal and the real component of the digital signal of the fifth frequency are filtered out in S260, and the real component of the digital signal of the sixth frequency is retained.
Optionally, the passband cutoff frequency of the low pass filter corresponding to the low pass filtering process in S260 is greater than 0 and smaller than the first frequency and the second frequency interval.
Optionally, the passband cutoff frequency of the low pass filter corresponding to the low pass filtering process in S260 is one half of the first frequency and the second frequency interval.
S270, the first device performs low-pass filtering on the second imaginary component to obtain an imaginary component of the digital signal at the sixth frequency.
Alternatively, in S270, the low-pass filtering process filters out the imaginary component of the digital signal at the fifth frequency, and retains the imaginary component of the digital signal at the sixth frequency.
Optionally, in the case that the second imaginary component further includes an imaginary component of the frequency-2-multiplied signal corresponding to the first mixed digital signal, the imaginary component of the frequency-2-multiplied signal corresponding to the first mixed digital signal and the imaginary component of the digital signal of the fifth frequency are filtered out in S270, and the imaginary component of the digital signal of the sixth frequency is retained.
Alternatively, the passband cutoff frequency of the low pass filter corresponding to the low pass filtering process in S270 is greater than 0 and smaller than the first frequency and the second frequency interval.
Optionally, the passband cutoff frequency of the low pass filter corresponding to the low pass filtering process in S270 is half of the interval between the first frequency and the second frequency.
It should be noted that the execution sequence of S260 and S270 is not limited at all, and S260 may be performed before or after S270 or simultaneously.
Optionally, after S260 and S270, the first device may obtain a digital signal corresponding to the second frequency according to the real component of the digital signal of the sixth frequency and the imaginary component of the digital signal of the sixth frequency, where the digital signal of the sixth frequency is the digital signal after the digital signal of the second frequency is down-converted.
It should be noted that, there is no requirement for any sequence between any step of S220 to S240 and any step of S250 to S270, for example, S220 may be executed before or after S250 or simultaneously; for another example, S230 may be performed before or after or simultaneously with S260; as another example, S240 may be performed before or after or simultaneously with S270.
The above steps implement a separation process of two frequency point signals, and the separation process is similar to the method 200 in the case of more than two frequency point signals, and in order to avoid redundancy, detailed description is omitted in the embodiments of the present application.
For better understanding of the scheme of the present application, fig. 3 gives a specific description by taking a separation implementation manner of CPFSK modulated signals of two frequency points as an example. The embodiment is applied to a CPFSK communication mode, and the separation of CPFSK modulation signals of each frequency point is realized when multi-frequency point communication is adopted. The first device comprises an FPGA as shown in figure 3 or may comprise an FPGA, an antenna, a down-conversion and an ADC as shown in figure 3. As shown in fig. 3, the antenna receives a multi-frequency-point CPFSK modulated signal, where the multi-frequency-point CPFSK modulated signal includes a CPFSK modulated signal at frequency point 1 and a CPFSK modulated signal at frequency point 2. The down-conversion module performs down-conversion processing on the CPFSK modulation signal of the frequency point 1 and the CPFSK modulation signal of the frequency point 2 to obtain mixing analog signals corresponding to the frequency point 1 and the frequency point 2, and outputs a mixing digital signal through the ADC.
For example, the mixed digital signal output by the ADC of fig. 3 may be the second mixed digital signal of method 200. The second mixing digital signal comprises a CPFSK modulation signal at a frequency point 1 and a digital signal obtained by performing down-conversion and ADC (analog-to-digital converter) sampling on the CPFSK modulation signal at a frequency point 2.
For example, in actual communication, the effective bandwidths of the CPFSK modulated signal at frequency point 1 and the CPFSK modulated signal at frequency point 2 are both 64Khz, and the two signals are separated by 2 Mhz. The sampling rate of the ADC is designed to be 70Mbps, and according to the Nyquist sampling theorem, the effective bandwidth of ADC sampling is half of the sampling rate of the ADC, so that the actual effective bandwidth is 35 Mhz. The ADC designed in this way can completely collect the signals of the frequency point 1 and the signals of the frequency point 2 after the multi-frequency point signals are subjected to down-conversion sampling processing. And transmitting the mixed digital signal sampled and output by the ADC to the FPGA through the LVDS. And carrying out digital DC removal and digital automatic gain control processing in the FPGA, wherein the processed signal is a mixing digital signal 1 comprising a frequency point 1 and a frequency point 2. The mixing digital signal 1 includes a digital signal corresponding to the frequency point 1 and a digital signal corresponding to the frequency point 2.
For example, the mixed digital signal 1 may be the first mixed digital signal in the method 200, the digital signal corresponding to the frequency point 1 is the digital signal of the first frequency in the method 200, and the digital signal corresponding to the frequency point 2 is the digital signal of the second frequency in the method 200.
Wherein, the frequency point is a number of a fixed frequency.
Specifically, as shown in fig. 3, in the digital dc-removing process, the mixing digital signals output by the ADCs are first split-processed, dc quantity statistics is performed on the mixing digital signals output by one of the ADCs to obtain a signal average value, and the mixing digital signals output by the other ADC are subtracted from the signal average value to remove dc components in the mixing digital signals output by the ADCs to obtain the mixing digital signals 3.
For example, the mixed digital signal 3 may be a signal obtained by performing digital dc-removal on the second mixed digital signal in the method 200.
Specifically, as shown in fig. 3, in the digital automatic gain control processing process, the mixing digital signal 3 is first split, power calculation is performed on one of the mixing digital signals 3, the power calculation outputs a result to the module value calculation module, factor calculation is performed after the module value calculation, an amplitude adjustment factor is obtained after the factor calculation, and truncation processing is performed to output the mixing digital signal 1 after the amplitude adjustment factor is divided by the mixing digital signal 3 of the other channel.
As shown in fig. 3, a local oscillation signal 1 of a digital signal frequency corresponding to a frequency point 1 is generated through a DDS, the local oscillation signal 1 is two orthogonal sine signals (sin) and cosine signals (cos), the cosine signal in the mixing digital signal 1 and the local oscillation signal 1 is multiplied to output an I-path component 1, and the sine signal in the mixing digital signal 1 and the local oscillation signal 1 is multiplied to output a Q-path component 1. The DDS and the low pass filtering may belong to the DDC.
For example, the local oscillation signal 1 is the local oscillation signal of the first frequency in the foregoing S220, the I-path component 1 is the first real component in the foregoing S220, and the I-path component 1 includes the real component of the digital signal of the third frequency corresponding to the digital signal of the first frequency and the real component of the digital signal of the fourth frequency corresponding to the digital signal of the second frequency. The Q-path component 1 is the first imaginary component in the foregoing S220, and the Q-path component 1 includes an imaginary component of a digital signal of a third frequency corresponding to the digital signal of the first frequency and an imaginary component of a digital signal of a fourth frequency corresponding to the digital signal of the second frequency.
As shown in fig. 3, the I path component 1 is processed by low-pass filtering to obtain a real component of the digital signal corresponding to the frequency point 1, and the Q path component 1 is processed by low-pass filtering to obtain an imaginary component of the digital signal corresponding to the frequency point 1.
For example, the low-pass filtering is the low-pass filtering in the aforementioned S230 and S240.
As shown in fig. 3, when the interval between the first frequency and the second frequency is 2Mhz, the passband cutoff frequency of the low-pass filter corresponding to the low-pass filtering process is 1 Mhz.
For example, the passband cutoff frequency of the low pass filter is one-half of the first frequency and the second frequency interval in the foregoing S230 and S240.
As shown in fig. 3, a local oscillation signal 2 of a digital signal frequency corresponding to a frequency point 2 is generated through a DDS, the local oscillation signal 2 is two orthogonal sine signals (sin) and cosine signals (cos), the mixing digital signal 2 and the cosine signal in the local oscillation signal 2 are multiplied to output an I-path component 2, and the mixing digital signal 2 and the sine signal in the local oscillation signal 2 are multiplied to output a Q-path component 2. The DDS and the low pass filtering may belong to the DDC.
For example, the local oscillation signal 2 is the local oscillation signal of the second frequency in the foregoing S250, the I path component 2 is the second real component in the foregoing S250, and the I path component 2 includes the real component of the digital signal of the fifth frequency corresponding to the digital signal of the first frequency and the real component of the digital signal of the sixth frequency corresponding to the digital signal of the second frequency. The Q-path component 2 is the second imaginary component in the aforementioned S250, and the Q-path component 2 includes the imaginary component of the digital signal of the fifth frequency corresponding to the digital signal of the first frequency and the imaginary component of the digital signal of the sixth frequency corresponding to the digital signal of the second frequency.
As shown in fig. 3, the I-path component 2 is processed by low-pass filtering to obtain a real component of the digital signal corresponding to the frequency point 2, and the Q-path component 2 is processed by low-pass filtering to obtain an imaginary component of the digital signal corresponding to the frequency point 2.
For example, the low-pass filtering is the low-pass filtering in the aforementioned S260 and S270.
As shown in fig. 3, when the interval between the first frequency and the second frequency is 2Mhz, the passband cutoff frequency of the low-pass filter corresponding to the low-pass filtering process is 1 Mhz.
For example, the passband cutoff frequency of the low pass filter is one-half of the passband cutoff frequency of the low pass filter in the aforementioned S260 and S270, the first frequency and the second frequency being separated.
In the above, fig. 3 completes the separation process of the digital signal corresponding to the frequency point 1 and the digital signal corresponding to the frequency point 2.
Compared with fig. 1, in fig. 3, only one digital dc removal and digital automatic gain control is needed to be performed in fig. 3, and two digital dc removal and two digital automatic gain controls need to be performed on signals of two frequency points in fig. 1, so that fig. 3 can avoid performing multiple digital dc removal and digital automatic gain control processes, thereby simplifying the calculation process and increasing the calculation speed.
Fig. 4 is a schematic structural diagram of an apparatus for signal processing according to an embodiment of the present application, and as shown in fig. 4, the apparatus according to the embodiment includes:
the obtaining unit 410 is configured to obtain a first mixed digital signal, where the first mixed digital signal includes a digital signal of a first frequency and a digital signal of a second frequency.
The processing unit 420 is configured to perform a down-conversion process on the first mixed digital signal according to the local oscillator signal of the first frequency to obtain a first real component and a first imaginary component, where the first real component includes a real component of a digital signal of a third frequency corresponding to the digital signal of the first frequency and a real component of a digital signal of a fourth frequency corresponding to the digital signal of the second frequency, and the first imaginary component includes an imaginary component of the digital signal of the third frequency and an imaginary component of the digital signal of the fourth frequency.
The processing unit 420 is further configured to perform low-pass filtering processing on the first real component to obtain a real component of the digital signal of the third frequency.
The processing unit 420 is further configured to perform low-pass filtering on the first imaginary component to obtain an imaginary component of the digital signal of the third frequency.
The processing unit 420 is further configured to perform down-conversion processing on the first mixed digital signal according to the local oscillator signal of the second frequency to obtain a second real component and a second imaginary component, where the second real component includes a real component of a digital signal of a fifth frequency corresponding to the digital signal of the first frequency and a real component of a digital signal of a sixth frequency corresponding to the digital signal of the second frequency, and the second imaginary component includes an imaginary component of the digital signal of the fifth frequency and an imaginary component of the digital signal of the sixth frequency.
The processing unit 420 is further configured to perform low-pass filtering processing on the second real component to obtain a real component of the digital signal at the sixth frequency.
The processing unit 420 is further configured to perform low-pass filtering processing on the second imaginary component to obtain an imaginary component of the digital signal at the sixth frequency.
The apparatus shown in fig. 4 may perform the functions of the first device or the FPGA in the above method embodiment, and for avoiding redundancy, the detailed description is omitted here.
It should be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional units and modules is only used for illustration, and in practical applications, the above function distribution may be performed by different functional units and modules as needed, that is, the internal structure of the apparatus may be divided into different functional units or modules to perform all or part of the above described functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
Based on the same inventive concept, fig. 5 is a schematic block diagram of another apparatus for signal processing provided in an embodiment of the present application, and the apparatus includes a processor, the processor is coupled with a memory, and the processor is configured to execute a computer program or instructions stored in the memory to implement the method of the first aspect or any implementation manner of the first aspect.
Based on the same inventive concept, embodiments of the present application provide a computer storage medium, on which a computer program is stored, and the computer program is executed by a processor to implement the method of the first aspect or any implementation manner of the first aspect.
The integrated units described above may be stored in one device if implemented in the form of software functional units and sold or used as separate products. Based on such understanding, all or part of the flow of the method of the embodiments described above can be implemented by instructing relevant hardware by a computer program, which can be stored in a chip of a computer, and when the computer program is executed by a processor, the steps of the method embodiments described above can be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable storage medium may include at least: any entity or device capable of carrying computer program code to a photographing apparatus/terminal apparatus, a recording medium, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signal, telecommunication signal, and software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In some jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and proprietary practices.
In the above embodiments, the description of each embodiment has its own emphasis, and reference may be made to the related description of other embodiments for parts that are not described or recited in any embodiment.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/device and method may be implemented in other ways. For example, the above-described apparatus/device embodiments are merely illustrative, and for example, the division of the modules or units is only one type of logical function division, and other division manners may exist in actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless otherwise specifically stated.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A method for signal processing, the method being applied to a first device, comprising:
acquiring a first mixing digital signal, wherein the first mixing digital signal comprises a digital signal of a first frequency and a digital signal of a second frequency;
performing down-conversion processing on the first mixing digital signal according to the local oscillator signal of the first frequency to obtain a first real component and a first imaginary component, where the first real component includes a real component of a digital signal of a third frequency corresponding to the digital signal of the first frequency and a real component of a digital signal of a fourth frequency corresponding to the digital signal of the second frequency, and the first imaginary component includes an imaginary component of the digital signal of the third frequency and an imaginary component of the digital signal of the fourth frequency;
performing low-pass filtering processing on the first real component to obtain a real component of the digital signal of the third frequency;
performing low-pass filtering processing on the first imaginary component to obtain an imaginary component of the digital signal of the third frequency;
performing down-conversion processing on the first mixing digital signal according to the local oscillator signal of the second frequency to obtain a second real component and a second imaginary component, where the second real component includes a real component of a digital signal of a fifth frequency corresponding to the digital signal of the first frequency and a real component of a digital signal of a sixth frequency corresponding to the digital signal of the second frequency, and the second imaginary component includes an imaginary component of the digital signal of the fifth frequency and an imaginary component of the digital signal of the sixth frequency;
performing low-pass filtering processing on the second real component to obtain a real component of the digital signal of the sixth frequency;
and performing low-pass filtering processing on the second imaginary component to obtain an imaginary component of the digital signal of the sixth frequency.
2. The method of claim 1, wherein the low pass filtering process corresponds to a low pass filter having a passband cutoff frequency that is one-half the first frequency and the second frequency separation.
3. The method of claim 1, wherein the obtaining a first mixed digital signal comprises:
receiving a multi-frequency point analog signal from a second device;
performing down-conversion processing and analog-digital conversion processing on the multi-frequency-point analog signal to obtain a second mixing digital signal;
and carrying out digital DC removal and digital automatic gain control processing on the second mixing digital signal to obtain the first mixing digital signal.
4. The method of claim 1, wherein the first device is a Field Programmable Gate Array (FPGA).
5. The method of any of claims 1 to 4, wherein the third frequency is zero.
6. The method of any of claims 1 to 4, wherein the sixth frequency is zero.
7. The method of any of claims 1-6, wherein the multi-frequency point analog signal is a multi-frequency point Continuous Phase Frequency Shift Keying (CPFSK) modulated signal.
8. An apparatus for signal processing, the apparatus comprising:
an acquisition unit configured to acquire a first mixed digital signal including a digital signal of a first frequency and a digital signal of a second frequency;
a processing unit, configured to perform down-conversion processing on the first mixed digital signal according to the local oscillator signal of the first frequency to obtain a first real component and a first imaginary component, where the first real component includes a real component of a digital signal of a third frequency corresponding to the digital signal of the first frequency and a real component of a digital signal of a fourth frequency corresponding to the digital signal of the second frequency, and the first imaginary component includes an imaginary component of the digital signal of the third frequency and an imaginary component of the digital signal of the fourth frequency;
the processing unit is further configured to perform low-pass filtering processing on the first real component to obtain a real component of the digital signal of the third frequency;
the processing unit is further configured to perform low-pass filtering on the first imaginary component to obtain an imaginary component of the digital signal of the third frequency;
the processing unit is further configured to perform down-conversion processing on the first mixed digital signal according to the local oscillator signal of the second frequency to obtain a second real component and a second imaginary component, where the second real component includes a real component of a digital signal of a fifth frequency corresponding to the digital signal of the first frequency and a real component of a digital signal of a sixth frequency corresponding to the digital signal of the second frequency, and the second imaginary component includes an imaginary component of the digital signal of the fifth frequency and an imaginary component of the digital signal of the sixth frequency;
the processing unit is further configured to perform low-pass filtering processing on the second real component to obtain a real component of the digital signal of the sixth frequency;
the processing unit is further configured to perform low-pass filtering processing on the second imaginary component to obtain an imaginary component of the digital signal at the sixth frequency.
9. An apparatus for signal processing, comprising a processor coupled with a memory, the processor being configured to implement the method of any one of claims 1-7 when executing computer programs or instructions stored in the memory.
10. A computer storage medium, characterized in that a computer program is stored on the computer storage medium, which computer program, when being executed by a processor, is adapted to carry out the method according to any one of claims 1-7.
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| US20060039511A1 (en) * | 2004-08-18 | 2006-02-23 | Jack Nachamkin | Digital signal processing remediation of cosite antenna interference |
| US20090231170A1 (en) * | 2006-03-30 | 2009-09-17 | Posdata Co., Ltd | Apparatus and method for digital frequency down-conversion |
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Application publication date: 20220819 |