CN114925840A

CN114925840A - Simulation method, apparatus and storage medium

Info

Publication number: CN114925840A
Application number: CN202210614944.2A
Authority: CN
Inventors: 孟则霖; 颜子贤
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2022-08-19

Abstract

The present disclosure provides an analog method, an apparatus and a storage medium, which relate to the field of data processing, and in particular to the field of quantum computation and quantum simulation. The specific implementation scheme is as follows: target quantum circuit C for simulating superconducting quantum chip to execute in classical computing equipment ₁ In the process of (2): determining a target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Wherein the layer evolution unitary matrix

Performing Lth of the target quantum circuit for the superconducting quantum chip obtained by simulation _j Evolution of the quantum state of the layer; based on Lth in the target quantum circuit _j Layer evolution unitary matrix corresponding to layers

Obtaining the target amountSub-circuit C ₁ Of the overall evolution unitary matrix

Thus, the execution target quantum circuit C of the superconducting quantum chip can be simulated ₁ The overall evolutionary unitary matrix.

Description

Simulation method, apparatus and storage medium

Technical Field

The present disclosure relates to the field of data processing technologies, and in particular, to quantum computing and quantum simulation technologies.

Background

At present, quantum computing has been implemented by many hardware platforms based on different physical principles, including superconducting quantum circuits, ion traps, optical photons, and nuclear magnetic resonance technologies. Due to strong expandability and high quantum gate operation speed, the superconducting quantum circuit is a leading technical route in the current quantum computing physical implementation. Superconducting quantum computing has been experimentally validated and has demonstrated superiority over classical computing in some specific computational problems.

Because hardware resources are expensive and scarce, when the realization of the quantum gate of the superconducting quantum circuit is researched, the operation of a classic computer simulation pulse on the superconducting quantum circuit is often used for designing and optimizing pulse parameters, so that the quantum gate with high fidelity is obtained in numerical value.

Disclosure of Invention

The present disclosure provides a simulation method, apparatus, and storage medium.

According to an aspect of the present disclosure, there is provided a simulation method applied to a classical computing device, including:

target quantum circuit C for simulating superconducting quantum chip to execute in classical computing equipment ₁ In the process of (2):

determining a target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Wherein the layer evolution unitary matrix

Performing Lth of the target quantum circuit for the simulated superconducting quantum chip _j Evolution of quantum states behind the layer;

based on the target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Obtaining the target quantum circuit C ₁ Total evolution unitary matrix of

According to another aspect of the present disclosure, there is provided a classic computing device, comprising:

a first processing unit for simulating a superconducting quantum chip in a classical computing device to execute a target quantum circuit C ₁ In the process of (2): determining a target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Wherein the layer evolution unitary matrix

a second processing unit for processing the quantum circuit based on the target ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Obtaining the target quantum circuit C ₁ Of the overall evolution unitary matrix

According to another aspect of the present disclosure, there is provided an electronic device including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method of any of the embodiments of the present disclosure.

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform a method according to any one of the embodiments of the present disclosure.

According to another aspect of the present disclosure, a computer program product is provided, comprising a computer program which, when executed by a processor, implements a method according to any of the embodiments of the present disclosure.

Thus, the superconducting quantum chip execution target quantum circuit C can be simulated ₁ The overall evolutionary unitary matrix.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The drawings are included to provide a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic flow chart diagram one of a simulation method according to an embodiment of the present application;

FIG. 2 is a schematic flow chart diagram two of a simulation method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an initial quantum circuit in a specific example of a simulation method according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a target quantum circuit in a specific example of a simulation method according to an embodiment of the present application;

FIG. 5 is a schematic flow chart diagram three of a simulation method according to an embodiment of the present application;

FIG. 6 is a schematic undirected graph of a superconducting quantum chip in a specific example of a simulation method according to an embodiment of the present application;

FIG. 7 is a first schematic diagram of a slicing result of a simulation method in a specific example according to an embodiment of the present application;

FIG. 8 is a second schematic diagram of a segmentation result of a simulation method in a specific example according to an embodiment of the present application;

FIG. 9 is a flow chart illustrating an implementation of a simulation method in a specific example according to an embodiment of the present application;

fig. 10(a) is a schematic diagram of an undirected graph (comprising 7 physical qubits) characterizing the connectivity structure of a superconducting quantum chip and a quantum circuit required for operation of the superconducting quantum chip;

fig. 10(b) is a schematic diagram of an undirected graph (comprising 12 physical qubits) characterizing the connectivity of a superconducting quantum chip and the quantum circuitry required for operation of the superconducting quantum chip;

FIG. 11 is a block diagram of a classic computing device, according to an embodiment of the present application;

FIG. 12 is a block diagram of an electronic device used to implement the simulation method of an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

Quantum computation is a computational model that follows quantum mechanics and regulates quantum information units to perform computation. Quantum computing is superior to conventional general purpose computers in dealing with certain problems, as compared to conventional computers. In quantum computing, a quantum gate can transform one quantum state into another quantum state, and is a reversible basic operation unit.

At present, quantum computing has been implemented by many hardware platforms based on different physical principles, including superconducting quantum circuits (i.e. superconducting quantum chips), ion traps, optical quanta, and nuclear magnetic resonance technology. Thanks to the strong expandability and the fast operation speed of the quantum gate, the superconducting quantum chip is a leading technical route in the current quantum computing physical implementation. Superconducting quantum computing has been experimentally validated at present and has demonstrated superiority over classical computing in certain computational problems.

Because hardware resources are expensive and scarce, when the implementation of the quantum gate of the superconducting quantum chip is researched, the operation of a classical computer simulation pulse on the superconducting quantum chip is often used for designing and optimizing pulse parameters, so that the quantum gate with high fidelity is obtained in numerical terms.

However, the evolution of superconducting quantum chips that numerically model multiple qubits on a classical computer is very difficult. This is because in numerical simulation, the dimension of the hilbert space in which the model used to simulate the complete superconducting quantum chip is located increases exponentially as the number of quantum bits in the model increases. Limited by the performance of classical computers, the time and storage space required to numerically solve the schrodinger equation of a high-dimensional hilbert space can be very large.

Based on the above, the scheme disclosed by the disclosure provides a novel simulation scheme for pulse control of the superconducting quantum chip, which can divide a hardware total subsystem corresponding to the superconducting quantum chip into a plurality of subsystems according to an input quantum circuit, a maximum interaction distance to be simulated and a connectivity structure of the superconducting quantum chip, then use schrodinger equation to numerically calculate the corresponding evolution of each subsystem, and finally combine the results in a complete hilbert space to simulate to obtain a final quantum state. According to the scheme, the remote interaction between the physical quantum bits can be ignored according to the hardware connectivity of the superconducting quantum chip and the structure of the quantum circuit, so that the dimensionality of the Hilbert space of the hardware total subsystem to be simulated is greatly reduced, and the numerical simulation of the pulse control of the superconducting quantum chip is accelerated.

The disclosed solution provides a simulation method; specifically, fig. 1 is a schematic flow chart one of a simulation method according to an embodiment of the present application. The method is optionally applied in classical computing devices, such as, for example, electronic devices with classical computing capabilities, such as personal computers, servers, server clusters, and the like. The method includes at least some of the following.

As shown in FIG. 1, the target quantum circuit C is implemented by simulating superconducting quantum chip in classical computing equipment ₁ In the process of (a), the method comprises:

step S101: determining a target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Wherein the layer evolution unitary matrix

Performing Lth of the target quantum circuit for the simulated superconducting quantum chip _j Evolution of quantum states behind the layer.

Here, the target quantum circuit C ₁ Comprising a plurality of logical qubits and a quantum gate acting on at least one logical qubit, i.e. also comprising a plurality of quantum gates. Further, the target quantum circuit C ₁ At least one level comprising at least one quantum gate in each level; said L is _j Layer of the target quantum circuit C ₁ Any one of the included levels.

It should be noted that the hierarchical division can be divided based on the order of the actual quantum gates, for example, the target quantum circuit C ₁ The quantum gate of the first level acts on the corresponding logic quantum bit in preference to the quantum gate of the second level; the quantum gate of the second level acts on the corresponding logic qubit in preference to the quantum gate of the third level, and so on; alternatively, the division may be performed based on actual requirements, and the division of the hierarchy is not particularly limited by the present disclosure.

Step S102: based on Lth in the target quantum circuit _j Layer evolution unitary matrix corresponding to layers

Obtaining the target quantum circuit C ₁ Total evolution unitary matrix of

Here, the total evolving unitary matrix

Namely the superconducting quantum chip obtained by simulation executes a target quantum circuit C ₁ Evolution of the latter quantum state. It should be noted that the layer evolution unitary matrix is obtained by solving the schrodinger equation by characterizing physical information of the superconducting quantum chip and a hamiltonian of the pulse parameter, so that the layer evolution unitary matrix can embody a control process of the quantum bit at a pulse level, and accordingly, the total evolution unitary matrix can reflect a control process of the quantum bit at a pulse level

Can also embody the control process of the quantum bit of the pulse level, thus being convenient for being based on the total evolution unitary matrix

Pulse parameters are designed and optimized to numerically model high fidelity quantum gates.

Thus, the superconducting quantum chip execution target quantum circuit C can be simulated ₁ The overall evolution unitary matrix of.

In a specific example, the superconducting quantum chip includes a plurality of physical qubits, and there may be a coupling between the physical qubits, for example, there may be a coupling between two adjacent physical qubits of the superconducting quantum chip. Here, the coupling between the physical parameters of the superconducting quantum chips may be direct coupling through capacitance or inductance, or indirect coupling through a coupler. Further, devices for coupling such as capacitors, inductors, couplers, etc. may be collectively referred to as coupling devices.

In a specific example of the disclosed solution, fig. 2 is a schematic flow chart two of a simulation method according to an embodiment of the present application. The method may optionally be applied in classical computing devices, such as personal computers, servers, server clusters, etc. electronic devices with classical computing capabilities. It is understood that the related content of the method shown in fig. 1 above can also be applied to this example, and the description of the related content in this example is omitted.

Further, the method includes at least part of the following. In particular, the target quantum circuit C is executed by simulating a superconducting quantum chip in a classical computing device ₁ As shown in fig. 2, the process includes:

step S201: based on the preset compiling rule, the initial quantum circuit C is subjected to ₀ Compiling to obtain the target quantum circuit C ₁ 。

Here, the preset compiling rule satisfies at least one of:

in the simulation process, the problem of crosstalk caused by coupling effect between physical quantum bits in the superconducting quantum chip when quantum gates in the target quantum circuit operate simultaneously can be reduced;

in the simulation process, the problem of crosstalk between quantum gates in the target quantum circuit within a distance d is ignored.

Here, the distance d is a preset shortest path; the shortest path may specifically refer to a shortest path between one physical qubit and another physical qubit in the superconducting quantum chip. Here, the definition of the shortest path can be referred to the following description, and is not described herein again.

Further, ignoring the crosstalk problem between quantum gates in the target quantum circuit within the range of the distance d may specifically be: the problem of crosstalk between any two quantum gates in the target quantum circuit within a distance d is ignored.

Thus, the target quantum circuit C used in the simulation process due to the disclosed scheme ₁ The method is obtained after compiling based on the preset compiling rule, so that crosstalk generated due to coupling effect between physical quantum bits in the superconducting quantum chip can be effectively reduced when the quantum gates run simultaneously (for example, when the quantum gates at the same level run simultaneously) in an experiment; meanwhile, the string of two quantum gates in the range of the distance d can be effectively ignoredAnd interference is reduced, so that the dimension of a Hilbert space in the simulation process is effectively reduced.

Step S202: determining a target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Wherein the layer evolution unitary matrix

Performing Lth of the target quantum circuit for the superconducting quantum chip obtained by simulation _j Evolution of the quantum state of the layer.

Step S203: based on Lth in the target quantum circuit _j Layer evolution unitary matrix corresponding to layers

Obtaining a total evolution unitary matrix of the target quantum circuit

It will be appreciated that quantum circuit C is due to the target ₁ Is to the initial quantum circuit C ₀ Compiled, so the simulation process of the disclosed scheme can also be understood as that the classical computing device simulates the superconducting quantum chip to execute the initial quantum circuit C ₀ The process of (1).

Thus, the physical system of the large-scale superconducting quantum chip can be divided into a plurality of subsystems, so that the evolution of the subsystems can be conveniently simulated, and moreover, the target quantum circuit C used in the simulation process ₁ The method is obtained after compiling based on the preset compiling rule, so that the dimensionality of a Hilbert space to be simulated is greatly reduced, the time consumed by simulation is greatly reduced, and the simulation efficiency is improved.

In a specific example, the preset compiling rule includes the target quantum circuit C obtained after compiling ₁ L in (1) _j The layers satisfy: adjacent logics of any two quantum gates within distance dThe intersection of the edit qubits is equal to the empty set. Therefore, a simple and feasible scheme is provided, and crosstalk generated by a physical quantum bit in the superconducting quantum chip due to a coupling effect can be effectively reduced when the quantum gates run simultaneously in an experiment, for example, when the quantum gates at the same level run simultaneously; meanwhile, the crosstalk of the two quantum gates in the range of the distance d can be effectively ignored, so that the dimension of a Hilbert space in the simulation process is effectively reduced.

Here, the target quantum circuit C ₁ The adjacent logical qubits of a quantum gate in (d) within its distance d can be defined as: all logical qubits at a distance d from the logical qubits acted on by the qubit gates.

In a specific example, the distance d is a preset shortest path; the shortest path may specifically refer to a shortest path between one physical qubit and another physical qubit in the superconducting quantum chip. Based on this, the target quantum circuit C ₁ The adjacent logic quantum bit of the quantum gate in the range of the distance d is determined based on the physical quantum bit corresponding to the logic quantum bit acted by the quantum gate in the superconducting quantum chip and all the physical quantum bits in the range of the preset shortest path. Further, a target quantum circuit C ₁ The adjacent logical qubits of a quantum gate in (b) within its distance d can be defined as: in the superconducting quantum chip, the physical qubits corresponding to the logical qubits acted on by the quantum gates are the logical qubits corresponding to all the physical qubits within the preset shortest path range of the physical qubits.

Further, in the target quantum circuit C ₁ L in (1) _j In the case where two or more quantum gates are included in a layer, the intersection of adjacent logical qubits of any two quantum gates within a distance d equal to the empty set may be specifically understood as: l th _j All logic qubits in a layer that are separated by a distance d or less from a logic qubit operated by one quantum gate, and all logic qubits in a layer that are separated by a distance d or less from a logic qubit operated by another quantum gateIntersections between the edit qubits are empty sets.

Further, in one example, for the initial quantum circuit C ₀ Target quantum circuit C obtained after compiling ₁ Satisfies the following conditions: in each of its levels, the intersection of adjacent logical qubits within a distance d of the logical qubits acted on by any two qubit gates is equal to the empty set.

In a specific example, the compiled target quantum circuit C ₁ The number of the included levels is larger than or equal to the initial quantum circuit C ₀ The number of levels involved. Therefore, a foundation is laid for reducing the time consumed by simulation and improving the simulation efficiency.

In a specific example, the target quantum circuit C ₁ The quantum gate included in (1) is a native quantum gate which can be realized by the superconducting quantum chip. Therefore, the Schrodinger equation is convenient to numerically calculate the corresponding evolution of each subsystem, and a total evolution unitary matrix is obtained for efficient simulation

And a foundation is laid.

For example, FIG. 3 shows three levels L ₁ ，L ₂ ，L ₃ Formed initial quantum circuit C ₀ The initial quantum circuit C ₀ Comprises 7 logic quanta bits, each of which is a logic quanta bit Q ₁ To logical qubit Q ₇ (ii) a Further, the square on a logical qubit in each level represents a single-bit gate (i.e., a single-qubit gate) acting on the logical qubit; and two blocks connected by a straight line represent a double-bit gate (i.e., a two-qubit gate) that acts on the corresponding logical qubits on the two blocks; for example, for L ₁ In terms of layers, the logical qubit acted on by the single-bit gate is the logical qubit Q ₂ (ii) a The logic quanta acted by the double-bit gate are respectively logic quanta Q ₃ And logical qubit Q ₄ 。

Further, during the simulation, to reduceWhen the quantum gates in the target quantum circuit operate simultaneously, the crosstalk problem generated by the coupling effect between the physical quantum bits in the superconducting quantum chip, and in order to ignore the crosstalk problem between the quantum gates in the target quantum circuit within the distance d range, the initial quantum circuit C shown in fig. 3 can also be subjected to ₀ Performing a compiling process, for example, d in the compiling process of this example is 1, and each logical qubit corresponds to one physical qubit in the superconducting quantum chip, and two adjacent physical qubits in the superconducting quantum chip have a coupling relationship, that is, the superconducting quantum chip includes 7 physical qubits, which are physical qubits q ₁ To physical qubit q ₇ And, coupling between two adjacent physical qubits, and, at the same time, a physical qubit q ₁ And a physical qubit q ₇ So as to obtain the target quantum circuit C shown in FIG. 4 after compiling ₁ 。

In particular, with an initial quantum circuit C ₀ Middle L ₁ Layer for example, logical qubit Q operated on by a single-qubit gate ₂ All logical qubits with a distance d equal to or less than 1 (i.e., a distance within a logical qubit range) are: logical qubit Q ₁ And logical qubit Q ₃ . Further, a logical qubit Q acted on by a double-bit gate ₃ And logical qubit Q ₄ All logical qubits with a distance d equal to or less than 1 are: logical qubit Q ₂ And logical qubit Q ₅ (ii) a At this time, the initial quantum circuit C ₀ L to ₁ In the layer, the intersection of adjacent logic qubits of the single-qubit gate and the double-qubit gate in the range of distance d equal to 1 is the logic qubit Q ₂ For non-empty sets, based on which the initial quantum circuit C needs to be set ₀ Middle L ₁ The layers are compiled to get the L < th > layer as shown in FIG. 4 ₁ Layer and L ₂ Layer, i.e. to initiate a quantum circuit C ₀ Middle L ₁ Two quantum gates of a layer are partitioned to a target quantum circuit C ₁ Middle L ₁ Layer and L ₂ And (3) a layer. In this kind ofPush to initial quantum circuit C ₀ Each layer in the target quantum circuit is compiled to obtain a target quantum circuit C as shown in FIG. 4 ₁ 。

Here, the compiled target quantum circuit C ₁ Is 5, is larger than the initial quantum circuit C ₀ Number of levels (3) included.

In a specific example of the disclosed solution, fig. 3 is a schematic flow chart three of a simulation method according to an embodiment of the present application. The method may optionally be applied in classical computing devices, such as personal computers, servers, clusters of servers, etc. electronic devices with classical computing capabilities. It is understood that the related contents of the methods shown in fig. 1 and fig. 2 above can also be applied to this example, and the example is not repeated for the related contents.

Further, the method includes at least part of the following. In particular, the target quantum circuit C is executed by simulating a superconducting quantum chip in a classical computing device ₁ As shown in fig. 5, the process includes:

step S501: on the basis of a preset segmentation rule, a target quantum circuit C is subjected to ₁ Middle L _j The layer is cut to obtain the L _j Layer corresponding circuit subsystems.

Here, the L < th > item _j The circuit subsystem corresponding to the layer comprises the L-th circuit subsystem _j And a subsystem formed by corresponding partial circuits of the layers.

Step S502: based on the obtained L _j The circuit subsystems corresponding to the layers divide the undirected graph representing the superconducting quantum chip to obtain the L < th > graph _j Layer corresponding hardware subsystems.

That is, the superconducting quantum chip is simulated on a classical computing device to execute the target quantum circuit C ₁ In the process of (2), a target quantum circuit C is required ₁ Middle L _j The layer is cut into a plurality of circuit subsystems, and then the physical quantum bit in the undirected graph representing the superconducting quantum chip is cut based on the result after cutting, so as to obtain the L < th > of the quantum chip _j Hardware subsystem with layer correspondenceNamely the subsystem corresponding to the quantum bit including part of the physical quantum bit.

For example, as shown in FIG. 6, an undirected graph G is introduced to represent the connected structure of a superconducting quantum chip, where each vertex q represents a physical qubit, an edge (q) of the superconducting quantum chip _m ，q _m′ ) Representing a physical qubit q _m And a physical qubit q _m′ There may be a coupling (including a direct coupling and an indirect coupling) between them, or there may be a coupling relationship. For example, a physical qubit q ₁ And a physical qubit q ₂ The two can be directly coupled through capacitance or inductance, or indirectly coupled through a coupler. Based on this, the set of vertices N and the set of edges E of the undirected graph G as shown in fig. 6 can be written as:

N＝{q ₁ ，q ₂ ，q ₃ ，q ₄ ，q ₅ ，q ₆ ，q ₇ }；

E＝{(q ₁ ，q ₂ )，(q ₂ ，q ₃ )，(q ₃ ，q ₄ )，(q ₄ ，q ₅ )，(q ₅ ，q ₆ )，(q ₆ ，q ₇ )，(q ₁ ，q ₇ )}；

accordingly, the undirected graph G may be denoted G ═ NUE.

It should be noted that the target quantum circuit C is implemented ₁ The physical quantum bit in the superconducting quantum chip, and the target quantum circuit C ₁ There is a mapping relationship between the logical qubits in (a), for example, there is a one-to-one correspondence relationship. Further, in practical application, the target quantum circuit C ₁ There may also be no one-to-one correspondence between logical qubits in (C) and physical qubits in the superconducting quantum chip, as long as the target quantum circuit (C) ₁ The number of logical qubits in (a) is not less than the number of physical qubits in the superconducting quantum chip. For example, target quantum circuit C ₁ One logical qubit in the superconducting qubit corresponds to a plurality of physical qubits in the superconducting quantum chip, etc., which is not limited by the disclosed solution.

Step S503: determine the secondL _j Layer-corresponding ith hardware subsystem k _jl Sub-evolution unitary matrix of

Wherein the sub-evolution unitary matrix

Said L < th > obtained for simulation _x The L-th hardware subsystem corresponding to the layer executes the L-th hardware subsystem _j And (4) evolution of quantum states after the first circuit subsystem corresponding to the layer.

Here, the L < th > is _j Layer-corresponding ith hardware subsystem k _jl Is based on said Lth obtained by splitting _j The l-th circuit subsystem corresponding to the layer.

In a specific example, the sub-evolution unitary matrix can be obtained by numerical calculation by using a time-containing hamilton in a Duffing oscillator form, and can embody the evolution process of controlling the superconducting quantum chip by pulses of specific parameters, so that the simulation of pulse level is realized, and simultaneously, the physical phenomena generated by neighbor coupling and sub-neighbor coupling are effectively simulated. Here, the flow of calculating the value of the unitary sub-evolution matrix may refer to the following derivation flow, which is not described herein again.

Step S504: based on the L < th > of _j Sub-evolution unitary matrix of l hardware subsystem corresponding to layer

Obtaining the target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Step S505: based on Lth in the target quantum circuit _j Layer evolution unitary matrix corresponding to layers

Obtaining a total evolution unitary matrix of a target quantum circuit

Therefore, the scheme can firstly segment the levels in the target quantum circuit based on the preset segmentation rule, then segment the undirected graph representing the superconducting quantum chip based on the hierarchical segmentation result of the target quantum circuit to obtain the hardware subsystems corresponding to the levels, and obtain the sub-evolution unitary matrix of the hardware subsystems corresponding to the levels through numerical calculation.

In addition, the unitary matrix can be evolved in a sub-mode, the layer evolution unitary matrix corresponding to the layers is obtained, and the total evolution unitary matrix is obtained finally, so that the problem of numerically solving the Schrodinger equation in the high-dimensional Schrodinger space is divided into numerical simulation of a plurality of low-dimensional Schrodinger spaces, and the time consumed by simulation can be greatly reduced.

In a specific example, the preset segmentation rule includes at least one of the following:

will L _j The layer contains logic quantum bit with quantum gate function and adjacent logic quantum bit with quantum gate function in the distance d as Lth _j A circuit subsystem of a layer;

will L _j Logic qubit of inactive quantum gate in layer as Lth _j The circuit subsystems of the layers.

For example, as shown in FIG. 7, the L-th line shown in FIG. 4 ₂ The layer is illustrated as an example, in which case the target quantum circuit C ₁ Middle L ₂ The layers may comprise circuit subsystems that are:

logical qubit Q acted on by a double-bit gate ₃ And logical qubit Q ₄ Logical qubit Q ₃ Neighboring logical qubits Q in the range of 1 for a distance d ₂ And a logical qubit Q ₄ Contiguous logical qubit Q within a distance d-1 ₅ What is meant byForming a circuit subsystem;

logical qubit Q of the remaining non-contributing quantum gates ₁ Logical qubit Q ₆ And logical qubit Q ₇ Each formed separately as a circuit subsystem.

Based on this, the target quantum circuit C ₁ Middle L ₂ The layer includes a total of 4 circuit subsystems.

Therefore, a simple and feasible circuit splitting scheme is provided, and thus, the problem of numerical solution of Schrodinger equation in a high-dimensional Hilbert space is split into a plurality of numerical simulations in a low-dimensional Hilbert space, so that the time consumed by simulation can be greatly reduced.

In a specific example, the L-th result is obtained _j The circuit subsystem corresponding to the layer is used for carrying out segmentation processing on the undirected graph representing the superconducting quantum chip to obtain the L < th > graph _j A hardware subsystem corresponding to a layer, comprising at least one of:

l th _j In the layer, a hardware subsystem is formed by a physical qubit corresponding to a logical qubit acted on by a quantum gate, an adjacent physical qubit of the physical qubit within a distance d, and an associated coupling device, wherein the associated coupling device is a coupling device for coupling the physical qubit corresponding to the quantum gate and/or the adjacent physical qubit;

at the L th _j In the layer, the hardware subsystem is formed by the physical qubits corresponding to the logical qubits of the unused qubits.

Therefore, a simple and feasible undirected graph segmentation scheme is provided, and thus, the problem of numerical solution of Schrodinger equation in a high-dimensional Hilbert space is divided into a plurality of numerical simulations in a low-dimensional Hilbert space, so that the time consumed by simulation can be greatly reduced.

For example, as shown in FIG. 7, the logical qubits in the target quantum circuit correspond one-to-one with the physical qubits in the superconducting quantum chip, and further as shown in Lth in FIG. 4 ₂ The layers are illustrated by way of example, and at this time,target quantum circuit C ₁ L to ₂ The hardware subsystems corresponding to the layers can be:

logical qubit Q to be acted on by a double-bit gate ₃ Corresponding physical quantum bit q ₃ Logical qubit Q acted on by a Bibit Gate ₄ Corresponding physical quantum bit q ₄ Physical qubit q ₃ Contiguous physical qubits q in the range of 1 to d ₂ Physical qubit q ₄ Contiguous physical qubit q in the range of 1 from d ₅ And a physical qubit q ₂ And a physical qubit q ₃ Coupling device between, physical qubit q ₄ And a physical qubit q ₃ Coupling device between, physical qubit q ₄ And a physical qubit q ₅ A coupling device between them to form a hardware subsystem;

logical qubit Q of the remaining non-contributing quantum gates ₁ Corresponding physical quantum bit q ₁ Logical qubit Q ₆ Corresponding physical quantum bit q ₆ And logical qubit Q ₇ Corresponding physical quantum bit q ₇ Each forming a hardware subsystem separately.

Based on this, the target quantum circuit C ₁ Middle L ₂ The number of hardware subsystems corresponding to the layers is 4.

Therefore, the evolution process of the corresponding ground circuit subsystems can be conveniently simulated one by one, and a foundation is laid for obtaining the layer evolution unitary matrix.

In a specific example, the layer evolution unitary matrix can be obtained as follows

I.e. based on said L _j Sub-evolution unitary matrix of l hardware subsystem corresponding to layer

Obtaining a target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

The method specifically comprises the following steps: subjecting the L th _j Carrying out tensor product processing on the sub evolution unitary matrix of each hardware subsystem corresponding to the layer to obtain a target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Thus, the problem of numerically solving the Schrodinger equation in the high-dimensional Hilbert space is divided into a plurality of numerical simulations in the low-dimensional Hilbert space, so that the time consumed by the simulation can be greatly reduced.

In a specific example, the unitary matrix of layer evolution is obtained

Then, the total evolution unitary matrix can be obtained based on the following mode

That is, the quantum circuit C based on the target as described above ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Obtaining a target quantum circuit C ₁ Total evolution unitary matrix of

The method specifically comprises the following steps: based on the target quantum circuit C ₁ Order of intermediate levels, the target quantum circuit C ₁ Performing product processing (such as matrix product processing) on the layer evolution unitary matrix corresponding to each middle layer to obtain the target quantum circuit C ₁ Of the overall evolution unitary matrix

That is, the target quantum circuit C is implemented on an analog superconducting quantum chip ₁ In the process, the superconducting quantum chip can be firstly simulated to executeAnd each layer in the target quantum circuit obtains a layer evolution unitary matrix of each layer, and then obtains a total evolution unitary matrix based on the layer evolution unitary matrix. For example, target quantum circuit C ₁ Comprises n layers, which can be designated as { L ₁ ，L ₂ ，…，L _n At this time, each level is evolved to obtain a layer evolution unitary matrix corresponding to each level, which can be recorded as

And finally, based on the layer evolution unitary matrix corresponding to each layer level

Obtaining the whole target quantum circuit C ₁ Total evolution unitary matrix of

Thus, compared with the prior art, the scheme disclosed by the invention has the following advantages:

first, the disclosed solution uses the "divide and conquer method" to simulate the pulse-level simulation of the superconducting quantum chip, which greatly reduces the time taken for simulation. Specifically, according to the scheme, a physical system (namely a hardware total amount subsystem) of a large-scale superconducting quantum chip is divided into a plurality of hardware subsystems according to a certain rule, and then the evolution of each hardware subsystem is calculated and simulated respectively, so that the problem of numerically solving the Schrodinger equation in a high-dimensional Hilbert space is divided into numerical simulation of a plurality of low-dimensional Hilbert spaces, and therefore the time consumed by simulation can be greatly reduced.

Secondly, the target quantum circuit used in the scheme of the present disclosure is obtained after compiling, and the target quantum circuit can reasonably ignore the long-distance weak interaction generated by coupling, so as to realize the dynamic simulation of the pulse level of the large-scale superconducting quantum chip. Meanwhile, quantum gates close to each other in the communication structure are staggered in time, and therefore crosstalk noise generated by the quantum gates running simultaneously is reduced.

Thirdly, the evolution unitary matrix of the hardware subsystem (the hardware subsystem is obtained by splitting based on the splitting mode) is obtained by numerical calculation through the time-containing Hamilton quantity in the form of Duffing oscillator, so that the physical phenomena generated by adjacent coupling and next adjacent coupling, including crosstalk caused by parasitic coupling, control of magnetic flux to bit frequency and the like, are effectively simulated.

Fourth, the disclosed solution is applicable to evolution simulation of dynamics of multi-bit quantum computation based on other physical systems.

The following detailed description of the disclosed embodiments is made in terms of two aspects, including: the first section, setting forth the background of the disclosed scheme, includes quantum circuits, connected structures of superconducting quantum chips and corresponding pulse compilation schemes. In the second section, the technical solution of the present disclosure is explained in detail. And a third part, which shows the effects and advantages of the disclosed solution.

A first part:

(1) quantum circuit, native quantum gate and superconducting quantum chip.

In the following, the initial quantum circuit C is described ₀ For example, the quantum circuit is introduced, and in practical application, the initial quantum circuit C is used ₀ Resulting target quantum circuit C ₁ See also below, the present disclosure directed to quantum circuits C ₁ And an initial quantum circuit C ₀ Similar structural features are not described in detail.

Given a quantum circuit (i.e. initial quantum circuit) C ₀ The quantum circuit C ₀ Comprising p levels, e.g. L ₁ ，L ₂ ，L ₃ ，...，L _p Can be recorded as C ₀ ＝{L ₁ ，L ₂ ，L ₃ ，...，L _p }; each level comprising a number of quantum gates g _i Herein, thisWhen it is, L _a The quantum gate included in a layer can be denoted as L _a ＝{g ₁ ，g ₂ ，...，g _i ,., wherein a is 1, 2, p, i is a natural number greater than or equal to 1. Quantum gate g _i The active logical qubits may be grouped into a set, e.g. a two-bit qubit gate g _i′ Acting on logical qubits Q ₁ And logical qubit Q ₂ In this case, it can be written as onQubits (g) _i′ )＝{Q ₁ ，Q ₂ }. Here, in this example, the quantum circuit C ₀ At the same level (e.g. Lth L) _a Layer) is an empty set, that is, the intersection of the logical qubits acted on by the quantum gates needs to satisfy:

for example, FIG. 3 shows three levels L ₁ ，L ₂ ，L ₃ Constituent quantum circuits C ₀ The quantum circuit C ₀ Comprises 7 logic quanta bits, each of which is a logic quanta bit Q ₁ To logical qubit Q ₇ (ii) a Further, the square on a logical qubit in each level represents a single-bit gate (i.e., a single-qubit gate) acting on that logical qubit; and two blocks connected by a straight line represent a double-bit gate (i.e., a two-qubit gate) that acts on the corresponding logical qubits on the two blocks; for example, for L ₁ For a layer, the logical qubit acted on by the single-bit gate is the logical qubit Q ₂ (ii) a The logic quanta acted by the double-bit gate are respectively logic quanta Q ₃ And logical qubit Q ₄ 。

Here, in a specific example, the quantum circuit C ₀ All the quantum gates g in the quantum gate array are native quantum gates which can be directly realized by a superconducting quantum chip, namely quantum gates which can be directly realized on a hardware level by pulses. It will be appreciated that in practice, the quantum circuit C ₀ All quantum gates g in (1) may or may not be superconducting quantum chipsA directly implemented native quantum gate, to which the disclosed solution is not particularly limited.

It should be noted that, in the superconducting quantum chip, the implementation of the native two-qubit gate requires a coupling effect between the physical qubits. Here, the coupling between the physical qubits of the superconducting quantum chip may be either a direct coupling through capacitance or inductance, or an indirect coupling through a coupler.

Further, as shown in fig. 6, an undirected graph G is introduced to represent the connected structure of the superconducting quantum chip, wherein each vertex q represents a physical qubit, an edge (q) of the superconducting quantum chip _m ，q _m′ ) Representing a physical qubit q _m And a physical qubit q _m′ There may be a coupling (including a direct coupling and an indirect coupling) between them, or there may be a coupling relationship. For example, a physical qubit q ₁ And a physical qubit q ₂ The two can be directly coupled through capacitance or inductance, or indirectly coupled through a coupler.

Based on this, the set of vertices N and the set of edges E of the undirected graph G as shown in fig. 6 can be written as:

N＝{q ₁ ，q ₂ ，q ₃ ，q ₄ ，q ₅ ，q ₆ ，q ₇ }；

accordingly, undirected graph G may be denoted G ═ NUE.

Further, a system corresponding to the undirected graph G can be regarded as a complete system of the superconducting quantum chip (which may be referred to as a total hardware subsystem for short), a subsystem of the total hardware subsystem (which may be referred to as a hardware subsystem for short) can be represented by a subgraph of the undirected graph G, and the hardware subsystem can be denoted as k.

Here, two physical qubits q _m And a physical qubit q _m′ The distance between can be defined as: physical quanta in undirected graph GBit q _m And a physical qubit q _m′ The shortest path between them, for example, the number of shortest edges can be regarded as the shortest path and recorded as function distance (q) _m ，q _m′ )。

Further, within the undirected graph G, the set of all physical qubits at distances of less than or equal to the distance d from the physical qubit qm (i.e. the predetermined shortest path) can be defined as:

further, a quantum circuit C ₀ The adjacent logical qubits of the quantum gate g in (b) within its distance d can be defined as: all the logical qubits at a distance d less than or equal to the logical qubit acted on by the quantum gate g are written as:

further, in this example, the physical quantum bit in the superconducting quantum chip, and the quantum circuit C ₀ There is a mapping relationship between the logical qubits in (e.g., as shown in FIG. 8, Quantum Circuit C) ₀ The logical quantum bits in the superconducting quantum chip and the physical quantum bits in the superconducting quantum chip have a one-to-one correspondence relationship.

In practical applications, the quantum circuit C ₀ There may also be no one-to-one correspondence between logical qubits in (C) and physical qubits in the superconducting quantum chip, as long as the quantum circuit (C) is in charge of ₀ The number of logical qubits in (a) is not less than the number of physical qubits in the superconducting quantum chip. For example, quantum circuit C ₀ One logical qubit in the superconducting quantum chip corresponds to a plurality of physical qubits in the superconducting quantum chip, etc., which the disclosed solution is not limited to.

(2) Pulse and native quantum gate

The present example uses a quantum circuit C ₀ All quantum gates g in (1)The example is introduced for a native quantum gate which can be directly realized by a superconducting quantum chip. Specifically, the native quantum gate of the superconducting quantum chip can be realized by applying a preset control pulse to the physical quantum bit of the superconducting quantum chip.

Here, it is assumed that the hardware subsystem k includes three physical qubits, which are: physical qubit q _m Physical qubit q _m′ And a physical qubit q _m″ . Here, the physical qubit q _m′ And a physical qubit q _m″ There is a coupling effect between the hardware subsystems, and in this case, the hardware subsystem k can be recorded as:

k＝{q _m ，(q _m′ ，q _m ″)} _{m，m′，m″} ；

further, using a temporal hamiltonian representation in the form of Duffing vibrators: hamiltonian H in a time period t during which a pulse corresponding to a quantum gate g is applied to the hardware subsystem k _k (t)：

Here, the operator

Representing a physical qubit q _m Generating an operator of (a); operator a _m Representing a physical qubit q _m Annihilation operator of (2), parameter ω _m Representing a physical qubit q _m A transition frequency from a ground state to a first excited state; operator alpha _m Representing a physical qubit q _m A dissonance from a ground state to a first excited state; operator symbol

Representing a physical qubit q _m′ Generating an operator; operator a _m′ Representing a physical qubit q _m′ The annihilation operator of (a); operator

Representing a physical qubit q _m″ Generating an operator of (a); operator a _m″ Representing a physical qubit q _m″ The annihilation operator of (a); j. the design is a square _m′m″ Representing a physical qubit Q _m″ And physical qubit Q _m′ The effective coupling strength between; h _ctrl And (t) is a pulse control item corresponding to the quantum gate g.

In this example, in order to increase the speed of numerical operation, the high-frequency oscillation term in the hamiltonian can be reduced or eliminated by rotating coordinate system transformation and rotating wave approximation. That is, the above formula (4) is converted into the specified rotational frequency ω by the above conversion and approximation _rot Hamiltonian of:

wherein the content of the first and second substances,

further, by rotating the wave approximation will

Eliminating middle and high frequency terms, thus obtaining Hamiltonian for numerical calculation

Can be simply recorded as H' _k (t) of (d). The Hamilton amount H' _k (t) contains the information related to the physical qubits and the pulses; further, the Hamilton quantity H' _k (t) unitary transformation matrix U of quantum state of corresponding hardware subsystem k _k The numerical solution can be obtained by the following formula:

further, based on the above formula (5) and formula (6), the unitary transformation matrix U of the quantum state of the hardware subsystem k is obtained _k ：

U _k ＝getUnitary(H′ _k ，g，ω _rot ) Formula (7);

wherein, H' _k Is H' _k (t), g denotes a quantum gate,. omega. _rot Indicating the specified rotating coordinate system frequency. The time consumed for the calculation of this step (e.g., equation 6 and equation 7) is related to the dimension of the hamilton quantity, because the hilbert space dimension grows exponentially with the number of qubits, and thus, when the hilbert space dimension of the system of the analog superconducting quantum chip is too large, the time consumed by this step becomes very large, and at this time, the memory of the computer may not be able to store the matrix with very large dimension.

A second part: technical scheme

The scheme of the disclosure provides a method for simulating pulse control of a superconducting quantum chip, which divides the whole system (such as a circuit total amount subsystem and a hardware total amount subsystem) into a plurality of subsystems without mutual interaction according to an input quantum circuit, a preset compiling rule, a communication structure of the superconducting quantum chip and the accuracy required to be simulated. The core steps of the disclosed scheme and the algorithms thereof will be described in detail herein.

(1) Compiling initial quantum circuits

The scheme of the present disclosure is based on the input quantum circuit (i.e. initial quantum circuit) C ₀ A connection structure G of the superconducting quantum chip and a preset compiling rule (such as a set distance d), and a quantum circuit C ₀ Compile into a new quantum circuit (i.e. target quantum circuit) C ₁ It is written as:

C ₁ ＝compile(G，C ₀ d) formula (8)

Here, for quantum circuit C ₀ (C ₀ ＝{L ₁ ，L ₂ ，L ₃ ，...，L _p }) new quantum circuit C obtained after compiling ₁ Comprising n levels, e.g. L ₁ ，L ₂ ，L ₃ ，...，L _n Can be recorded as C ₁ ＝{L ₁ ，L ₂ ，L ₃ ，...，L _n Wherein, then is greater than or equal to p. Further, for the new quantum circuit C ₁ In other words, each level includes several quantum gates g _i E.g. item L _j The quantum gate comprised by a layer may also be denoted L _j ＝{g ₁ ，g ₂ ，...，g _i ,.., wherein j is 1, 2, n, i is a natural number equal to or greater than 1. In addition, the quantum circuit C ₀ Middle L _a Quantum gates, i.e. L, included in a layer _a ＝{g ₁ ，g ₂ ，...，g _i ,., and a new quantum circuit C ₁ Middle L _j Quantum gates, i.e. L, included in a layer _j ＝{g ₁ ，g ₂ ，...，g _i ,., the quantum gates contained may or may not be identical.

Further, the preset compiling rule is that: for obtaining new quantum circuit C after compiling ₁ In each level thereof, e.g. L _j Any two quantum gates of a layer, such as quantum gate g _i And quantum gate g _i′ The intersection of adjacent logical qubits within the distance d is equal to the empty set, i.e. it is necessary to satisfy:

here, the purpose of using the preset compilation rule is two: the first is that the crosstalk generated by the coupling effect of the physical quantum bit in the superconducting quantum chip when the quantum gate runs simultaneously can be reduced in the experiment; the second is that the crosstalk of the two quantum gates in the range of the distance d can be ignored in the simulation process (i.e. simulation process), so as to reduce the dimension of the simulated hilbert space.

For example, as shown in FIG. 4, for the quantum circuit C shown in FIG. 3 ₀ A possible new quantum circuit C obtained after compiling based on the preset compiling rule (e.g. distance d ═ 1) ₁ . It will be appreciated that, in practical applications, a plurality of different new quantum circuits C may be compiled based on a given preset compiling rule ₁ At this time, the selection can be based on actual requirementsOne of them is not particularly limited in the present disclosure.

(2) For new quantum circuit C ₁ Performing a cutting process

The scheme of the disclosure is based on the input distance d and a new quantum circuit C ₁ L to _j Layers and undirected graph G characterizing the connectivity of superconducting quantum chips, for a new quantum circuit C ₁ Lth of the corresponding complete system (abbreviated as circuit total subsystem) _j The layers are cut to obtain a new quantum circuit C ₁ L to _j Several subsystems (circuit subsystems for short) corresponding to the layer.

Specifically, the preset segmentation rule is as follows: for new quantum circuit C ₁ For the hierarchy of (1), the L < th > level _j The logical qubit acted on by each qubit g of the layer and its neighbouring logical qubits within the distance d serve as a circuit subsystem comprising a new quantum circuit C ₁ Middle L _j A partial circuit structure in a layer; novel quantum circuit C ₁ The L th _j In the layer, the rest idle logic qubits (i.e., the logic qubits without the quantum gate effect) each serve as a circuit subsystem.

Further, based on new quantum circuit C ₁ Middle L _j The result of the layer splitting will be undirected graph G _j Each qubit of a layer g corresponds to a physical qubit acted upon by the logical qubit, and neighboring physical qubits of the physical qubit within a distance d, and a coupling device (such as a capacitor or inductor or coupler) for coupling the physical qubits (e.g., the physical qubit corresponding to the logical qubit acted upon by the qubit g, and the neighboring physical qubits of the physical qubit within the distance d) as a hardware subsystem. Meanwhile, in the undirected graph G, a new quantum circuit C ₁ L to _j The idle physical qubits corresponding to the idle logical qubits of the layer (i.e., the physical qubits not corresponding to the logical qubits acting as quantum gates) each act as a hardware subsystem。

Note that the new quantum circuit C ₁ Middle L _j Circuit subsystem obtained by slicing layers, and circuit based on Lth _j The hardware subsystems obtained by segmenting the undirected graph G according to the segmentation result of the layer correspond to each other, in other words, the segmentation modes of the undirected graph G and the undirected graph G have an association relation, so that the L < th > can be obtained _j The circuit subsystem (or hardware subsystem) obtained after the slicing of the layers is denoted as k _j (ii) a That is, k _j Is to the L < th > of _j The circuit sub-systems obtained after the layers have been split, or the representation is based on Lth _j The L-th graph obtained by segmenting the undirected graph G according to the segmentation result of the layer _j The corresponding hardware subsystem of the layer.

Further, based on L _j The layer segmentation result is obtained by segmenting the undirected graph G to obtain the L-th graph _j Segmentation process of hardware subsystem corresponding to layer, available function slice (G, L) _j And d) denotes the number L obtained after the slicing _j Set of hardware subsystems corresponding to layers, K ═ K _j1 ，k _j2 ，k _j3 ...k _jb Denotes, i.e. L _j The number of hardware subsystems corresponding to the layers is b, and b is a natural number more than or equal to 2; it will be appreciated that the set K may also represent the Lth _j Circuit subsystems corresponding to the layers, L _j The number of the circuit subsystems corresponding to the layers is b.

Specifically, K ═ slice (G, L) _j ，d)＝{k _j1 ，k _j2 ，k _j3 ...k _jb Equation (10);

for example, as shown in FIG. 7, for the new quantum circuit C shown in FIG. 4 ₁ L to ₂ The set of circuit subsystems after the layer segmentation is as follows:

{{Q ₅ ，Q ₂ ，Q ₃ ，Q ₄ ，(Q ₄ ，Q ₅ )，(Q ₂ ，Q ₃ )，(Q ₃ ，Q ₄ )}，{Q ₁ }，{Q ₆ }，{Q ₇ }}.

similarly, a new quantum circuit C is shown in FIG. 4 ₁ L to ₂ Layer pairThe set K of hardware subsystems is:

K＝{{q ₅ ，q ₂ ，q ₃ ，q ₄ ，(q ₄ ，q ₅ )，(q ₂ ，q ₃ )，(q ₃ ，q ₄ )}，{q ₁ }，{q ₆ }，{q ₇ equation (11).

(3) Calculating an evolving unitary matrix

And simulating to obtain an evolution unitary matrix corresponding to each layer of the quantum circuit. For example, for the new quantum circuit C ₁ L of (1) _j Layer, needs to calculate the L < th > L _j Layer evolution unitary matrix corresponding to layers

The layer evolution unitary matrix

Used for simulating the superconducting quantum chip to execute a new quantum circuit C ₁ To the L th _j Quantum state after the layer.

The calculation method comprises the following steps: according to a given frequency ω of the rotating coordinate system _rot And the L < th > of _j Each hardware subsystem k corresponding to the layer _jl (

l

1, 2.. b.) e.k, and the hardware subsystem K _jl Corresponding quantum gate

To obtain the L _j Hardware subsystem k with corresponding layers _jl Sub-evolution unitary matrix of

Here, a hardware subsystem without the quantum gate effect may be considered as a qubit idle during the simulation.

Further, repeating the above operation to obtain the L-th _j Sub evolution unitary matrix of all hardware subsystems corresponding to the layer and the L < th > _j Carrying out tensor product processing on the sub evolution unitary matrix of all hardware subsystems corresponding to the layer to obtain the Lth _j Layer evolution unitary matrix corresponding to layer

Further, a new quantum circuit C is obtained ₁ The layer evolution unitary matrix corresponding to all the levels is obtained, and the new quantum circuit C is obtained based on the layer evolution unitary matrix corresponding to all the levels ₁ Total evolution unitary matrix (level maximum L) _n I.e. new quantum circuits C ₁ Consisting of n levels):

(4) algorithm steps of the presently disclosed aspects

As shown in fig. 9, the algorithm steps of the scheme of the present disclosure mainly include:

step 1: input of initial quantum circuit C composed of native quantum gate ₀ Undirected graph G showing the connected structure of the superconducting quantum chip, and preset rotation frequency ω _rot And a preset maximum interaction distance d.

And 2, step: initial quantum circuit C ₀ Compiling based on the compiling mode to obtain a new quantum circuit C ₁ In order to reduce crosstalk and to reduce the analog hilbert space dimension.

And 3, step 3: for the new quantum circuit C according to the undirected graph G and the distance d ₁ L in (1) _j Layer, cutting to obtain the L-th layer _j A plurality of circuit subsystems corresponding to the layers; and based on L _j Slicing the undirected graph G to obtain the resultL th _j And the layers correspond to a plurality of hardware subsystems.

And 4, step 4: using Duffing oscillator model to obtain L _j Hamiltonian of each hardware subsystem of the layer, and calculating to obtain the Lth _j Hardware subsystem k of a layer _jl Corresponding sub-evolutionary unitary matrix

And the L < th > is _j Performing tensor product processing on the sub evolution unitary matrix corresponding to all hardware subsystems of the layer to obtain the L < th > hardware subsystem _j Layer evolution unitary matrix corresponding to layers

And 5: multiplying the layer evolution unitary matrix of all levels according to the level sequence to obtain the new quantum circuit C ₁ Total evolution unitary matrix of

And a third part: results display

Fig. 10(a) is a schematic diagram of an undirected graph (including 7 physical qubits) characterizing a connected structure of a superconducting quantum chip and a quantum circuit desired to be operated by the superconducting quantum chip, and fig. 10(b) is a schematic diagram of an undirected graph (including 12 physical qubits) characterizing a connected structure of a superconducting quantum chip and a quantum circuit desired to be operated by the superconducting quantum chip. Based on this, the present disclosure compares the operation speed of the simulation method of the existing full hamiltonian with the present disclosure through two different examples of fig. 10(a) and 10 (b). The specific results are shown in the following table:

it is worth noting that the existing full Hamiltonian-based approach is not able to perform kinetic simulations on superconducting quantum chips of 12 physical qubits, since the Hilbert space dimension exceeds the upper limit of the matrix dimension that can be handled by classical computers.

In conclusion, compared with the existing scheme, the scheme disclosed by the invention has the following advantages:

Second, the target quantum circuit used in the present disclosure is obtained after compiling, and the target quantum circuit can reasonably ignore the remote weak interaction caused by coupling, so as to implement the dynamic simulation of the pulse level of the large-scale superconducting quantum chip. Meanwhile, quantum gates close to each other in the communication structure are staggered in time, and therefore crosstalk noise generated by the quantum gates running simultaneously is reduced.

The disclosed solution provides a classic computing device, as shown in fig. 11, comprising:

a first processing unit 1101 for executing a target quantum circuit C in a classical computing device simulating a superconducting quantum chip ₁ In the process of (2): determining a target quantumCircuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

Wherein the layer evolution unitary matrix

Performing Lth of the target quantum circuit for the superconducting quantum chip obtained by simulation _j Evolution of quantum states behind the layer;

a second processing unit 1102 for processing the target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

In a specific example of the disclosure, the first processing unit is further configured to:

based on the preset compiling rule, the initial quantum circuit C is processed ₀ Compiling to obtain the target quantum circuit C ₁ (ii) a Wherein the preset compiling rule satisfies at least one of the following:

in the simulation process, the problem of crosstalk generated by coupling between physical quantum bits in the superconducting quantum chip when quantum gates in the target quantum circuit operate simultaneously can be solved;

In a specific example of the disclosure, the preset compiling rule includes the target quantum circuit C obtained after compiling ₁ L of (1) _j The layers satisfy: the intersection of adjacent logical qubits of any two quantum gates within a distance d is equal to the empty set.

In a specific example of the disclosed solution, the result is obtained after compilationThe target quantum circuit C ₁ The number of levels included is greater than or equal to the initial quantum circuit C ₀ The number of levels involved.

In a specific example of the presently disclosed subject matter, the target quantum circuit C ₁ The quantum gate included in (1) is a native quantum gate which can be realized by the superconducting quantum chip.

based on preset segmentation rules, the target quantum circuit C is segmented ₁ Middle L _j The layer is cut to obtain the L < th > layer _j Circuit subsystems corresponding to the layers;

based on the obtained L _j The circuit subsystems corresponding to the layers divide the undirected graph representing the superconducting quantum chip to obtain the L < th > graph _j Hardware subsystems corresponding to the layers;

determining the L < th > of _j Layer-corresponding ith hardware subsystem k _jl Unitary matrix of sub-evolution

Wherein the sub-evolution unitary matrix

Said L < th > being obtained for simulation _j The L-th hardware subsystem corresponding to the layer executes the L-th hardware subsystem _j Evolution of quantum state after the first circuit subsystem corresponding to the layer;

based on the L < th > of _j Sub-evolution unitary matrix of l hardware subsystem corresponding to layer

In a specific example of the present disclosure, the preset segmentation rule includes at least one of:

will L _j The layer contains logic quantum bit with quantum gate function and adjacent logic quantum bit with quantum gate function in the range of distance d as Lth _j A circuit subsystem of a layer;

will L _j Logical qubits of inactive quantum gates in a layer as Lth _j The circuit subsystems of the layers.

In a specific example of the disclosed solution, the L < th > result is based on _j The circuit subsystem corresponding to the layer is used for carrying out segmentation processing on the undirected graph representing the superconducting quantum chip to obtain the L < th > graph _j A hardware subsystem corresponding to a layer, comprising at least one of:

l th _j In the layer, a physical qubit corresponding to the logical qubit acted by the quantum gate, an adjacent physical qubit of the physical qubit within a distance d, and a hardware subsystem formed by associated coupling devices, wherein the associated coupling devices are coupling devices for coupling the physical qubit corresponding to the quantum gate and/or the adjacent physical qubit;

l th _j In the layer, the hardware subsystem is formed by the physical quantum bit corresponding to the logic quantum bit of the unused quantum gate.

In a specific example of the disclosure, the first processing unit is specifically configured to assign the lth instruction to the first processing unit _j Carrying out tensor product processing on the sub evolution unitary matrix of each hardware subsystem corresponding to the layer to obtain a target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

In a specific example of the disclosed solution, the second processing unit is specifically configured to be based on the target quantum circuit C ₁ Order of intermediate levels, the target quantum circuit C ₁ Performing product processing on the layer evolution unitary matrix corresponding to each middle layer to obtain the target quantum circuit C ₁ Of the overall evolution unitary matrix

For a description of specific functions and examples of each unit of the classical computing device in the embodiments of the present disclosure, reference may be made to the relevant description of the corresponding step in the above method embodiments, and details are not repeated here.

The present disclosure also provides an electronic device, a readable storage medium, and a computer program product according to embodiments of the present disclosure.

FIG. 12 shows a schematic block diagram of an example electronic device 1200, which can be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 12, the apparatus 1200 includes a computing unit 1201 which can perform various appropriate actions and processes in accordance with a computer program stored in a Read Only Memory (ROM)1202 or a computer program loaded from a storage unit 1208 into a Random Access Memory (RAM) 1203. In the RAM1203, various programs and data required for the operation of the device 1200 may also be stored. The computing unit 1201, the ROM 1202, and the RAM1203 are connected to each other by a bus 1204. An input/output (I/O) interface 1205 is also connected to bus 1204.

Various components in the device 1200 are connected to the I/O interface 1205 including: an input unit 1206 such as a keyboard, a mouse, or the like; an output unit 1207 such as various types of displays, speakers, and the like; a storage unit 1208 such as a magnetic disk, optical disk, or the like; and a communication unit 1209 such as a network card, modem, wireless communication transceiver, etc. The communication unit 1209 allows the device 1200 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The computing unit 1201 may be a variety of general purpose and/or special purpose processing components having processing and computing capabilities. Some examples of the computing unit 1201 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. The calculation unit 1201 performs the respective methods and processes described above, such as the simulation method. For example, in some embodiments, the simulation method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 1208. In some embodiments, part or all of a computer program may be loaded onto and/or installed onto device 1200 via ROM 1202 and/or communications unit 1209. When the computer program is loaded into the RAM1203 and executed by the computing unit 1201, one or more steps of the simulation method described above may be performed. Alternatively, in other embodiments, the computing unit 1201 may be configured to perform the simulation method in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user may provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server combining a blockchain.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be executed in parallel, sequentially or in different orders, and are not limited herein as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved.

The above detailed description should not be construed as limiting the scope of the disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method of simulation, comprising:

Wherein the layer evolution unitary matrix

2. The method of claim 1, further comprising:

based on the preset compiling rule, the initial quantum circuit C is subjected to ₀ Compiling to obtain the target quantum circuit C ₁ (ii) a Wherein the preset compiling rule satisfies at least one of the following conditions:

in the simulation process, the problem of crosstalk caused by coupling effect between physical quantum bits in the superconducting quantum chip when quantum gates in the target quantum circuit operate simultaneously can be solved;

3. The method of claim 2, wherein,

the preset compiling rule comprises the target quantum circuit C obtained after compiling ₁ L of (1) _j The layers satisfy: the intersection of adjacent logical qubits of any two qubits within a distance d equals the empty set.

4. The method of claim 2 or 3, wherein the compiled target quantum circuit C ₁ The number of the included levels is larger than or equal to the initial quantum circuit C ₀ The number of levels involved.

5. The method of any one of claims 1 to 4, wherein the target quantum circuit C ₁ The quantum gate included in (1) is a native quantum gate which can be realized by the superconducting quantum chip.

6. The method of any of claims 1 to 5, further comprising:

based on the obtained L _j The circuit subsystems corresponding to the layers divide the undirected graph characterizing the superconducting quantum chip to obtain the L < th > graph _j Hardware subsystems corresponding to the layers;

Wherein the sub-evolution unitary matrix

Said L < th > obtained for simulation _j The L-th hardware subsystem corresponding to the layer executes the L-th hardware subsystem _j Evolution of quantum state after the first circuit subsystem corresponding to the layer;

wherein the definite target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

The method comprises the following steps:

7. The method of claim 6, wherein the preset slicing rule comprises at least one of:

8. The method of claim 7, wherein the L-th score is based on the obtained score _j The circuit subsystems corresponding to the layers divide the undirected graph representing the superconducting quantum chip to obtain the L < th > graph _j A hardware subsystem corresponding to a layer, comprising at least one of:

l th _j Physical qubits corresponding to logical qubits acted on by the qubits, neighboring physical qubits within a distance d of the physical qubits, and hardware subsystems formed by associated coupling devices in the layer, wherein the associated couplingsThe device is a coupling device used for coupling the physical quantum bit corresponding to the quantum gate and/or the adjacent physical quantum bit;

9. The method of any of claims 6 to 8, wherein the basing is based on the lth _j Sub-evolution unitary matrix of l hardware subsystem corresponding to layer

The method comprises the following steps:

subjecting the L th _j Carrying out tensor product processing on the sub evolution unitary matrix of each hardware subsystem corresponding to the layer to obtain a target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

10. The method of any one of claims 1 to 9, wherein the target-based quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

The method comprises the following steps:

based on the target quantum circuit C ₁ Order of middle hierarchy, the target quantum circuit C ₁ Multiplying the layer evolution unitary matrix corresponding to each layerProcessing to obtain the target quantum circuit C ₁ Of the overall evolution unitary matrix

11. A classic computing device, comprising:

Wherein the layer evolution unitary matrix

Obtaining the target quantum circuit C ₁ Total evolution unitary matrix of

12. The classic computing device of claim 11, wherein the first processing unit is further to:

based on the preset compiling rule, the initial quantum circuit C is processed ₀ Compiling to obtain the target quantum circuit C ₁ (ii) a Wherein the preset compiling rule satisfies at least one of the following conditions:

13. The classical computing device according to claim 12, wherein the pre-set compilation rule comprises the compiled target quantum circuit C ₁ L in (1) _j The layers satisfy: the intersection of adjacent logical qubits of any two qubits within a distance d equals the empty set.

14. Classical computing device according to claim 12 or 13, wherein the compiled target quantum circuit C ₁ The number of levels included is greater than or equal to the initial quantum circuit C ₀ The number of levels involved.

15. The classical computing device according to any one of claims 11 to 14, wherein the target quantum circuit C ₁ The quantum gate included in (1) is a native quantum gate which can be realized by the superconducting quantum chip.

16. The classic computing device of any of claims 11-15, wherein the first processing unit is further to:

Wherein the sub-evolution unitary matrix

based on the L < th > L _j Sub-evolution unitary matrix of l hardware subsystem corresponding to layer

17. The classic computing device of claim 16, wherein the preset slicing rules comprise at least one of:

will be L to _j The layer contains logic quantum bit with quantum gate function and adjacent logic quantum bit with quantum gate function in the range of distance d as Lth _j A circuit subsystem of a layer;

will be L to _j Logical qubits of inactive quantum gates in a layer as Lth _j The circuit subsystems of the layers.

18. The classic computing device of claim 17, wherein the lth based on the derivation _j The circuit subsystems corresponding to the layers divide the undirected graph representing the superconducting quantum chip to obtain the L < th > graph _j A hardware subsystem corresponding to a layer, comprising at least one of:

l th _j Physical qubits corresponding to logical qubits acted on by the qubits, adjacent physical qubits of the physical qubits within a distance d, and associated coupling device shapesThe hardware subsystem is formed, wherein the related coupling device is a coupling device for coupling the physical qubit corresponding to the quantum gate and/or the adjacent physical qubit;

19. Classical computing device according to any one of claims 16 to 18, wherein said first processing unit is specifically configured to assign said lth _j Carrying out tensor product processing on the sub evolution unitary matrix of each hardware subsystem corresponding to the layer to obtain a target quantum circuit C ₁ Middle L _j Layer evolution unitary matrix corresponding to layers

20. Classical computing device according to any of claims 11 to 19, wherein the second processing unit, in particular for basing on the target quantum circuit C ₁ Order of middle hierarchy, the target quantum circuit C ₁ Performing product processing on the layer evolution unitary matrix corresponding to each middle layer to obtain the target quantum circuit C ₁ Of the overall evolution unitary matrix

21. An electronic device, comprising:

at least one processor; and

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-10.

22. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-10.

23. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1-10.