CN114925000A - Address translation method, electronic device and electronic equipment - Google Patents

Abstract

An address translation method, an electronic device and an electronic apparatus. The address translation method comprises the following steps: acquiring a target address to be converted; generating a read page table request using the target address and issuing the read page table request over the first interconnect; enabling the page table query unit to receive a page table reading request sent by a first interconnection, and querying at least one page table step by step from the storage device according to the page table reading request to obtain a first address corresponding to the target address; and enabling the page table query unit to return the queried first address through the first interconnection. According to the address translation method, the page table query unit reads the page table from the storage device without the bus or on-chip interconnection, or reads the page table from the storage device by fewer buses or on-chip interconnections, so that the time delay of reading the page table from the storage device by the buses or on-chip interconnections is reduced, and the efficiency of address translation is improved.

Description

Address translation method, electronic device and electronic equipment

Technical Field

Embodiments of the present disclosure relate to an address translation method, an electronic device, and an electronic apparatus.

Background

In the field of computer technology, a programmer may write a program using an arbitrary Virtual Address (VA) within a system specification range, instead of a physical Address, and a Central Processing Unit (CPU) executes an application program using the Virtual Address. Different processes running in the system are generally assigned different virtual address spaces, and the virtual address space of each process covers a larger range. For example, when a process allocates a memory to the process and accesses the memory, a virtual Address needs to be mapped to a Physical Address (PA), and the Physical Address is a real Physical memory access Address. The differentiated use of virtual addresses and physical addresses has become a mainstream trend in the industry.

Disclosure of Invention

At least one embodiment of the present disclosure provides an address translation method, including: acquiring a target address to be converted; generating a read page table request using the target address and issuing the read page table request over a first interconnect; enabling a page table query unit to receive the read page table request sent by the first interconnection, and querying at least one page table step by step from a storage device according to the read page table request to obtain a first address corresponding to the target address; and enabling the page table query unit to return the queried first address through the first interconnection.

For example, in an address translation method provided by at least one embodiment of the present disclosure, generating the read page table request using the target address is performed in a case where the first address corresponding to the target address is not cached in a memory management unit that performs address translation.

For example, in an address translation method provided by at least one embodiment of the present disclosure, the first interconnect includes a first interconnect unit, the read page table request is issued through the first interconnect unit, and the read page table request issued through the first interconnect unit is received.

For example, in an address translation method provided in at least one embodiment of the present disclosure, the first interconnect unit includes a bus or an on-chip interconnect.

For example, in an address translation method provided in at least one embodiment of the present disclosure, the first interconnect further includes a second interconnect unit and a third interconnect unit, and the first interconnect unit communicates with the third interconnect unit through the second interconnect unit; and sending the page table reading request sequentially through the first interconnection unit, the second interconnection unit and the third interconnection unit.

For example, in an address translation method provided in at least one embodiment of the present disclosure, the page table read request sequentially sent through the third interconnect unit, the second interconnect unit, and the first interconnect unit is received.

For example, in an address translation method provided in at least one embodiment of the present disclosure, the second interconnection unit includes an inter-die connection, and the third interconnection unit includes a bus or an on-die interconnection.

For example, in an address translation method provided by at least one embodiment of the present disclosure, the step-by-step querying of at least one page table to obtain a first address corresponding to the target address and the generating of the read page table request using the target address are performed in different dies, respectively.

For example, in an address translation method provided in at least one embodiment of the present disclosure, the target address is a virtual address, and the first address is a physical address; or, the target address is a virtual address, and the first address is an intermediate physical address; or, the target address is an intermediate physical address, and the first address is a physical address.

At least one embodiment of the present disclosure further provides an electronic device, including: a first interconnect; a memory management unit coupled with the first interconnect and configured to: obtaining a target address, generating a read page table request using the target address, and issuing the read page table request over the first interconnect; a page table walk unit coupled to the first interconnect and configured to: receiving the page table reading request sent by the first interconnection, inquiring at least one page table step by step from a storage device according to the page table reading request to obtain a first address corresponding to the target address, and returning the inquired first address to the storage management unit through the first interconnection.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the storage management unit is a system storage management unit.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the page table walk unit corresponds to a plurality of different storage management units.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the memory management unit and the page table walk unit are respectively located in different dies, and the first interconnect includes an inter-die connection.

At least one embodiment of the present disclosure further provides an electronic device, which includes the electronic apparatus provided in any embodiment of the present disclosure, and the electronic device further includes the storage device, where the storage device is configured to store a multi-level page table.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the page table walk unit is further configured to directly access the storage device or be coupled to the storage device through another interconnect, where the another interconnect is different from the first interconnect.

For example, in an electronic device provided in at least one embodiment of the present disclosure, for a case where the page table walk unit directly accesses the storage apparatus, the storage apparatus includes a storage controller that includes the page table walk unit, or the storage apparatus includes a cache that includes the page table walk unit.

For example, in an electronic device provided in at least one embodiment of the present disclosure, the storage device is a double rate synchronous dynamic random access memory.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 is a schematic diagram of the operation of a system memory management unit;

fig. 2 is a flowchart illustrating an address translation method according to at least one embodiment of the disclosure;

FIG. 3 is a schematic view of an example of steps S10 to S30 in FIG. 2;

fig. 4 is a schematic diagram of an example of step S40 in fig. 2;

FIG. 5 is a schematic view illustrating an example of steps S10 to S40 in FIG. 2;

FIG. 6 is a schematic view showing another example of steps S10 to S40 in FIG. 2;

fig. 7 is a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure;

fig. 8 is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

fig. 9 is a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure; and

fig. 10 is a schematic block diagram of still another electronic device provided in at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The present disclosure is illustrated below by means of several specific examples. Detailed descriptions of known functions and known components may be omitted in order to keep the following description of the embodiments of the present disclosure clear and concise. When any component of an embodiment of the present disclosure appears in more than one drawing, that component is identified in each drawing by the same or similar reference numeral.

A Memory Management Unit (MMU) provides translation from virtual addresses to physical addresses in a computer system between an execution Unit (e.g., a CPU or a processor core of a CPU) and Memory. The process of going from a virtual address to a physical address is called address translation (or mapping). For example, data/instruction addresses, etc. behind the execution of the user program are virtual addresses that are issued by the execution unit, intercepted by the MMU, and translated into physical addresses. The MMU may also have other functions such as memory attribute translation, permission checking, and the like.

A System Memory Management Unit (SMMU) is widely used in various systems on Chip (SoC), and is interposed between an I/O peripheral and, for example, a bus, and is also used as a Memory Management Unit, mainly for converting a virtual address to a physical address of the peripheral, that is, converting the virtual address into a corresponding physical address.

The rules for translation of virtual addresses to physical addresses (mapping rules) are stored in page tables, which are stored in the storage of the system. The MMU (e.g., SMMU) includes a Page table walk Unit (PWU) and a Translation Lookaside Buffer (TLB). In order to realize the translation from a virtual address to a physical address, the MMU firstly searches the TLB to see whether the corresponding physical address is cached in the TLB, if the TLB has (hit), the translation is directly completed, and if the TLB does not have (miss), the MMU needs to search a page table for translation by the PWU using a storage device (e.g., Double Data Rate SDRAM (DDR)) with the virtual address going to the system once or multiple times, and finally obtains the physical address corresponding to the virtual address, thereby realizing the access operation to the physical address.

FIG. 1 is a schematic diagram of a system memory management unit. As shown in fig. 1, a pre-designed circuit function module applied to an Application Specific Integrated Circuit (ASIC) or an editable logic device (FPGA) is called an Intellectual Property Core (IP Core), or IP. The IP may be any logic module or functional module used in ASIC or FPGA, such as a filter, a memory controller, an interface program, etc., and the IP core is used to refer to the circuit functional module in the present disclosure, and the embodiments of the present disclosure do not limit the specific function, structure, etc. of the circuit functional module.

For example, as shown in fig. 1, taking SMMU as an example, when IP is to perform, for example, read-write access, a virtual address VA to be accessed is issued first; after receiving the virtual address VA, the SMMU needs to perform a translation from the virtual address to a physical address, and in order to perform the translation, the SMMU needs to read a page table from a DDR to an upper field (generally referred to as an index (index) portion) of the virtual address VA corresponding to the page table; after reading the contents of the page table, the SMMU converts the virtual address VA into the physical address PA and outputs the physical address PA by combining the contents of the page table with the lower field (usually called offset) of the virtual address VA corresponding to the offset address, and then continues the subsequent access operation with the physical address.

The behavior of SMMU to DDR read page Table, abbreviated as PTW (Page Table walking). In order to realize the translation of a virtual address VA to a physical address PA once, in the case of using a multi-level page table by an operating system, the SMMU needs to perform multiple PTW operations. For example, fig. 1 illustrates an example in which the common address bit width is 48 bits (bit), the page granularity is 4KB, and 4 page tables (page table 0 to page table 3) are shared. In this example, the upper 36 bits of the virtual address are the index portion and the lower 12 bits are the offset portion. The index portion includes 4 9-bit composition fields, which correspond to the page tables of level 0 to level 3, respectively, in order from the upper bits to the lower bits. After receiving the virtual address VA sent by the IP, the SMMU acquires an index portion in the virtual address VA, and based on fields corresponding to the page tables from the 0 th level to the 3 rd level, the SMMU needs to do PTWs 4 times in sequence (for example, named PTW0, PTW1, PTW2, and PTW3, respectively). For example, the SMMU makes a PTW that sends a page table read request and a corresponding address field to a Network-on-chip (NoC, as an example of an on-chip interconnect), and the NoC sends the page table read request to the DDR, and then accesses a corresponding page table (one of the page tables 0 to 3) in the DDR according to the page table read request, and retrieves the page table contents read from the page table from the DDR.

For example, as shown in fig. 1, PTW0 accesses the level 0 page table using the corresponding level 0 field according to the starting physical address of the multi-level page table, e.g., a page table base address register record, the page table contents retrieved from the level 0 page table being the memory address Addr0 of the level 1 page table to be accessed by PTW1 in DDR; PTW1 accesses the level 1 page table using the corresponding level 1 field, the page table contents retrieved from the level 1 page table being the memory address Addr1 of the level 2 page table PTW2 is to access in DDR; PTW2 accesses the level 2 page table using the corresponding level 2 field, the page table contents retrieved from the level 2 page table being the memory address Addr2 of the level 3 page table PTW3 is to access in DDR; the PTW3 accesses the 3 rd page table using the corresponding 3 rd field, and the page table contents retrieved from the 3 rd page table are the memory address (e.g., physical address) of the target page, and the memory address of the target page plus the offset part of the virtual address VA can obtain the physical address PA corresponding to the virtual address VA.

Therefore, in order to perform address translation to obtain the physical address PA from the virtual address VA, PTW0, PTW1, PTW2, and PTW3 need to be first performed and completed according to the index portion in the virtual address VA. SMMU goes through NoC and accesses DDR each time it does PTW, thus experiencing latency on NoC and latency to access DDR. For example, the delay on NoC is denoted by "NoC _ delay", and the delay for accessing DDR is denoted by "DDR _ delay". For the scheme shown in fig. 1, 4 PTWs are required for the SMMU to complete one translation from the virtual address VA to the physical address PA, and the total Delay0 required can be calculated at least as follows:

delay0 ═ 4 noc _ Delay +4 ddr _ Delay formula (1)

In a computer system, most communication processes among functional circuit modules need to pass through a bus or an on-chip interconnection (for example, NoC), the bus or the on-chip interconnection is busy, and a large amount of resource competition exists, so that delay generated on the bus or the on-chip interconnection by the SMMU is large when the PTW is done once. Therefore, it takes a lot of time for SMMU to read the page table every time the SMMU goes to the storage device, which results in a long time for the virtual address to physical address translation, thereby reducing the efficiency and performance of SoC.

At least one embodiment of the present disclosure provides an address translation method, including: acquiring a target address to be converted; generating a read page table request using the target address and issuing the read page table request over the first interconnect; enabling the page table query unit to receive a page table reading request sent by a first interconnection, and querying at least one page table step by step from the storage device according to the page table reading request to obtain a first address corresponding to the target address; and enabling the page table query unit to return the queried first address through the first interconnection.

At least one embodiment of the present disclosure further provides an electronic device corresponding to the method for performing address translation.

At least one embodiment of the present disclosure further provides an electronic device corresponding to the electronic apparatus.

In the address translation method, the electronic device, and the electronic apparatus provided in at least one embodiment of the present disclosure, in the process of performing address translation, the page table lookup unit reads the page table from the storage device without passing through the bus or the on-chip interconnect, or reads the page table from the storage device with fewer buses or on-chip interconnects, so that a delay of reading the page table from the storage device by the bus or the on-chip interconnect is reduced, the efficiency of address translation is improved, and the efficiency and performance of, for example, an SoC are improved.

At least one embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements already described.

Fig. 2 is a flowchart illustrating an address translation method according to at least one embodiment of the present disclosure.

For example, as shown in fig. 2, at least one embodiment of the present disclosure provides an address translation method for performing address translation in a computer system, for example, translating a virtual address into a physical address, so that a target address can be accessed by using the translated physical address, where the target address can point to a storage address in a storage device, for example, and can point to a certain functional circuit module in the computer system, such as a Direct Memory Access (DMA) unit, a PCIE device, and the like. For example, the computer system includes at least one Memory Management Unit (MMU) (e.g., SMMU) and a page table access unit (PWU) that is disposed independently of the MMU, e.g., the page table access unit is coupled to, and communicates with, the memory management unit via an interconnect, and is no longer part of, or directly coupled to, the MMU, and therefore is not disposed within the memory management unit. The above address translation method may be performed by a memory management unit and a page table access unit. As shown in FIG. 2, the address conversion method includes the following steps S10-S40.

Step S10: acquiring a target address to be converted;

step S20: generating a read page table request using the target address and issuing the read page table request over the first interconnect;

step S30: enabling the page table query unit to receive a page table reading request sent by the first interconnection, and querying at least one page table step by step from the storage device according to the page table reading request to obtain a first address corresponding to the target address;

step S40: and enabling the page table query unit to return the queried first address through the first interconnection.

For example, the storage management unit is used in the system as a whole to perform the conversion from the target address to the first address in the above-described steps S10 to S40, and the conversion operation is further performed by means of the PWU in this process. For example, the storage management unit may be an SMMU, which may further include, for example, a TLB; in other embodiments, the storage management unit may also be other electronic components capable of implementing an address translation function, which is not limited in this embodiment of the disclosure.

For example, the target address is a virtual address to be translated, and the first address is a physical address; or, the target Address is a virtual Address to be converted, and the first Address is an Intermediate Physical Address (IPA); or, the target address is an intermediate physical address to be translated, and the first address is a physical address.

For example, the intermediate physical address PA is a concept introduced after the virtualization of a computer. For computer systems that support virtualization, each virtual machine system (guest OS) cannot directly map virtual addresses VA to physical addresses PA of the entire system, but rather to a restricted physical address space. Therefore, in the computer system supporting virtualization, the virtual machine system (guest OS) is responsible for mapping the virtual address VA to the intermediate physical address PA, and the virtual machine monitor (Hypervisor) is responsible for mapping the intermediate physical address PA to the specific physical address PA, and address translation operations are respectively involved from the virtual address VA to the intermediate physical address PA and from the intermediate physical address PA to the physical address PA, and can be performed by the address translation method according to at least one embodiment of the present disclosure.

For example, generating a read page table request using a target address is performed in the event that the first address corresponding to the target address is not cached in the TLB of the memory management unit performing the address translation. For example, when the storage management unit performs translation of a target address to a first address, if the first address corresponding to the target address is cached in the TLB of the storage management unit, the storage management unit does not generate a read page table request, but directly completes translation of the target address to the first address inside the TLB of the storage management unit; if the first address corresponding to the target address is not cached in the TLB of the storage management unit, the storage management unit generates a read page table request and performs address translation, for example, in steps S10-S40.

For example, in at least one embodiment, a computer system may include multiple memory management units and at least one page table walk unit independent of the memory management units, e.g., each page table walk unit may be used for a corresponding memory management unit and may also be used for a corresponding plurality of different memory management units, i.e., multiple memory management units may share, for example, one page table walk unit.

For example, in at least one embodiment, the memory management unit and the page table walk unit may be located in the same die (die), which are coupled to, and communicate with, each other through on-chip interconnects; in at least one embodiment, the memory management unit and the page table walk unit may also be located in different dies (die), respectively, and the first interconnect for coupling, communicating with, the memory management unit and the page table walk unit includes a die-to-die connection (D2D).

FIG. 3 is a schematic view of an example of steps S10 to S30 in FIG. 2; fig. 4 is a schematic diagram of an example of step S40 in fig. 2.

For example, as shown in fig. 3, in step S10, the storage management unit 110 acquires an access request to the target address 101 issued by the IP or processor (IP/CPU)300, thereby generating an address conversion request to the target address. In step S20, the memory management unit 110 generates a read page table request 102 using the target address 101. Taking the example of the system using n-level page tables, that is, taking the example of the memory management unit 110 needing to read the page table n times into the memory device 200, the read page table request 102 includes PTW0, PTW1, … …, and PTWn-1; the memory management unit 110 issues a read page table request 102 to a remote page table walk unit 130 via a first interconnect 120. In step S30, the page table walk unit 130 receives the read page table request 102 from the memory management unit 110 via the first interconnect 120, and walks at least one page table (i.e., n is greater than or equal to 1, e.g., n is equal to 3 or 4) in stages from the memory device 200 according to the read page table request 102 to obtain the first address corresponding to the target address 101. For example, in the case where the target address is a virtual address, the first address may be a physical address or an intermediate physical address.

For example, as shown in fig. 3, the process of the page table walk unit 130 walking through at least one page table from the storage device 200 to obtain the first address corresponding to the target address 101 is as follows: PTW0 accesses the level 0 page table using the corresponding level 0 field according to the starting physical address of the multi-level page table, e.g. as recorded by the page table base address register, the page table contents retrieved from the level 0 page table being the memory address Addr0 of the level 1 page table to be accessed by PTW1 in DDR; PTW1 accesses the level 1 page table using the corresponding level 1 field, the page table contents retrieved from the level 1 page table being the memory address Addr1 of the level 2 page table PTW2 is to access in DDR; PTW2 accesses the level 2 page table using the corresponding level 2 field, the page table contents retrieved from the level 2 page table being the memory address Addr2 of the level 3 page table PTW3 is to access in DDR; … …, respectively; PTWn-1 uses the corresponding n-1 level field to access the n-1 level page table, the page table content retrieved from the n-1 level page table is the memory address of the target page table, and the memory address of the target page table plus the offset part in the virtual address VA can obtain the first address corresponding to the target address.

For example, as shown in fig. 4, in step S40, the page table walk unit 130 returns the result (here, the first address) of the walk of the multi-level page table 103(Addr0/Addr1/… …/Addr n-2/first address) to the memory management unit 110 at once via the first interconnect 120; the storage management unit 110 outputs the obtained first address 1031 for a subsequent operation (such as accessing a storage device or a peripheral device), thereby completing the conversion of the target address 101 to the first address 1031 in fig. 3.

For example, the target address 101 is a virtual address VA, and the first address 1031 is a physical address PA; or, the target address 101 is a virtual address VA, and the first address 1031 is an intermediate physical address IPA; alternatively, target address 101 is intermediate physical address IPA and first address 1031 is physical address PA.

For example, the memory management unit 110 generates the read page table request 102(PTW0, PTW1, … …, PTWn-1) using the target address 101 in the case where the first address 1031 corresponding to the target address 101 is not cached in the memory management unit 110 (e.g., in the TLB) that performs address translation. For example, when the memory management unit 110 performs the translation of the target address 101 to the first address 1031, if the first address 1031 corresponding to the target address 101 is already cached in the memory management unit 110 (e.g., TLB), the memory management unit 110 does not generate the read page table request 102 but directly completes the translation of the target address 101 to the first address 1031 inside the memory management unit 110; if the first address 1031 corresponding to the target address 101 is not cached in the storage management unit 110, the storage management unit 110 generates the read page table request 102 and performs address translation in, for example, steps S10 to S40.

For example, as shown in fig. 3 and fig. 4, in an address translation method provided in at least one embodiment of the present disclosure, the storage management unit 110 may obtain the first address 1031 by directly querying the multi-level page table 103 from the storage device 200 through the page table querying unit 130 as long as it issues the read page table request 102 once. For example, the latency on the first interconnect 120 is denoted by "noc _ delay" and the latency of accessing the memory device 200 is denoted by "ddr _ delay". PTW is required n times by the storage management unit 110 to complete one conversion from the target address 101 to the first address 1031, and the total Delay1 required can be expressed as:

delay1 ═ 1 × noc _ Delay + n × ddr _ Delay equation (2)

Comparing equation (2) with equation (1), taking n-4 as an example, Delay1 reduces the latency of reading the page table from memory device 200 by first interconnect 120 3 times (3 × noc _ Delay) compared to Delay0 compared to the scheme in fig. 1.

Therefore, the page table walk unit 130 can read the page table from the storage device 200 directly to obtain the first address 1031 without passing through the first interconnect 120, so as to reduce the latency of the first interconnect 120 reading the page table from the storage device 200, improve the conversion efficiency of the target address 101 to the first address 1031, and improve the efficiency and performance of, for example, the SoC.

In another example of the above embodiment, the memory management unit itself may comprise, for example, a level 0 page table and the memory management unit itself also has (at least partial) page table walk functionality, then the memory management unit may, for an initial read page table request generated based on the target address, the PTW0 may be executed directly locally (i.e., within the memory management unit), followed by a further read page table request using the obtained memory address Addr0 of the level 1 page table obtained by querying the level 0 page table, the target address (or the remaining address portion of the target address except for the fields corresponding to the level 0 page table), etc., which is sent to a page table walk unit independent of the memory management unit for a subsequent page table walk operation, resulting in a first address corresponding to the target address, which is returned to the memory management unit. This example can also reduce the latency incurred in querying the page table due to operations over the first interconnect, thereby improving, for example, the efficiency and performance of the SoC.

FIG. 5 is a schematic view illustrating an example of steps S10 to S40 in FIG. 2; fig. 6 is a schematic diagram illustrating another example of steps S10 to S40 in fig. 2.

For example, the operation of "generating a read page table request using a target address" in step S20 and the operation of "sequentially consulting at least one page table to obtain a first address corresponding to the target address" in step S30 may be performed in one die (die) or performed in different dies (die), respectively. For example, fig. 5 shows a case where the two operations are performed in one die (die), where the memory management unit 110 and the page table walk unit 130 are located in the same die (die), and are coupled and communicate with each other through a first interconnect; for example, fig. 6 shows a case where the two operations are performed in different dies (die), and the memory management unit 110 and the page table walk unit 130 are located in different dies (die), and are coupled and communicate with each other through the first interconnect and other interconnects.

For example, as shown in fig. 5, the first interconnection 120 includes a first interconnection unit 121. The memory management unit 110 issues the read page table request 102 via the first interconnect unit 121, and the page table walk unit 130 receives the read page table request 102 issued via the first interconnect unit 121.

For example, as shown in fig. 5, in step S10, the storage management unit 110 acquires the destination address 101 issued by the IP/CPU 300. In step S20, the storage management unit 110 generates a read page table request 102(PTW0, PTW1, … …, PTWn-1) using the target address 101; the memory management unit 110 issues a read page table request 102 via the first interconnect unit 121. In step S30, the page table walk unit 130 receives the read page table request 102 issued via the first interconnect unit 121, and walks at least one page table stage by stage from the storage device 200 according to the read page table request 102 to obtain the first address corresponding to the target address 101. In step S40, the page table walk unit 130 returns the multi-level page table 103(Addr0/Addr1/… …/Addr n-2/first address) obtained by the walk to the storage management unit 110 at a time via the first interconnect unit 121; the storage managing unit 110 outputs the obtained first address 1031, thereby completing the conversion of the target address 101 to the first address 1031.

For example, the first interconnection unit 121 may be a bus or an on-chip interconnection, or may also be other electronic elements capable of implementing an address transmission function, for example, the on-chip interconnection may be a network on chip (NoC), and the network on chip may be a cross (Switch) network, a ring (ring) network, a Tree (Tree) network, a Mesh (Mesh) network, a Torus (Torus) network, or the like, which is not limited in this embodiment of the disclosure.

For example, as shown in fig. 6, the first interconnection 120 further includes a second interconnection unit 122 and a third interconnection unit 123. The first interconnect unit 121 communicates with the third interconnect unit 123 via the second interconnect unit 122. For example, the memory management unit 110 sequentially sends the page table read request 102 through the first interconnect unit 121, the second interconnect unit 122, and the third interconnect unit 123, and the page table walk unit 130 receives the page table read request 102 sequentially sent through the third interconnect unit 123, the second interconnect unit 122, and the first interconnect unit 121.

For example, as shown in fig. 6, in step S10, the storage management unit 110 acquires the destination address 101 issued by the IP/CPU 300. In step S20, the storage management unit 110 generates a read page table request 102(PTW0, PTW1, … …, PTWn-1) using the target address 101; the memory management unit 110 sequentially issues the read page table request 102 through the first interconnect unit 121, the second interconnect unit 122, and the third interconnect unit 123. In step S30, the page table walk unit 130 receives the read page table request 102 sequentially issued through the third interconnect unit 123, the second interconnect unit 122, and the first interconnect unit 121, and walks at least one page table from the storage device 200 step by step according to the read page table request 102 to obtain the first address corresponding to the target address 101. In step S40, the page table walk unit 130 returns the searched multi-level page table 103(Addr0/Addr1/… …/Addr n-2/first address) to the storage management unit 110 in sequence through the third interconnect unit 123, the second interconnect unit 122, and the first interconnect unit 121 at a time; the storage managing unit 110 outputs the obtained first address 1031, thereby completing the conversion of the target address 101 to the first address 1031.

For example, the third interconnect unit 123 and the first interconnect unit 121 may be buses or on-chip interconnects, or may also be other electronic components capable of implementing an address transmission function, for example, the on-chip interconnects may be a network on chip (NoC), and the network on chip may be a cross (Switch) network, a ring (ring) network, a Tree (Tree) network, a Mesh (Mesh) network, a Torus (Torus) network, and the like, which is not limited in this embodiment of the disclosure; the second interconnection unit 122 includes inter-wafer connections (D2D), or may be other electronic components capable of implementing connection functions between different wafers (die), which is not limited by the embodiment of the disclosure.

Fig. 7 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.

For example, as shown in fig. 7, the electronic device 100 includes a first interconnect 120, a memory management unit 110, and a page table walk unit 130, which may perform an address translation method according to any embodiment of the present disclosure. The memory management unit 110 is coupled to the first interconnect 120 and is configured to: acquiring a target address 101; generating a read page table request 102 using a target address 101; and a read page table request 102 via a first interconnect 120. The page table walk unit 130 is coupled to the first interconnect 120 and configured to: receiving a page table read request 102 sent via the first interconnect 120, querying at least one page table from the storage device stage by stage according to the page table read request 102 to obtain a first address 1031 corresponding to the target address 102, and returning a queried multi-stage page table 103 to the storage management unit 110 via the first interconnect 120; the storage managing unit 110 outputs the obtained first address 1031, thereby completing the conversion of the target address 101 to the first address 1031.

Likewise, in this embodiment, for example, the storage management unit 110 may be an SMMU, or may be other electronic components capable of implementing an address translation function, and the embodiment of the present disclosure is not limited thereto. For example, the memory management unit 110 and the page table walk 130 unit may be located in the same die (die); or may be located in different wafers (die), respectively, and the first interconnect comprises an inter-wafer connection (D2D). For example, the page table walk unit 130 can be used in the same memory management unit 110, or can be used in a plurality of different memory management units 110.

Fig. 8 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.

For example, as shown in fig. 8, the electronic device 10 includes an electronic apparatus 100 and a storage apparatus 200 as shown in fig. 7, for example. The storage device 200 is configured to store multi-level page tables, including the multi-level page table 103(Addr0/Addr1/… …/Addr n-2/first address) queried by the page table querying unit 130 in fig. 3 to 6.

For example, as shown in fig. 8, the electronic device 100 obtains a target address 101, generates a read page table request 102 using the target address 101, and obtains a multi-level page table 103 by looking up from the storage device 200 according to the read page table request 102 to obtain a first address 1031 corresponding to the target address 102. The electronic apparatus 100 outputs the obtained first address 1031, thereby completing the conversion of the target address 101 to the first address 1031.

For example, the memory apparatus 200 may include a DDR, and may also be other memory devices capable of storing a multi-level page table, which is not limited by the embodiment of the present disclosure.

For example, in the electronic apparatus 10 shown in fig. 8, the page table walk unit 130 of the electronic device 100 is further configured to directly access the storage device 200 or to be coupled with the storage device 200 through another interconnect (not shown), which is different from the first interconnect 120.

For example, in the case where the page table walk unit 130 is coupled to the memory device 200 through another interconnect different from the first interconnect 120, the process of accessing the memory device 200 by the page table walk unit 130 does not pass through the first interconnect 120, so that the latency of reading the page table from the memory device 200 by the first interconnect 120 is reduced, thereby improving the efficiency of the translation of the target address 101 to the first address 1031.

Fig. 9 is a schematic block diagram of another electronic device provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 9, in the case where the page table walk unit 130 directly accesses the memory device 200, the page table walk unit 130 may be integrated into the memory device 200, and thus the memory device 200 may be directly accessed without passing through another bus or on-chip interconnect. At this time, the process of accessing the memory device 200 by the page table walk unit 130 also does not go through the first interconnect 120, so that the latency of the first interconnect 120 reading the page table from the memory device 200 is reduced, and the efficiency of converting the target address 101 to the first address 1031 is improved.

For this case, the storage device 200 may include, for example, a Memory Controller (MC) including the page table walk unit 130, that is, the page table walk unit 130 is integrated in the memory controller, the memory controller is used to manage read and write operations to the storage device, and the like; alternatively, the storage 200 may include, for example, a cache (cache) including the page table walk unit 130; alternatively, the page table walk unit 130 may be integrated in other components in the storage device 200, and the embodiment of the disclosure is not limited in this respect.

Fig. 10 is a schematic block diagram of another electronic device provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 10, the electronic device 400 is, for example, suitable for implementing the address translation method provided by the embodiment of the present disclosure. The electronic device 400 may be a terminal device or a server or the like. It should be noted that the electronic device 400 shown in fig. 10 is only one example, and does not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

For example, as shown in fig. 10, the electronic device 400 may include a processing apparatus (e.g., a central processing unit, a graphics processor, etc.) 41 that may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM)42 or a program loaded from a storage apparatus 48 into a Random Access Memory (RAM) 43. In the RAM 43, various programs and data necessary for the operation of the electronic apparatus 400 are also stored. The processing device 41, the ROM 42, and the RAM 43 are connected to each other via a bus 44. An input/output (I/O) interface 45 is also connected to bus 44. Generally, the following devices may be connected to the I/O interface 45: input devices 46 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, or the like; an output device 37 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage devices 48 including, for example, magnetic tape, hard disk, etc.; and a communication device 49. The communication means 49 may allow the electronic device 400 to communicate with other electronic devices wirelessly or by wire to exchange data. While fig. 10 illustrates an electronic device 400 having various means, it is to be understood that not all illustrated means are required to be implemented or provided, and that the electronic device 400 may alternatively be implemented or provided with more or less means.

For a detailed description and technical effects of the electronic device 10/400, reference may be made to the description of the electronic apparatus above, which is not repeated herein.

For the present disclosure, there are several points to be explained:

(1) in the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to general designs.

(2) Features of the disclosure in the same embodiment and in different embodiments may be combined with each other without conflict.

The above is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and shall be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (17)

1. An address translation method, comprising:

acquiring a target address to be converted;

generating a read page table request using the target address and issuing the read page table request over a first interconnect;

enabling a page table query unit to receive the read page table request sent by the first interconnection, and querying at least one page table step by step from a storage device according to the read page table request to obtain a first address corresponding to the target address;

and enabling the page table query unit to return the queried first address through the first interconnection.

2. The method of claim 1, wherein generating the read page table request using the target address is performed in the event that the first address corresponding to the target address is not cached in a memory management unit performing address translation.

3. The method of claim 1, wherein the first interconnect comprises a first interconnect unit,

the method further includes issuing the read page table request via the first interconnect unit, and receiving the read page table request issued via the first interconnect unit.

4. The method of claim 3, wherein the first interconnect unit is a bus or an on-chip interconnect.

5. The method of claim 3, wherein the first interconnect further comprises a second interconnect unit and a third interconnect unit, the first interconnect unit communicating with the third interconnect unit via the second interconnect unit;

and sending the page table reading request sequentially through the first interconnection unit, the second interconnection unit and the third interconnection unit.

6. The method of claim 5, wherein the read page table request issued sequentially through the third interconnect unit, the second interconnect unit, and the first interconnect unit is received.

7. The method of claim 5, wherein the second interconnect unit comprises an inter-die connection and the third interconnect unit comprises a bus or an on-die interconnect.

8. The method of any of claims 5-7, wherein said generating said read page table request using said target address is performed in separate dies in association with said progressively consulting at least one page table to obtain a first address corresponding to said target address.

9. The method of claim 1, wherein the target address is a virtual address and the first address is a physical address; alternatively, the first and second electrodes may be,

the target address is a virtual address, and the first address is an intermediate physical address; alternatively, the first and second liquid crystal display panels may be,

the target address is an intermediate physical address, and the first address is a physical address.

10. An electronic device, comprising:

a first interconnect;

a memory management unit coupled with the first interconnect and configured to: obtaining a target address, generating a read page table request using the target address, and issuing the read page table request over the first interconnect;

a page table walk unit coupled to the first interconnect and configured to: receiving the page table reading request sent by the first interconnection, querying at least one page table from a storage device step by step according to the page table reading request to obtain a first address corresponding to the target address, and returning the queried first address to the storage management unit through the first interconnection.

11. The electronic device of claim 10, wherein the storage management unit is a system storage management unit.

12. The electronic device of claim 10, wherein the page table walk unit corresponds to a plurality of different storage management units.

13. The electronic device of claim 11, wherein the memory management unit and the page table walk unit are each located in a different die, and the first interconnect comprises an inter-die connection.

14. An electronic device comprising the electronic apparatus of any of claims 10-13, the electronic device further comprising the memory device, wherein the memory device is configured to store a multi-level page table.

15. The electronic device of claim 14, wherein the page table walk unit is configured to access the storage directly or to be coupled with the storage through another interconnect, wherein the other interconnect is different from the first interconnect.

16. The electronic device of claim 15, wherein, for the case where the page table walk unit directly accesses the storage device, the storage device comprises a storage controller that comprises the page table walk unit, or,

the storage device includes a cache including the page table walk unit.

17. The electronic device of claim 14, wherein the storage is a double rate synchronous dynamic random access memory.

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