CN114915358A

CN114915358A - Radio monitoring system, method, device and storage medium

Info

Publication number: CN114915358A
Application number: CN202210479230.5A
Authority: CN
Inventors: 陈富强; 张艳辉; 闫培树; 凌智; 霍岳恒; 窦晓洋; 孟维良; 张陆峰; 徐文慧; 陈继武; 尚晓华; 张光云; 陈玮玮; 刘冬
Original assignee: Chengdu Dechen Borui Technology Co ltd
Current assignee: Chengdu Dechen Borui Technology Co ltd
Priority date: 2022-05-06
Filing date: 2022-05-06
Publication date: 2022-08-16

Abstract

The invention provides a radio monitoring system, which comprises a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip and an upper computer, wherein the radio frequency front end is connected with the AD data acquisition module through a network; the radio frequency front end is used for receiving a signal to be analyzed through an antenna and processing the signal to be analyzed to obtain an intermediate frequency signal; the system comprises an AD data acquisition module, an FPGA processor, a DDR3 storage chip, a host computer, a human-computer interaction software, a user instruction, an FPGA processor and a frequency spectrum waveform display module, wherein the AD data acquisition module is used for converting an intermediate frequency signal into IQ data, the FPGA processor is used for storing the IQ data and playing back the IQ data based on a corresponding playback mode, carrying out frequency spectrum analysis on the IQ data in the playing back process, obtaining an analysis result and an analysis result, the DDR3 storage chip is used for storing the IQ data received by the FPGA processor, and the host computer is used for operating the human-computer interaction software, acquiring the user instruction based on the operating human-computer interaction software, issuing the user instruction to the FPGA processor and displaying the frequency spectrum waveform based on the analysis result.

Description

Radio monitoring system, method, device and storage medium

Technical Field

The present disclosure relates to the field of radio monitoring, and more particularly, to a radio monitoring system, method, apparatus, and storage medium.

Background

With the advancement of science and technology, the wireless communication industry has also been greatly developed. The increasingly complex radio environment drives the overall increase of radio monitoring systems towards the goals of higher sensitivity, more convenient product form and richer functions. For the spectrum analysis of radio signals, the aim is to spread the signals which are mutually overlapped and interleaved in the time domain to the frequency domain, and the signals of different frequency components are separated and further analyzed, so as to identify, position, measure and orient the signals.

Therefore, it is desirable to provide a radio monitoring system, a radio monitoring method, a radio monitoring apparatus, and a storage medium, which can realize controllable spectrum analysis speed, high-speed and large-capacity storage of IQ data, control storage management of IQ data through an FPGA processor, and perform constant-speed, fast-speed and slow-speed spectrum analysis on IQ data in a playback mode, better deal with signal search and detail expansion analysis, and further enrich the application scenarios of the radio monitoring system.

Disclosure of Invention

One or more embodiments of the present description provide a radio monitoring system, including a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, and an upper computer;

the radio frequency front end is in communication connection with the AD data acquisition module, and is used for receiving a signal to be analyzed through an antenna and performing at least one of amplification, filtering and frequency mixing on the signal to be analyzed to obtain an intermediate frequency signal;

the AD data acquisition module is in communication connection with the FPGA processor and is used for converting the intermediate frequency signal into IQ data and uploading the IQ data to the FPGA processor;

the FPGA processor is in communication connection with the DDR3 storage chip and the upper computer respectively, and is used for storing the IQ data, playing back the IQ data based on a corresponding playback mode, performing frequency spectrum analysis on the IQ data in the playback process, obtaining an analysis result and uploading the analysis result to the upper computer; the playback mode comprises at least one of a normal-speed spectrum analysis mode, a fast-speed spectrum analysis mode and a slow-speed spectrum analysis mode;

the DDR3 storage chip is used for storing the IQ data received by the FPGA processor, and a data source during playback of the FPGA processor comprises the IQ data stored by the DDR3 storage chip;

the upper computer is used for operating the human-computer interaction software, acquiring a user instruction based on the operation of the human-computer interaction software, issuing the user instruction to the FPGA processor, and displaying a frequency spectrum waveform based on the analysis result.

In some embodiments, the IQ data are stored sequentially within the DDR3 memory chip with reference to an acquisition timing sequence; the FPGA processor, in implementing the spectral analysis of the IQ data in the playback, is further configured to: acquiring the playback mode; reading a plurality of data packets according to the storage sequence of the IQ data in the DDR3 storage chip and referring to corresponding reading rules based on the playback mode; wherein each of the plurality of data packetsThe points and/or the lengths of the IQ data contained in the IQ data packets are the same, and the sum of the lengths of all the IQ data in the plurality of data packets does not exceed a preset storage length; the number of points of the IQ data included in each of the data packets is 2 ⁿ (ii) a And playing back the IQ data in the obtained data packets, and performing spectrum analysis on the IQ data in the playback.

In some embodiments, the read rule comprises a fetch interval value; the obtaining the playback mode further comprises obtaining the fetch interval value; the fetch interval value may be based on a length value or a point value representation of the IQ data; the value of the access interval represents the length value or the point value of the IQ data at the interval between the first IQ data in two adjacent data packets.

In some embodiments, when the playback mode is a constant-speed spectrum analysis mode, the fetch interval value is equal to a length value or a point value of the IQ data included in one data packet; when the playback mode is a fast spectrum analysis mode, the fetch interval value is greater than a length value or a point value of the IQ data contained in one data packet; when the playback mode is a slow spectrum analysis mode, the fetch interval value is smaller than a length value or a point value of the IQ data included in one data packet.

In some embodiments, the fetch interval value is determined based on a first predictive model, the first predictive model being a machine learning model, the first predictive model being configured to determine the fetch interval value based on at least one of a data acquisition rate, a transmission delay, a check error rate, a noise rate, a size and a number of MTUs.

In some embodiments, the preset storage length does not exceed a total length of the IQ data that the DDR3 memory chip can store.

In some embodiments, the preset storage length is determined based on a second prediction model, the first prediction model is a machine learning model, and the first prediction model is configured to determine the preset storage length based on at least one of data characteristics of the IQ data, the fetch interval value, a number of points of the IQ data included in one of the data packets, and characteristics of the AD data acquisition module.

In some embodiments, the FPGA processor and the DDR3 memory chips are connected by a PCIe interface.

In some embodiments, the AD data acquisition module is communicatively coupled to the FPGA processor via a jesd204b interface.

One or more embodiments of the present specification provide a radio monitoring method, which is implemented based on the FPGA processor in the foregoing radio monitoring system, and the radio monitoring method includes: receiving IQ data uploaded by the AD data acquisition module; storing the IQ data and sending the IQ data to the DDR3 storage chip; acquiring a playback mode and a reading rule based on the upper computer; reading a plurality of data packets from the DDR3 memory chip according to the playback mode and corresponding reading rules; playing back the IQ data in the obtained data packets, and performing spectrum analysis on the IQ data in the playback; and uploading the analysis result to the upper computer.

One or more embodiments of the present description provide a computer-readable storage medium storing computer instructions that, when read by a computer, cause the computer to perform the radio monitoring method.

One or more embodiments of the present description provide a radio monitoring device, the device comprising a processor and a memory; the memory is configured to store instructions that, when executed by the processor, cause the apparatus to implement operations corresponding to the radio monitoring method.

Drawings

The present description will be further explained by way of exemplary embodiments, which will be described in detail by way of the accompanying drawings. These embodiments are not intended to be limiting, and in these embodiments like numerals are used to indicate like structures, wherein:

FIG. 1 is a schematic diagram of an application scenario of a radio monitoring system according to some embodiments of the present description;

FIG. 2 is a block diagram of an exemplary architecture of a radio monitoring system in accordance with certain embodiments of the present description;

FIG. 3 is a schematic diagram of a first predictive model in accordance with some embodiments of the present description;

FIG. 4 is a schematic illustration of a first predictive model, according to some embodiments of the present disclosure;

FIG. 5 is an exemplary flow diagram of a radio monitoring method according to some embodiments described herein;

FIG. 6 is a block diagram of an exemplary architecture of an FPGA processing device for a radio monitoring system in accordance with certain embodiments of the present description;

FIG. 7 is an exemplary flow diagram of a method for spectrum analysis for a radio monitoring system according to some embodiments described herein;

FIG. 8 is a schematic diagram of a data packet read in a constant rate spectral analysis mode, according to some embodiments of the present description;

FIG. 9 is a schematic diagram of a data packet read in a fast spectrum analysis mode according to some embodiments of the present description;

FIG. 10 is a schematic diagram of a data packet read in a slow spectrum analysis mode according to some embodiments of the present description.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only examples or embodiments of the present description, and that for a person skilled in the art, the present description can also be applied to other similar scenarios on the basis of these drawings without inventive effort. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.

It should be understood that "system", "apparatus", "unit" and/or "module" as used herein is a method for distinguishing different components, elements, parts, portions or assemblies at different levels. However, other words may be substituted by other expressions if they accomplish the same purpose.

As used in this specification and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

Flowcharts are used in this specification to illustrate the operations performed by the system according to embodiments of the present specification. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, the various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to the processes, or a certain step or several steps of operations may be removed from the processes.

Fig. 1 is a schematic diagram of an application scenario 100 of a radio monitoring system according to some embodiments of the present description.

In some embodiments, the application scenario 100 may be configured as radio monitoring or the like. The method can be applied to corresponding communication control scenes such as radio monitoring, radio identification, radio management and the like. The application scenario 100 may include a server 110, a network 120, a user terminal 130, a storage device 140, and a signal source 150. The server 110 may include a processing engine 112. In some embodiments, server 110, user terminal 130, storage device 140, and signal source 150 may be connected to and/or communicate with each other via a wireless connection (e.g., network 120), a wired connection, or a combination thereof.

The server 110 may be used to implement radio monitoring. In some embodiments, the method can be specifically used for realizing monitoring of radio such as satellites, and the monitoring technology can be applied to many fields such as government departments, national defense military, news media, customs, foreign exchange, combat readiness communication and the like.

The server 110 refers to a system having computing capabilities, and in some embodiments, the server 110 may be a single server or a group of servers. The set of servers can be centralized or distributed (e.g., the servers 110 can be a distributed system). In some embodiments, the server 110 may be local or remote. For example, server 110 may access information and/or data stored in user terminal 130 and/or storage device 140 via network 120. As another example, server 110 may be directly connected to user terminal 130 and/or storage device 140 to access stored information and/or data. In some embodiments, the server 110 may be implemented on a cloud platform. By way of example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an internal cloud, a multi-tiered cloud, and the like, or any combination thereof. In some embodiments, server 110 may be implemented on a computing device 200 having one or more of the components illustrated in FIG. 2 in the present application.

In some embodiments, the server 110 may include a processing engine 112. The processing engine 112 may process information and/or data related to the wireless signal. For example, the processing engine 112 may implement radio monitoring in the information data acquired by the signal source 150. In some embodiments, processing engine 112 may include one or more processing engines (e.g., a single core processing engine or a multi-core processor). By way of example only, the processing engine 112 may include one or more hardware processors such as a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), an application specific instruction set processor (ASIP), a Graphics Processing Unit (GPU), a Physical Processing Unit (PPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a controller, a microcontroller unit, a Reduced Instruction Set Computer (RISC), a microprocessor, or the like, or any combination thereof.

Network 120 may facilitate the exchange of information and/or data. In some embodiments, one or more components in the application scenario 100 (e.g., the server 110, the user terminal 130, the storage device 140, and the signal source 150) may send information and/or data to other components in the application scenario 100 through the network 120. For example, the processing engine 112 may send the analysis results of the monitored radio to the user terminal 130 via the network 120. In some embodiments, the network 120 may be a wired network or a wireless network, or the like, or any combination thereof. By way of example only, network 120 may include a cable network, a wired network, a fiber optic network, a telecommunications network, an intranet, the Internet, a Local Area Network (LAN), a Wide Area Network (WAN), a Wireless Local Area Network (WLAN), a Metropolitan Area Network (MAN), a Wide Area Network (WAN), the Public Switched Telephone Network (PSTN), a Bluetooth network, a ZigBee network, a Near Field Communication (NFC) network, or the like, or any combination thereof. In some embodiments, network 120 may include one or more network access points. For example, the network 120 may include wired or wireless network access points, such as base stations and/or internet exchange points 120-1, 120-2, …, through which one or more components of the application scenario 100 may connect to the network 120 to exchange data and/or information.

In some embodiments, the user terminal 130 may include a mobile device 130-1, a tablet computer 130-2, a laptop computer 130-3, a desktop computer 130-4, and the like, or any combination thereof. In some embodiments, mobile device 140-1 may include a smart home device, a wearable device, a mobile device, a virtual reality device, an augmented reality device, and the like, or any combination thereof. In some embodiments, the smart home devices may include smart lighting devices, smart appliance control devices, smart monitoring devices, smart televisions, smart cameras, interphones, and the like, or any combination thereof. In some embodiments, the wearable device may include a bracelet, footwear, glasses, helmet, watch, clothing, backpack, smart accessory, and the like, or any combination thereof. In some embodiments, the mobile device may include a mobile phone, a Personal Digital Assistant (PDA), a gaming device, a navigation device, a point of sale (POS) device, a laptop computer, a desktop computer, etc., or any combination thereof. In some embodiments, the virtual reality device and/or the enhanced virtual reality device may include a virtual reality helmet, virtual reality glasses, a virtual reality eyeshade, an augmented reality helmet, augmented reality glasses, an augmented reality eyeshade, and the like, or any combination thereof. For example, the virtual reality device and/or the augmented reality device may include a google glass ^TM 、RiftCon ^TM 、Fragments ^TM 、GearVR ^TM And the like.

In some embodiments, the user terminal 130 may be a mobile terminal configured to collect radio signals. The user terminal 130 may send and/or receive information related to radio signal monitoring and identification to the processing engine 112 or a processor installed in the user terminal 130 via a user interface. For example, the user terminal 130 may transmit radio signal data captured by the user terminal 130 installed in the user terminal 120 to the processing engine 112 or the processor installed in the user terminal via the user interface. The user interface may be in the form of an application implemented on the user terminal 130 for identifying satellites. A user interface implemented on the user terminal 130 may facilitate communication between the user and the processing engine 112. For example, a user may enter and/or import radio signal data that needs to be identified via a user interface. The processing engine 112 may receive input signal data via a user interface. As another example, the user may input a request to identify the radio signal via a user interface implemented on the user terminal 130. In some embodiments, in response to the identification request, the user terminal 130 may directly process the radio signal data via a processor of the user terminal 130 based on a signal acquisition device installed in the user terminal 130 as described elsewhere in this application. In some embodiments, in response to the identification request, the user terminal 130 may send the identification request to the processing engine 112 for determining a radio signal based on a signal acquisition device installed by the signal source 150 or elsewhere in the application. In some embodiments, the user interface may facilitate presenting or displaying information and/or data (e.g., signals) related to radio monitoring received from the processing engine 112. For example, the information and/or data may include results indicating radio monitoring content, or indicate that radio monitoring is performed, etc. In some embodiments, the information and/or data may be further configured to cause the user terminal 130 to display the results to the user.

Storage device 140 may store data and/or instructions. In some embodiments, storage device 140 may store data obtained from signal source 150. Storage device 140 may store data and/or instructions that processing engine 112 may execute or use to perform the exemplary methods described herein. In some embodiments, storage device 140 may include mass storage, removable storage, volatile read-write memory, read-only memory (ROM), etc., or any combination thereof. Exemplary mass storage devices may include magnetic disks, optical disks, solid state drives, and the like. Exemplary removable memories may include flash drives, floppy disks, optical disks, memory cards, compact disks, magnetic tape, and the like. Exemplary volatile read and write memory can include Random Access Memory (RAM). Exemplary RAM may include Dynamic Random Access Memory (DRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Static Random Access Memory (SRAM), thyristor random access memory (T-RAM), zero capacitance random access memory (Z-RAM), and the like. Exemplary ROMs may include mask read-only memories (MROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), compact disc read-only memories (CD-ROMs), digital versatile disc read-only memories (dvroms), and the like. In some embodiments, the storage device 140 may execute on a cloud platform. By way of example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an internal cloud, a multi-tiered cloud, and the like, or any combination thereof.

In some embodiments, a storage device 140 may be connected to the network 120 to communicate with one or more components (e.g., server 110, user terminal 130) in the application scenario 100. One or more components in the application scenario 100 may access data or instructions stored in the storage device 140 via the network 120. In some embodiments, the storage device 140 may be directly connected to or in communication with one or more components in the application scenario 100 (e.g., server 110, user terminal 130). In some embodiments, the storage device 140 may be part of the server 110.

The signal source 150 is a signal terminal that emits a radio signal, and for example, the signal source may be a satellite, a signal generator, a base station, or the like. The radio signals generated by the signal source 150 can be collected based on the corresponding signal collecting device.

It should be noted that the above description is intended to be illustrative, and not to limit the scope of the application. Many alternatives, modifications, and variations will be apparent to those skilled in the art. The features, structures, methods, and other characteristics of the exemplary embodiments described herein may be combined in various ways to obtain additional and/or alternative exemplary embodiments. For example, the signal source 150 may be configured with a storage module, a processing module, a communication module, and the like. However, such changes and modifications do not depart from the scope of the present application.

Fig. 2 is a block diagram of an exemplary architecture of a radio monitoring system in accordance with some embodiments of the present disclosure.

As shown in fig. 2, the radio monitoring system 200 may include a radio frequency front end 210, an AD data acquisition module 220, an FPGA processor 230, a DDR3 memory chip 240, and an upper computer 250.

In some embodiments, the rf front end 210 may be configured to receive a radio signal from a signal source (e.g., the signal source 15), and in some embodiments, the rf front end may be composed of a series of components between the rf transceiver and the antenna, such as a Power Amplifier (PA), a Switch (Switch), a Filter (Filter), a Duplexer (Duplexer and Diplexer), a Low Noise Amplifier (LNA), and so on. In some embodiments, the radio frequency front end is in communication connection with the AD data acquisition module, and the radio frequency front end is configured to receive a signal to be analyzed through an antenna, and perform at least one of amplification, filtering, and frequency mixing on the signal to be analyzed to obtain an intermediate frequency signal.

In some embodiments, the AD data acquisition module 220 may employ an ADI high-speed AD chip design. In some embodiments, the AD data acquisition module 220 is communicatively connected to the FPGA processor, and the AD data acquisition module is configured to convert the intermediate frequency signal into IQ data and upload the IQ data to the FPGA processor.

In some embodiments, the FPGA processor 230 may be in communication connection with the DDR3 memory chip and the upper computer, and the FPGA processor is configured to store the IQ data, play back the IQ data based on a corresponding playback mode, perform spectrum analysis on the IQ data during playback, obtain an analysis result, and upload the analysis result to the upper computer; the playback mode includes at least one of a normal spectral analysis mode, a fast spectral analysis mode, and a slow spectral analysis mode.

For more details regarding FPGA processor 230, reference may be made to fig. 5-7 and the description thereof.

In some embodiments, the DDR3 memory chip 240 is configured to store the IQ data received by the FPGA processor, and the data source of the FPGA processor during playback includes the IQ data stored in the DDR3 memory chip.

The DDR3 memory chip is used as an IQ data memory unit, the cost is low, the board manufacturing volume is small, the memory capacity can be expanded to several GB, the memory speed supports dozens of GB/s, the original IQ data memory under the high sampling rate can be met, the memory duration from several seconds to several minutes can be supported according to the difference of the sampling rate, and the conventional monitoring requirement on the radio signal is fully met.

In some embodiments, the upper computer 250 may be configured to run human-machine interaction software, obtain a user instruction based on the running human-machine interaction software, issue the user instruction to the FPGA processor, and display a spectrum waveform based on the analysis result.

In some embodiments, the radio monitoring system in the embodiments of the present specification may support a normal spectrum analysis mode and a fast and slow spectrum analysis mode during data playback, and different playback modes have different operation steps, which mainly differ in the skip control of the IQ data access interval during playback.

It should be noted that the above description of the system and its components is merely for convenience of description and should not be construed as limiting the present disclosure to the illustrated embodiments. It will be appreciated by those skilled in the art that, given the teachings of the present system, any combination of components or sub-systems may be combined with other components without departing from such teachings. For example, the radio frequency front end and the AD data acquisition module may be integrated in one component. For another example, the components may share one storage device, and each component may have a storage device. Such variations are within the scope of the present disclosure.

As shown in fig. 5, which is an exemplary flow diagram of a radio monitoring method according to some embodiments of the present description, in some embodiments, flow 500 may be performed by FPGA processor 230. In some embodiments, flow 500 may include the following steps:

step 510, accepting the IQ data uploaded by the AD data acquisition module.

In some embodiments, the radio monitoring system may collect the received signal through the antenna based on the radio frequency front end, and then output the intermediate frequency signal after processing, such as amplification, filtering, frequency mixing, and the like, the collected signal based on the radio frequency front end.

In some embodiments, the radio frequency front end may transmit the obtained intermediate frequency signal to an AD data acquisition module designed by an ADI high-speed AD chip, and the AD data acquisition module performs signal conversion processing on the received intermediate frequency signal to obtain a corresponding digital signal, that is, IQ data.

In some embodiments, the AD data acquisition module may send the IQ data processed by the AD data acquisition module to the FPGA processor as the signal processing unit.

And step 520, storing the IQ data and sending the IQ data to the DDR3 memory chip.

In some embodiments, the FPGA processor may cache real-time IQ data uploaded by the AD data acquisition module, and at the same time, forward the data to the DDR3 memory chip.

In some embodiments, the DDR3 memory chip may store all IQ data uploaded by the AD data acquisition module. In some embodiments, the DDR3 memory chip may store the IQ data according to the acquisition timing of the radio signal corresponding to the IQ data.

Step 530, obtaining a playback mode and a reading rule based on the upper computer.

In some embodiments, the user can input the required playback mode by the upper computer, and the playback mode input by the user is transmitted to the FPGA processor by the upper computer. In some embodiments, the radio monitoring system may pre-store the reading rules corresponding to various playback modes, and the FPGA processor may determine the corresponding reading rules based on the playback modes after determining the playback modes. In some embodiments, the playback mode may include at least one of a constant-rate spectral analysis mode, a fast-rate spectral analysis mode, and a slow-rate spectral analysis mode. See step 540 for a detailed description of the playback mode.

The read rule refers to a rule that the FPGA processor reads IQ data from a data source, and in some embodiments, the read rule may include a fetch interval value. In some embodiments, the fetch interval value may be based on a length value or a point value representation of the IQ data. The fetch interval value represents a length value or a point value of the IQ data spaced between the first IQ data in two adjacent data packets.

And 540, reading a plurality of data packets from the DDR3 memory chip according to the playback mode and the corresponding reading rule.

In some embodiments, the FPGA processor may read the plurality of data packets with reference to the corresponding reading rule based on the playback mode in an order in which the IQ data are stored within the DDR3 memory chip; the number of points and/or the length of the IQ data contained in each data packet in the plurality of data packets are the same, and the sum of the lengths of all the IQ data in the plurality of data packets does not exceed a preset storage length; the number of points of the IQ data contained in each data packet is 2 ⁿ Such as 2048 points, 4096 points, etc. In some embodiments, the number of data points included in a data packet is the number of FFT processing points (i.e., the length of a packet of FFT) for a subsequent FFT processing.

In some embodiments, reading the plurality of data packets with reference to the corresponding reading rule based on the playback mode is mainly based on the fetching interval value determined by the reading rule corresponding to the playback mode.

In some embodiments, when the playback mode is a constant-speed spectrum analysis mode, the fetch interval value is equal to a length value or a point value of the IQ data included in one of the data packets. For example, if the number of points of the IQ data included in one of the data packets is 2048 points, the value of the fetch interval may be equal to 2048 points. That is, in the constant-speed spectrum analysis mode, each data packet read by the FPGA processor is continuous data in the DDR3 storage chip.

For example only, when the playback mode is the constant-speed spectrum analysis mode, after the FPGA processor finishes reading the IQ data with one packet of FFT length, the FPGA processor continues to read the IQ data with the next packet of FFT length from an adjacent address until the sum of the lengths of all the IQ data in a plurality of data packets does not exceed a preset storage length, where the preset storage length may refer to a data length reaching a storage boundary, that is, the preset storage length does not exceed a total length of the IQ data that can be stored by the DDR3 storage chip, or meets a required data length. For more description of the preset storage length, refer to fig. 4 and its description, which are not described herein.

It should be noted that, when the preset storage length refers to a data length reaching a storage boundary, if the data lengths of all the read data reach the storage boundary, and if the remaining IQ data cannot form a packet of complete FFT length, the last packet of data is discarded, and subsequent spectrum analysis is not performed, so as to avoid the occurrence of spectrum leakage.

In some embodiments, when the playback mode is a fast spectrum analysis mode, the fetch interval value is greater than a length value or a point value of the IQ data included in one of the data packets; for example, if the number of points of the IQ data included in one of the data packets is 2048 points, the value of the access interval may be equal to 3000 points. In some embodiments, the value of the access interval of the fast spectrum analysis mode may be based on a predetermined setting, such as a setting of the user, and in some embodiments, the value of the access interval of the fast spectrum analysis mode may also be determined by a machine learning model, for example, see fig. 3 and the description thereof.

In some embodiments, the fetch interval value may also be expressed based on an address jump amount, for example, in a fast spectral analysis mode, the address jump amount may be equal to the difference between the fetch interval value and a packet FFT length value. When the playback mode is a fast spectrum analysis mode, which is only an example, the address jump amount may be greater than one packet of FFT length, after the IQ data of one packet of FFT length is read, the FPGA processor may skip a segment of data of an adjacent address, where the length of the segment of data is the difference between the fetch interval value and the value of one packet of FFT length, that is, the address jump amount, and then start reading the IQ data of the next packet of FFT length until the sum of the lengths of all the IQ data in multiple data packets does not exceed a preset storage length. In this case, the readable times of the storage space of the whole DDR3 memory chip are reduced, and the sampling of the data is equivalent to the improvement of the spectrum analysis speed.

In some embodiments, when the playback mode is the slow spectrum analysis mode, the fetch interval value is smaller than a length value or a point value of the IQ data included in one of the data packets, for example, when the point value of the IQ data included in one of the data packets is 2048 points, the fetch interval value may be equal to 1500 points. In some embodiments, the value of the fetch interval of the slow spectrum analysis mode may be based on a predetermined setting, such as a setting of the user, and in some embodiments, the value of the fetch interval of the slow spectrum analysis mode may also be determined by a machine learning model, for example, see fig. 3 and the description thereof.

In some embodiments, when the playback mode is the slow spectrum analysis mode, the fetch interval value may also be expressed based on an address jump amount, for example, in the slow spectrum analysis mode, the address jump amount may be equal to a difference between a packet FFT length value and the fetch interval value. For example only, when the playback mode is the slow spectrum analysis mode, the address jump amount is smaller than one packet of FFT length, and after the IQ data of one packet of FFT length is read, the IQ data of the next packet of FFT length is read starting from the end address by jumping back by one segment of address (i.e. the address jump amount) until the sum of the lengths of all the IQ data in the multiple data packets does not exceed the preset storage length. In this case, the read-back addresses have overlapping portions, and a certain section of IQ data is repeatedly read for multiple times, so that the readable times of the whole DDR3 memory chip are increased, which is equivalent to slowing down the spectrum analysis speed.

Similarly, it should be noted that, when the playback mode is the fast spectrum analysis mode or the slow spectrum analysis mode, and the preset storage length refers to a data length reaching the storage boundary, if the data lengths of all the read data reach the storage boundary, and if the remaining IQ data cannot form a complete FFT length, the last packet of data is discarded, and subsequent spectrum analysis is not performed, so as to avoid the occurrence of spectrum leakage.

Step 550, playing back the IQ data in the obtained multiple data packets, and performing spectrum analysis on the IQ data during playback to obtain an analysis result.

In some embodiments, the FPGA serves as a signal processing unit, which can control storage and playback of the IQ data, and perform speed control on the spectrum analysis in the playback mode according to a setting, such as selecting a fast, a normal, and a slow spectrum analysis speed, to finally obtain a corresponding spectrum analysis result.

Step 560, uploading the analysis result to the upper computer

In some embodiments, the FPGA processor may upload the spectrum analysis result to the upper computer through the PCIe interface, and the upper computer performs further graphic display on the application software, so that a user can visually know the relevant indexes of the signal.

In some embodiments of the invention, a radio monitoring system for fast and slow spectrum analysis and IQ record playback is designed by using an FPGA and a DDR3 memory chip. The system can switch the spectrum analysis speed in an IQ playback state so as to aim at different radio monitoring tasks: under the application scenes of quickly searching and identifying signals, quick spectrum analysis can be selected so as to save retrieval time; when the abnormal jump signal is analyzed in detail, slow frequency spectrum analysis can be selected to obtain technical indexes and observation effects of finer granularity. DD (DD) with high heat dissipating capacity

It should be noted that the above description related to the flow 500 is only for illustration and description, and does not limit the applicable scope of the present specification. Various modifications and changes to flow 500 may occur to those skilled in the art, given the benefit of this description. However, such modifications and variations are intended to be within the scope of the present description.

FIG. 3 is a schematic diagram illustrating a first predictive model 300 according to some embodiments herein.

In some embodiments, the first predictive model may be a model for predicting fetch interval values. For example, Convolutional Neural Networks (CNNs), Deep Neural Networks (DNNs), and the like, or combinations thereof.

In some embodiments, the input to the first prediction model may include one or more of a data acquisition rate, a transmission delay, a check error rate, a noise rate, a size and number of MTUs, a playback mode, a number of data points for one packet. In some embodiments, the output of the first predictive model may include an estimated fetch interval value.

In some embodiments, the data acquisition rate may refer to the rate at which data is transmitted to the FPGA processor based on the AD data acquisition module, for example, may refer to the number of data points transmitted per unit time, and the transmission rate may be expressed in terms of bit rate and baud rate. For example, the transmission rate may be 100 bits/s or 5B. In some embodiments, the transmission delay refers to the total time required by a data sender (e.g., an AD data acquisition module) from the beginning of sending a data frame to the end of sending the data frame, and the transmission delay is related to the size of the sent data frame. For example, if the data frame size is 2000 bits, the transmission rate is 200 bits/s, and the transmission delay is 1 s. In some embodiments, the check error rate is a ratio of data that is transmitted to check whether the transmitted data is correct to obtain data that has errors. In some embodiments, the method of checking the transmitted data may include parity checking, code sum checking, cyclic redundancy check, and the like. In some embodiments, the check error rate may include a bit error (bit) rate, a character error rate, or the like.

In some embodiments, the noise rate is a ratio of data points where data is interfered by external noise during transmission and errors occur. For example, the size of a transmitted data frame is 100 bits, the data point which is interfered by external noise and has errors is 20 bits, and the noise rate is 20%.

In some embodiments, the data size of the data frame may be related to a Maximum Transmission Unit (MTU). The data size of the data frame is not greater than the size of the MTU. For example, the data size of the data frame is equal to or close to the size of the MTU. MTU refers to the maximum packet size that a communication protocol can pass over a layer. The MTU may specify the payload size that the sender is able to accept. The size of the MTU may be in bytes.

In some embodiments, the playback mode may include a normal spectral analysis mode, a fast spectral analysis mode, and a slow spectral analysis mode, and further description regarding the playback mode is provided with reference to fig. 5 and its description.

In some embodiments, the number of data points of a data packet refers to the number of points and/or length of the IQ data included in each data packet, and is generally 2 ⁿ For more description of the number of data points of a packet, refer to fig. 5 and its description.

In some embodiments, the first predictive model may be trained using a plurality of labeled training samples. For example, a plurality of labeled training samples may be input into an initial first prediction model, a loss function may be constructed from the labels and the results of the initial first prediction model, and parameters of the initial first prediction model may be iteratively updated based on the loss function. And finishing model training when the loss function of the initial first prediction model meets a preset condition to obtain a trained first prediction model. The preset condition may be that the loss function converges, the number of iterations reaches a threshold, and the like.

In some embodiments, the training samples may include at least multiple sets of historical sample data, and each set of historical sample data may include a historical data acquisition rate, a historical transmission delay, a historical check error rate, a historical noise rate, a size and number of historical MTUs, and a number of data points of one data packet corresponding to a certain historical playback mode. The tag may be a fetch interval value corresponding to the historical playback mode. The labels may be retrieved based on manual labeling.

The data acquisition interval value of the data point can be accurately predicted through the first prediction model, so that a more appropriate reading rule is determined to read the data, the possibility of continuous loss or invalidity of the data is reduced, and the influence of unread data on the effectiveness of the whole data analysis is reduced.

FIG. 4 is a schematic diagram of a process 400 of training and executing a second predictive model according to some embodiments described herein.

In some embodiments, a value of a preset memory length may be predicted based on the second prediction model, and in some embodiments, the preset memory length does not exceed a total length of the IQ data that the DDR3 memory chip may store. In some embodiments, the preset storage length is adjustable in size. For example, the preset memory length is from 2 ¹⁰ Adjusted to 2 ²⁰ . In some embodiments, the storage capacity of the DDR3 memory chip sets the preset storage length, for example, the larger the storage capacity of the DDR3 memory chip is, the larger the preset storage length may be increased accordingly.

In some embodiments, the predetermined storage length may be predicted based on a second prediction model. In some embodiments, the second prediction mode may be implemented by Deep Neural Networks (DNNs), Convolutional Neural Networks (CNNs), or the like.

In some embodiments, the input 430 of the second prediction module 440 may be data characteristics of IQ data, a value of a fetch interval, a number of points of IQ data contained in one data packet, characteristics of an AD data acquisition module, a storage capacity of a DDR3 storage chip, and the like, and the output 450 may be a preset storage length. The data characteristics of the IQ data refer to characteristics characterizing the IQ data, which may include, for example, acquisition time, length, type, and the like. Data characteristics of the IQ data may be acquired based on the AD data acquisition module. The characteristics of the AD data acquisition module may include characteristics characterizing the performance of the AD data acquisition module, such as chip model, processing speed, capacity, and the like. The characteristics of the AD data acquisition module may be obtained based on the specifications of the AD data acquisition module. For the description of the fetching interval value, the number of points of IQ data included in one data packet, the storage capacity of the DDR3 memory chip, and the like, refer to fig. 3 and fig. 5, which are not described herein again.

In some embodiments, the second prediction model 440 may be trained based on a number of labeled training samples 410. For example, the labeled training samples 410 are input into the initial second prediction model 420, a loss function is constructed from the labels and the prediction results of the initial second prediction model 420, and the parameters of the model are iteratively updated based on the loss function. And when the trained model meets the preset condition, finishing the training. The preset conditions include loss function convergence, threshold reaching of iteration times and the like.

In some embodiments, the training samples may include at least data characteristics of the sample IQ data, sample access interval values, number of points of IQ data contained in the sample data packet, characteristics of the sample AD data acquisition module, and storage capacity of the sample DDR3 memory chip. The tag may be the actual set memory length. The tags may be generated based on historical data retrieved from a storage system, or the tags may be manually labeled.

Some embodiments of the present description may implement, by processing the preset storage length, determining the preset storage length based on information such as data characteristics of IQ data, a fetch interval value, a number of points of IQ data included in one data packet, characteristics of an AD data acquisition module, and a storage capacity of a DDR3 storage chip, which may effectively improve accuracy of the preset storage length, reduce difficulty of manual calculation, and improve efficiency of data processing.

Fig. 6 is a block diagram illustrating an exemplary configuration of an FPGA processing device for a radio monitoring system according to some embodiments of the present disclosure.

As shown in fig. 6, the FPGA processing device (i.e., the aforementioned FPGA processor) may include a bandwidth matching and buffering module 610, a spectrum analysis playback control module 620, a data source selection module 630, a digital signal processing module 640, and an external connection module 650.

In some embodiments, the bandwidth matching and buffering module is communicatively connected to the data source selecting module and the spectrum analysis playback control module, respectively, and may be configured to receive a digital signal and buffer the received digital signal.

In some embodiments, the data source selection module is in communication connection with the spectrum analysis playback control module and the digital signal processing module respectively. The data source selection module can be used for determining the data source read by the spectrum analysis playback control module when performing data playback and spectrum analysis. In some embodiments, the data source selection module may accept user-set data source information based on a peripheral device such as a host computer.

In some embodiments, the spectrum analysis playback control module is communicatively coupled to a memory device of the radio monitoring system. In some embodiments, the spectrum analysis playback control module may be configured to read a plurality of data packets from the data source based on a playback mode, refer to a reading rule corresponding to the playback mode, play back the acquired digital signals in the plurality of data packets, and perform spectrum analysis on the digital signals during playback to obtain an analysis result. For a detailed description, refer to fig. 7 and its description, which are not repeated herein.

In some embodiments, the digital signal processing module includes a digital filtering unit, an FFT unit, and a detection unit, which are connected in sequence. In some embodiments, the digital signal processing module is configured to perform digital filtering, fast fourier transform, and detection on the playback data in the spectrum analysis playback control module.

In some embodiments, the external connection module is configured to enable communication between the FPGA processing device and at least some of the devices in the radio monitoring system other than the FPGA processing device. For example, the external connection module may include a PCIe interface, a jesd204b interface, and the like, the FPGA processing device may be connected to the DDR3 memory chip through the PCIe interface, and the AD data acquisition module may be communicatively connected to the FPGA processing device through the jesd204b interface.

It should be noted that the above description of the system and its components is merely for convenience of description and should not be construed as limiting the present disclosure to the illustrated embodiments. It will be appreciated by those skilled in the art that, given the teachings of the present system, any combination of components or sub-systems may be combined with other components without departing from such teachings. For example, the data source selection module and the spectral analysis playback control module may be integrated in one component. For another example, the components may share one storage device, and each component may have a storage device. Such variations are within the scope of the present disclosure.

As shown in fig. 7, which is an exemplary flow diagram of a radio monitoring method according to some embodiments of the present description, in some embodiments, flow 700 may be performed by an FPGA processing device. In some embodiments, flow 700 may include the following steps:

step 710, obtaining storage parameters of the data to be analyzed.

The data to be analyzed refers to data that needs to be subjected to spectrum analysis, such as the aforementioned IQ data or digital signal. In some embodiments, the storage parameters may include storage start point, storage length, and the like. In some embodiments, the storage parameters may be set by the host computer based on a user.

And 720, storing the data to be analyzed based on the storage parameters.

In some embodiments, after the FPGA processing device obtains the storage parameters, the storage parameters may be stored correspondingly. For example, the FPGA processing device may store the data to be analyzed based on a storage start point and a storage length set by a user and acquired from the upper computer.

Step 730, obtaining a playback instruction, wherein the playback instruction comprises a playback mode and a data source; the playback mode comprises a constant-speed spectrum analysis mode, a fast spectrum analysis mode and a slow spectrum analysis mode.

In some embodiments, the playback indication may be set by the user via the host computer, for example, the user sends the playback to the FPGA processing device via the host computer in a fast spectrum analysis mode.

An address offset is determined based on the playback mode, step 740.

The address offset refers to a data offset that needs to be spaced between data packets when the FPGA processing device reads data, and in some embodiments, the address offset may be represented by an address jump amount, and further description on the address jump amount is shown in fig. 5, which is not described herein again.

Step 750, reading data with preset length from the data source based on the address offset and using the data as a data packet.

After the playback mode is determined, the address offset can be determined based on the playback mode, and the FPGA processing device can read data with a preset length from the data source based on the address offset and use the data as a data packet. For more description of the data and the data packets with the preset length, refer to fig. 5, which is not described herein again.

And 760, judging whether the sum of the data lengths in all the read data packets meets a preset condition, if so, stopping data reading, and otherwise, determining the initial reading address of the next data packet based on the address offset and reading the next data packet.

In some embodiments, after completing reading of data of one data packet each time, the FPGA processing device needs to determine a sum of lengths of all data currently read, specifically, determine whether the sum of the lengths of the data in all the read data packets meets a preset condition, if yes, stop reading the data and enter step 770, otherwise, determine an initial reading address of a next data packet based on the address offset and read the next data packet, and execute step 760 again.

And step 770, after the data reading is finished, the read data is played back and subjected to spectrum analysis, and an analysis result is obtained.

In some embodiments, the FPGA processing device may replay the read data, perform spectrum analysis during the replay, further obtain an analysis result, send the analysis result to an upper computer, and further perform display of a corresponding graph by the upper computer, so that a user can visually know corresponding information.

The following describes specific operations performed by the FPGA processing apparatus in conjunction with different playback modes:

when the playback mode is the constant-speed spectrum analysis mode, the FPGA processing device is configured to:

acquiring storage parameters of the digital signal based on the external connection module, wherein the storage parameters comprise a storage starting point and a storage length;

based on the storage parameters, the digital signals are stored through the bandwidth matching and caching module;

judging whether the length of the stored digital signal meets the storage length;

in response, an interrupt signal based on the external connection module issues a storage complete signal to the radio monitoring system. For example, after the storage length meets the set requirement, the FPGA processing device generates a storage completion signal and informs the upper computer in an interrupt mode.

The storage process can be executed for multiple times, and corresponding files in the radio monitoring system record the storage parameters during each storage.

And when the frequency spectrum analysis is carried out in a playback state, the data source selection module acquires a data source for playback based on the external connection module and starts a playback control process. For example, the data source selection module performs playback of the data source based on user selection through the upper computer, and starts a playback control flow.

And the spectrum analysis playback control module reads data from the data source by taking the FFT length as the continuous read-back data volume.

When data reading is carried out, after the digital signal of each packet of FFT length is completely read, the frequency spectrum analysis playback control module judges whether the total reading amount and the storage boundary meet preset conditions.

In response to that preset conditions are not met, the spectrum analysis playback control module starts continuous reading of the digital signals of the next packet of FFT length, and the initial reading address of the digital signals of the next packet of FFT length is separated from the initial reading address of the digital signals of the previous packet of FFT length adjacent to the initial reading address by the data volume of one packet of FFT length; i.e., the address offset is a packet FFT length.

Wherein the total read-back data volume satisfies the following formula:

total_num＝n*fft_length

wherein, total _ num is the total read-back data amount, n is the packet number of the data with the completely read FFT length, and FFT _ length is the processing point number of the FFT unit, i.e. one packet FFT length. Fig. 8 is a schematic diagram illustrating data reading in the constant-speed spectrum analysis mode.

The digital signal processing module replaces real-time sampling data with playback data read by the spectrum analysis playback control module, and performs digital filtering, fast Fourier transform and detection processing on the playback data in sequence based on the digital filtering unit, the FFT unit and the detection unit.

And returning the playback data to the radio monitoring system based on the external connection module to perform spectrum analysis to obtain an analysis result.

When the playback mode is the fast spectrum analysis mode, the FPGA processing device is configured to:

and acquiring storage parameters of the digital signal based on the external connection module, wherein the storage parameters comprise a storage starting point and a storage length.

and judging whether the length of the stored digital signal meets the storage length.

In response, an interrupt signal based on the external connection module issues a storage complete signal to the radio monitoring system.

And when the frequency spectrum analysis is carried out in a playback state, the data source selection module acquires a data source and a fast coefficient for playback based on the external connection module, and starts a playback control flow. In some embodiments, the fast coefficients may be represented by a fetch interval value.

And in response to the preset condition being not met, the spectrum analysis playback control module starts continuous reading of the digital signal with the next packet of FFT length, and the data volume corresponding to the fast coefficient of the initial reading address of the digital signal with the next packet of FFT length and the initial reading address of the digital signal with the previous packet of FFT length adjacent to the initial reading address of the digital signal with the next packet of FFT length.

Wherein the total read-back data volume satisfies the following formula:

total_num＝n*fft_length (1)

total_addr_offset＝(n-1)*read_gap+fft_length (2)

wherein, in formula 1, total _ num is the total read-back data amount, n is the packet number of the data with the completely read FFT length, and FFT _ length is the processing point number of the FFT unit;

in equation 2, total _ addr _ offset is the total address offset, read _ gap is the fast coefficient, and read _ gap is greater than fft _ length; fig. 9 is a schematic diagram illustrating reading data in the fast spectrum analysis mode.

When the playback mode is the slow spectrum analysis mode, the FPGA processing device is configured to:

And when the frequency spectrum analysis is carried out in a playback state, the data source selection module acquires a data source and a fast coefficient for playback based on the external connection module, and starts a playback control flow.

Wherein the total read-back data volume satisfies the following formula:

total_num＝n*fft_length (3)

total_addr_offset＝(n-1)*read_gap+fft_length (4)

in formula 3, total _ num is the total read-back data amount, n is the packet number of the data with the completely read FFT length, and FFT _ length is the number of processing points of the FFT unit.

In equation 4, total _ addr _ offset is the total address offset, read _ gap is the fast coefficient, and read _ gap is smaller than fft _ length. Fig. 10 is a schematic diagram of reading data in the slow spectrum analysis mode.

In some embodiments of the present invention, the speed spectrum analysis function can be switched by design. The normal-speed spectrum analysis is used in common application scenes, and the fast-speed spectrum analysis and the slow-speed spectrum analysis are used in application scenes with special requirements, so that the analysis performance of the system can be improved. And the support range of the fast and slow coefficients is very wide, the fast speed can support dozens of times of spectrum analysis speed, the slowest speed can support point-by-point spectrum scanning analysis, and the fast and slow speeds can be set at will. The user can freely switch in the technical scheme of quick retrieval and detailed analysis according to actual requirements.

Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing detailed disclosure is to be regarded as illustrative only and not as limiting the present specification. Various modifications, improvements and adaptations to the present description may occur to those skilled in the art, though not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present specification and thus fall within the spirit and scope of the exemplary embodiments of the present specification.

Also, the description uses specific words to describe embodiments of the description. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the specification is included. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the specification may be combined as appropriate.

Additionally, the order in which the elements and sequences of the process are recited in the specification, the use of alphanumeric characters, or other designations, is not intended to limit the order in which the processes and methods of the specification occur, unless otherwise specified in the claims. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.

Similarly, it should be noted that in the preceding description of embodiments of the present specification, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to imply that more features than are expressly recited in a claim. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.

Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.

For each patent, patent application publication, and other material, such as articles, books, specifications, publications, documents, etc., cited in this specification, the entire contents of each are hereby incorporated by reference into this specification. Except where the application history document does not conform to or conflict with the contents of the present specification, it is to be understood that the application history document, as used herein in the present specification or appended claims, is intended to define the broadest scope of the present specification (whether presently or later in the specification) rather than the broadest scope of the present specification. It is to be understood that the descriptions, definitions and/or uses of terms in the accompanying materials of this specification shall control if they are inconsistent or contrary to the descriptions and/or uses of terms in this specification.

Finally, it should be understood that the embodiments described herein are merely illustrative of the principles of the embodiments of the present disclosure. Other variations are also possible within the scope of the present description. Thus, by way of example, and not limitation, alternative configurations of the embodiments of the specification can be considered consistent with the teachings of the specification. Accordingly, the embodiments of the present description are not limited to only those embodiments explicitly described and depicted herein.

Claims

1. A radio monitoring system is characterized by comprising a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip and an upper computer;

2. The radio monitoring system according to claim 1, wherein the IQ data are sequentially stored with reference to an acquisition timing sequence within the DDR3 memory chip;

the FPGA processor, in implementing the spectral analysis of the IQ data in the playback, is further configured to:

acquiring the playback mode;

reading a plurality of data packets according to the storage sequence of the IQ data in the DDR3 storage chip and referring to corresponding reading rules based on the playback mode; the number of points and/or the length of the IQ data contained in each data packet in the plurality of data packets are the same, and the sum of the lengths of all the IQ data in the plurality of data packets does not exceed a preset storage length; the number of points of the IQ data included in each of the data packets is 2 ⁿ ；

And playing back the IQ data in the obtained data packets, and performing spectrum analysis on the IQ data in the playback.

3. A radio monitoring system according to claim 2, wherein the reading rules include a fetch interval value;

the obtaining the playback mode further comprises obtaining the fetch interval value;

the fetch interval value may be based on a length value or a point value representation of the IQ data;

the value of the access interval represents the length value or the point value of the IQ data at the interval between the first IQ data in two adjacent data packets.

4. A radio monitoring system according to claim 3,

when the playback mode is a constant-speed spectrum analysis mode, the fetch interval value is equal to a length value or a point value of the IQ data contained in one data packet;

when the playback mode is a fast spectrum analysis mode, the fetch interval value is greater than a length value or a point value of the IQ data contained in one data packet;

when the playback mode is a slow spectrum analysis mode, the fetch interval value is smaller than a length value or a point value of the IQ data included in one data packet.

5. A radio monitoring system according to claim 3, wherein the fetch interval value is determined based on a first predictive model, the first predictive model being a machine learning model, the first predictive model being configured to determine the fetch interval value based on at least one of data acquisition rate, transmission delay, check error rate, noise rate, size and number of MTUs.

6. The radio monitoring system according to claim 2, wherein the predetermined storage length does not exceed a total length of the IQ data that can be stored in the DDR3 memory chip.

7. A radio monitoring system according to claim 6, wherein the predetermined storage length is determined based on a second prediction model, the first prediction model is a machine learning model, and the first prediction model is configured to determine the predetermined storage length based on at least one of data characteristics of the IQ data, the fetch interval value, the number of points of the IQ data included in one of the data packets, and characteristics of the AD data acquisition module.

8. A radio monitoring method implemented by an FPGA processor in a radio monitoring system according to any one of claims 1-7, the radio monitoring method comprising:

receiving IQ data uploaded by the AD data acquisition module;

storing the IQ data and sending the IQ data to the DDR3 storage chip;

acquiring a playback mode and a reading rule based on the upper computer;

reading a plurality of data packets from the DDR3 memory chip according to the playback mode and corresponding reading rules;

replaying the IQ data in the obtained data packets, and performing spectrum analysis on the IQ data in the replaying process to obtain an analysis result;

and uploading the analysis result to the upper computer.

9. A computer-readable storage medium storing computer instructions which, when read by a computer, cause the computer to perform the radio monitoring method of claim 8.

10. A radio monitoring device, the device comprising a processor and a memory; the memory is configured to store instructions that, when executed by the processor, cause the apparatus to perform operations corresponding to the radio monitoring method of claim 8.