CN114914237B - Layout structure of ROMKEY unit, chip layout method and chip - Google Patents
Layout structure of ROMKEY unit, chip layout method and chip Download PDFInfo
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Abstract
The application relates to the field of integrated circuit chip design, and provides a layout structure of an ROMKEY unit, a chip layout method and a chip. The layout structure of the ROMKEY unit comprises a first logic layout area and a second logic layout area, wherein the first logic layout area and the second logic layout area are provided with respective logic output ends, and metal belts are covered above the logic output ends of the first logic layout area and the second logic layout area; the logic output end of the first logic layout area is connected with the metal belt through a connecting hole so as to realize a first logic function; or the logic output end of the second logic layout area is connected with the metal belt through a connecting hole so as to realize the second logic function. The application has simple and flexible structure and strong adaptability, and can be suitable for various process fields; when the chip is re-designed, if the ROMKEY key or the ROMCODE needs to be updated, only one layer of mask plate is modified to realize different logic outputs.
Description
Technical Field
The application relates to the field of integrated circuit chip design, in particular to a layout structure of an ROMKEY unit, a chip layout method and a chip.
Background
The security chip is a chip which accords with the national secret security certification and supports the national secret algorithm. The security chip has a security algorithm, a communication interface, an independent processor and a storage unit, and can independently generate a secret key and encrypt and decrypt. The ROM is used as a memory for storing a power-on bootstrap program of the security chip, self-checking is carried out on sensors such as light, temperature and burrs in the chip, and random keys are generated on security components such as a bus, a RAM and a FLASH, so that the security of the ROM is very important for the security chip. For security, the boot program at the time of power-on of the chip is encrypted by a ROMKEY (memory key) to generate a ROMCODE command, and the ROMCODE command is masked in the ROM to prevent power-on loss. Since the ROMKEY generating the romcore is often an attack point for deciphering the security chip, the design of the ROMKEY is crucial to the security of the whole chip.
ROMKEY is usually implemented in a hardware-hardened form through layout design by connecting binary codes (1, 0 code) to a digital power supply or a digital ground through layout design, thereby implementing a key of logic 1 or logic 0. Because of the importance of the ROMKEY in the security chip, the layout design needs to consider several aspects such as flexibility, compilability, capability of physical verification, FIB physical attack prevention, convenience for code point and key modification, and cost saving of tape-out.
In the prior art, a 128 Bit binary code is converted into 16 different ROMKEY units from high to low, each ROMKEY unit is realized by arranging ROMKEY _1, ROMKEY _0 and ROMKEY _ EDGE (EDGE layout area) from high to low according to 8-Bit 0 and 1 code, and 16 ROMKEY units are called during digital back-end design to realize key hardware solidification. The method has the following defects: firstly, the bottom layer layout layers PPLUS (P-type ion implantation area), NWELL (N-well) and NPLUS (N-type ion implantation area) of the ROMKEY _1 and ROMKEY _0 layout areas are not consistent, if a chip needs to update a key and ROMCODE, the whole chip bottom mask plate at least needs to modify four layers of masks, the cost of the plate changing flow sheet is high, and the design is not flexible enough; secondly, binary codes corresponding to 16 ROMKEY units need to be manually solidified into ROMKEY _1 and ROMKEY _0, and design risks exist in the manual solidification process; thirdly, the scheme is limited by the process. When the process is developed to an ultra-deep sub-meter process, particularly a nanometer process, the size of a standard unit is reduced in proportion, and the scheme is difficult to pass physical verification in a module layout, so that the scheme is difficult to realize.
Disclosure of Invention
In order to solve one of the technical defects, a layout structure of a ROMKEY unit is provided in the embodiment of the present application.
According to a first aspect of the embodiments of the present application, a layout structure of a ROMKEY unit is provided, which includes a first logic layout area and a second logic layout area, where the first logic layout area and the second logic layout area are provided with respective logic output ends, and a metal band covers both the logic output ends of the first logic layout area and the logic output ends of the second logic layout area; the logic output end of the first logic layout area is connected with the metal belt through a connecting hole so as to realize a first logic function; or the logic output end of the second logic layout area is connected with the metal belt through a connecting hole so as to realize the second logic function.
Further, the first logical layout area and the second logical layout area each include: a PPLUS zone, an NPLUS zone, an NWELL zone, and a POLY zone; the PPLUS area is positioned in the NWELL area; the POLY region passes through the PPLUS region and the NPLUS region.
Further, the heights of the PPLUS region, the NPLUS region, the NWELL region, and the POLY region are the same as the heights of the digital standard cells around the layout.
Further, the PPLUS region comprises a first active region, the NPLUS region comprises a second active region, metal layers cover the first active region and the second active region, the first active region is connected with the metal layers above the first active region through a plurality of through holes, and the second active region is connected with the metal layers above the second active region through a plurality of through holes.
Furthermore, the first logic layout area is provided with a power supply end and a grounding end, and a first active area of the first logic layout area is connected with the power supply end; the second logic layout area is provided with a power supply end and a grounding end, and a second active area of the second logic layout area is connected with the grounding end.
Furthermore, the logic output end of the first logic layout area is connected to a power supply end through a first active area of the first logic layout area, and the logic output end of the second logic layout area is connected to a grounding end through a second active area of the second logic layout area.
Further, the first logical layout area is separated from the second logical layout area by a distance of zero.
According to the first aspect of the embodiments of the present application, there is further provided a layout structure of a ROMKEY unit with twice driving force, including two ROMKEY units formed by the layout structure of the ROMKEY unit, where the two ROMKEY units are connected in series.
According to the first aspect of the embodiment of the application, the layout structure of the ROMKEY unit with four times of driving force is further provided, the ROMKEY unit comprises four ROMKEY units formed by the layout structure of the ROMKEY unit, and the four ROMKEY units are connected in series.
According to a second aspect of the embodiments of the present application, there is provided a chip layout method, including:
determining a ROMKEY standard unit matched with a driving force according to the routing distance between the ROMKEY area and the ROM area or the encryption area, wherein the ROMKEY standard unit is formed according to the layout structure of the ROMKEY unit provided by the first aspect of the embodiment of the application;
instantiating the ROMKEY standard units according to the length of the ROMKEY binary key to obtain the required number of ROMKEY standard units;
and calling the ROMKEY standard cell by a layout and wiring tool to perform layout and wiring to form a chip layout.
Further, the step of calling the ROMKEY standard cell to perform layout and wiring by using a layout and wiring tool to form a chip layout includes: generating a netlist for defining a binary code key through a synthesis tool; and calling the ROMKEY standard cell through a layout and wiring tool, and automatically connecting the logic output end of the ROMKEY standard cell according to the binary code defined by the netlist so as to realize the logic output of the corresponding binary code.
Furthermore, the ROMKEY standard units are arranged in a digital logic area of the chip layout in an array form; or the ROMKEY standard units are distributed in a digital logic area of the chip layout in a scattered mode.
The embodiment of the application also provides a chip, which comprises a ROM storage unit and a digital logic area; the digital logic area comprises 2 N Each ROMKEY standard unit, wherein N is a positive integer greater than or equal to 1; the ROMKEY standard cell is formed according to a layout structure of the ROMKEY standard cell provided by the first aspect of the embodiment of the application.
Further, said 2 N The ROMKEY standard cells are arranged in the digital logic area in an array form; or, said 2 N The ROMKEY standard cells are distributed in the digital logic area in a scattered mode.
The ROMKEY unit layout structure is simple and flexible, high in adaptability and applicable to various process fields; when the chip is re-designed, if the ROMKEY key or the ROMCODE needs to be updated, only one layer of mask plate is modified to realize different logic outputs. The layout structure can select the TIE1 and TIE0 to be freely combined according to project requirements, and adopts bottom routing, so that the routing metal layer is low, the concealment is good, and the attack difficulty of using FIB and other modes by a physical attacker is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic diagram of a layout structure of a ROMKEY unit according to an embodiment of the present application;
fig. 2 is a schematic diagram of a layout structure of a ROMKEY unit according to another embodiment of the present application;
FIG. 3 is a block diagram of a first logical layout area and a second logical layout area provided in one embodiment of the present application;
FIG. 4 is a diagram illustrating a concatenation of a first logical layout area and a second logical layout area, according to an embodiment of the present application;
fig. 5 is a layout structure of the ROMKEY unit with logic "1" output provided in the embodiment of the present application;
fig. 6 is a layout structure of the ROMKEY unit with an output of logic "0" provided in the embodiment of the present application;
fig. 7 is a layout structure of a ROMKEY unit with double driving force provided in the embodiment of the present application;
fig. 8 is a layout structure of a ROMKEY unit with four driving forces according to an embodiment of the present disclosure;
fig. 9 is a flowchart of a chip layout method according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when in use, and are used only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another, and are not to be construed as indicating or implying relative importance.
In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "coupled," and the like are to be construed broadly and include, for example, fixed or removable connections or integral parts; may be mechanically, electrically or otherwise in communication with each other; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
As described in the background art, the prior art converts a 128 Bit binary code into 16 different ROMKEY units from high to low, each ROMKEY unit is implemented by arranging ROMKEY _1, ROMKEY _0 and ROMKEY _ EDGE (EDGE layout area) from high to low according to 8-Bit 0 and 1 codes, and 16 ROMKEY units are called during digital back-end design to implement key hardware solidification. The method has the following defects: firstly, the bottom layer layout layers PPLUS (P-type ion implantation area), NWELL (N-well) and NPLUS (N-type ion implantation area) of the ROMKEY _1 and ROMKEY _0 layout areas are not consistent, if a chip needs to update a key and ROMCODE, the whole chip bottom mask plate at least needs to modify four layers of masks, the cost of the plate changing flow sheet is high, and the design is not flexible enough; secondly, binary codes corresponding to 16 ROMKEY units need to be manually solidified into ROMKEY _1 and ROMKEY _0, and design risks exist in the manual solidification process; thirdly, the scheme is limited by the process.
In view of the above problems, an embodiment of the present application provides a layout structure of a ROMKEY unit, including a first logic layout area and a second logic layout area, where the first logic layout area and the second logic layout area are provided with respective logic output ends, and metal strips cover both the upper portions of the logic output ends of the first logic layout area and the logic output ends of the second logic layout area. The logic output end of the first logic layout area is connected with the metal belt through a connecting hole so as to realize a first logic function; or the logic output end of the second logic layout area is connected with the metal belt through a connecting hole so as to realize the second logic function. The layout structure is simple and flexible, has strong adaptability and can be suitable for the field of various process procedures; when the chip is re-designed, if the ROMKEY key or the ROMCODE needs to be updated, only one layer of mask plate is modified to realize different logic outputs. The layout structure can select the logic output end TIE1 and TIE0 to be freely combined according to project requirements, and adopts bottom-layer routing, so that the routing metal layer is low, the concealment is good, and the attack difficulty of using FIB and other modes by a physical attacker is improved.
Referring to fig. 1 and 2, the present embodiment provides a layout structure of a ROMKEY unit, including a first logic layout area and a second logic layout area. The first logic layout area is provided with a logic output end TIE1, the second logic layout area is provided with a logic output end TIE0, and METAL strips Metal2 cover the upper parts of the logic output end TIE1 of the first logic layout area and the logic output end TIE0 of the second logic layout area. As shown in fig. 1, the logic output terminal TIE1 of the first logic layout area is connected to the METAL tape METAL2 through a connection hole VIA1, thereby realizing a function of outputting a logic "1". As shown in fig. 2, the logic output terminal TIE0 of the second logic layout area is connected to the METAL tape METAL2 through the connection hole VIA1, thereby implementing a function of outputting a logic "0".
The first logic layout area and the second logic layout area form an ROMKEY standard unit, a logic output end TIE1 and a logic output end TIE0 are metal layers, and the ROMKEY standard unit is controlled to output logic '1' or logic '0' by connecting the metal layer of the logic output end TIE1 or the metal layer of the logic output end TIE0 through a connecting hole VIA 1. Covering a METAL belt METAL2 on two output ports of the TIE1 and the TIE0, and connecting a connecting hole VIA1 to the TIE1 if logic '1' needs to be output during layout design, so that the TIE1 is communicated with the METAL2, and the output of the ROMKEY standard unit is logic '1'; if the logic '0' needs to be output, the connection hole VIA1 is connected to the TIE0, the TIE0 is communicated with the METAL2, and the ROMKEY standard unit is output as the logic '0'. The metal layer forming the connection hole VIA1 is used as a code point layer of the ROM at the same time and is used for compiling a control logic program of the chip. The ROM code point layer and the output control layer of the ROMKEY standard unit are designed into the same through hole metal layer, and when the chip is subjected to edition modification design, the ROMKEY key or the ROMCODE is updated if necessary, and only one layer of photomask mask (corresponding to VIA 1) is modified.
Fig. 3 is a block diagram of a first logical layout area and a second logical layout area according to an embodiment of the present application. As shown in fig. 3, the first logic layout area includes: a PPLUS region, an NPLUS region, an NWELL region, and a POLY region, the PPLUS region being located within the NWELL region, the POLY region p1 passing through the PPLUS region and the NPLUS region. The height or width of the PPLUS area, the NPLUS area, the NWELL area and the POLY area is the same as that of the digital standard cells around the layout structure, so that splicing is facilitated. The PPLUS region of the first logic layout area includes a first active region d1, metal layers (m 1, m2, m3, m 4) are covered above the first active region d1 and the second active region d2, the first active region d1 is connected to the metal layer m1 through a via c1 so as to be connected to the power supply terminal VCC, and the logic output terminal TIE1 is connected to the metal layer m2 through a via c2 so as to be communicated with the first active region d1 and connected to the power supply terminal VCC through the first active region d 1. The NPLUS region of the first logic layout area includes a second active region d2, and the second active region d2 is connected to the metal layer m3 through a via c4 and the metal layer m4 through a via c5, and thus connected to the ground terminal GND. The POLY region p1 is connected to the metal layer m3 through a via c 3. The second logic layout region includes: a PPLUS zone, an NPLUS zone, an NWELL zone, and a POLY zone, the PPLUS zone being located within the NWELL zone, the POLY zone p1 passing through the PPLUS zone and the NPLUS zone. The height or width of the PPLUS area, the NPLUS area, the NWELL area and the POLY area is the same as that of the digital standard cells around the layout structure, so that splicing is facilitated. The PPLUS region of the second logic layout area includes a first active region d1, metal layers (m 1, m2, m3, m 4) are covered above the first active region d1 and the second active region d2, the first active region d1 is connected with the metal layer m1 through a via hole c1 so as to be connected to a power supply terminal VCC, and the first active region d1 is connected with the metal layer m2 through via holes c2, c 3. The POLY region p1 is connected to the metal layer m2 through a via c 4. The NPLUS area of the second logic layout area includes a second active region d2, and the second active region d2 is connected to the metal layer m4 through vias c5 and c6, and thus connected to the ground terminal GND. The logic output terminal TIE0 is connected to the metal layer m3 through the vias c7 and c8, and thus communicates with the second active region d2, and is connected to the ground terminal GND through the second active region d 2.
As shown in fig. 4, the first logic layout area and the second logic layout area are spliced together, and the logic output terminal TIE1 of the first logic layout area and the logic output terminal TIE0 of the second logic layout area are covered by a METAL strip METAL2, so as to form an ROMKEY unit with one-time driving force. The first logical layout area and the second logical layout area of the ROMKEY unit are separated by zero. The ROMKEY cell includes four ports VCC, GND, TIE1 and TIE 0. Referring to fig. 5, if the ROMKEY unit output is required to be logic "1" when designing the key unit at the digital front end, the logic output terminal TIE1 and the METAL strap METAL2 are connected through the connection hole VIA 1. Referring to fig. 6, if the output of the ROMKEY unit is required to be logic "0" when designing the key unit at the front end of the digital signal, the logic output TIE0 and the METAL strap METAL2 are connected through a connection hole VIA 1.
The layout of the first logic layout area and the second logic layout area of the ROMKEY unit can also be determined according to the driving force required by the process and the chip routing length. The ROMKEY area is far away from the ROM or the encryption area, and when the routing requires strong driving, the ROMKEY unit with double driving force or the ROMKEY unit with quadruple driving force can be adopted. Referring to fig. 7, the double-driving-force ROMKEY unit layout structure includes two single-driving-force ROMKEY units, and the two ROMKEY units in the layout are connected in series. Referring to fig. 8, the four-driving-force ROMKEY unit layout structure includes four one-driving-force ROMKEY units, and 4 ROMKEY units in the layout are connected in series.
The ROMKEY unit layout structure of the embodiment can freely select the logic output terminal TIE1 or TIE0 of the ROMKEY standard unit according to the chip process and design requirements, does not need to manually design and solidify the ROMKEY unit, has simple and flexible structure and strong adaptability, is not limited to the process, and is suitable for various process fields. The layout structure can select the free combination of the TIE1 and TIE0 logic output ends according to project requirements, adopts bottom routing, has low routing metal layer and good concealment, and improves the attack difficulty of physical attackers in FIB and other modes.
Fig. 9 is a flowchart of a chip layout method according to an embodiment of the present invention. As shown in fig. 9, the present embodiment provides a chip layout method, including the following steps:
s1, determining an ROMKEY standard unit matched with the driving force according to the routing distance between the ROMKEY area and the ROM area or the encryption area. The ROMKEY standard cell is formed according to the layout structure of the ROMKEY cell of the above embodiment.
For example, if the routing distance between the ROMKEY area and the ROM area or the encryption area is relatively short, the ROMKEY standard unit with one time of driving force is matched; if the routing distance between the ROMKEY area and the ROM area or the encryption area is relatively far, the ROMKEY standard unit with double driving force or the ROMKEY standard unit with quadruple driving force is matched.
S2, instantiating the ROMKEY standard units according to the length of the ROMKEY binary key to form the required number of ROMKEY standard units. For example, the binary code length of the ROMKEY key is 128 bits, and the ROMKEY standard unit needs to be instantiated 128 times; if the binary code length of the ROMKEY key is 32 bits, the ROMKEY standard unit is instantiated 32 times.
And S3, calling the ROMKEY standard unit through a layout and wiring tool to perform layout and wiring to form a chip layout.
Specifically, a netlist for defining a binary code key is generated through a synthesis tool (Design compiler), a ROMKEY standard cell is called through a layout and routing tool, and the logic output ends of the ROMKEY standard cell are automatically connected according to the binary code defined by the netlist, so that the logic output corresponding to the binary code is realized. For example, if a logic "1" needs to be output, connecting the connection hole VIA1 of the ROMKEY standard cell to TIE1, so that TIE1 is communicated with METAL2, and the ROMKEY standard cell outputs a logic "1"; if the logic '0' needs to be output, the connection hole VIA1 is connected to the TIE0, the TIE0 is communicated with the METAL2, and the ROMKEY standard unit outputs the logic '0'. The metal layer forming the connecting hole VIA1 is also used as a code point layer of the ROM, so that the control logic program of the compiling chip can be obtained. The ROM code point layer and the output control layer of the ROMKEY standard unit are the same through hole metal layer, when the chip layout is subjected to plate change design, if a ROMKEY key or ROMCODE needs to be updated, only one layer of photomask mask plate is modified, and the production cost of mass production chips is greatly saved.
Optionally, the ROMKEY standard cells are arranged in the digital logic region of the chip layout in an array form, or the ROMKEY standard cells are arranged in the digital logic region of the chip layout in a dispersed form. The ROMKEY standard unit is fused in the digital logic area, the occupied area of a chip layout is very small, the wiring metal layer is low, and the concealment is good.
The chip layout method of the embodiment can freely select the logic output terminal TIE1 or TIE0 of the ROMKEY standard unit according to the chip process and design requirements, does not need to manually design and solidify the ROMKEY unit, is very flexible in design realization, is not limited to process, and is suitable for various process fields. According to the method, the TIE1 and the TIE0 of the ROMKEY standard unit can be selected to be freely combined to form the key with the required length according to project requirements, and the bottom layer routing is adopted, so that the attack difficulty of a physical attacker using FIB and other modes is improved.
The embodiment of the invention also provides a chip which comprises a ROM storage unit and a digital logic area. The digital logic area comprises 2 N And (4) a plurality of ROMKEY standard units (N is a positive integer greater than or equal to 1). 2 N The ROMKEY standard cells are arranged in the digital logic area in an array form; or, 2 N The ROMKEY standard cells are distributed in the digital logic area in a scattered mode. The ROMKEY standard cell is formed according to the layout structure of the ROMKEY standard cell in the embodiment. For example, the length of the binary code of the ROMKEY key in the chip is 128 bits, and 128 ROMKEY standard units are adopted; the binary code length of the ROMKEY key in the chip is 32 bits, and 32 ROMKEY standard units are adopted.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (12)
1. A layout structure of a ROMKEY unit comprises a first logic layout area and a second logic layout area, and is characterized in that the first logic layout area and the second logic layout area are provided with respective logic output ends, and metal belts are covered above the logic output ends of the first logic layout area and the second logic layout area;
the logic output end of the first logic layout area is connected with the metal belt through a connecting hole so as to realize a first logic function; or the logic output end of the second logic layout area is connected with the metal belt through a connecting hole so as to realize a second logic function;
the metal layer forming the connecting hole and the code point layer of the ROM are the same through hole metal layer, and the output logic of the ROMKEY unit formed by the first logic layout area and the second logic layout area is controlled by adjusting the logic output end connected with the connecting hole so as to change the password of the ROM;
one ROMKEY unit forms an ROMKEY standard unit, or two ROMKEY units are connected in series to form an ROMKEY standard unit with double driving force, or four ROMKEY units are connected in series to form an ROMKEY standard unit with four driving force;
the ROMKEY standard unit is used for instantiating to form an ROMKEY layout.
2. The layout structure of the ROMKEY unit according to claim 1, wherein the first logic layout area and the second logic layout area each comprise: a PPLUS area, an NPLUS area, an NWELL area and a POLY area; the PPLUS area is positioned in the NWELL area; the POLY region passes through the PPLUS region and the NPLUS region.
3. The layout structure of the ROMKEY cell according to claim 2, wherein the height of the PPLUS region, NPLUS region, NWELL region, and POLY region is the same as the height of the digital standard cell around the layout structure.
4. The layout structure of the ROMKEY cell of claim 2, wherein the PPLUS region comprises a first active region, the NPLUS region comprises a second active region, a metal layer covers the first active region and the second active region, the first active region is connected to the metal layer above the first active region through a plurality of vias, and the second active region is connected to the metal layer above the second active region through a plurality of vias.
5. The layout structure of the ROMKEY unit as claimed in claim 4, wherein the first logic layout area is provided with a power supply terminal and a ground terminal, and the first active region of the first logic layout area is connected with the power supply terminal;
the second logic layout area is provided with a power supply end and a grounding end, and a second active area of the second logic layout area is connected with the grounding end.
6. The layout structure of the ROMKEY cell as claimed in claim 5, wherein the logic output terminal of the first logic layout region is connected to a power supply terminal through the first active region of the first logic layout region, and the logic output terminal of the second logic layout region is connected to a ground terminal through the second active region of the second logic layout region.
7. The layout structure of the ROMKEY cell according to claim 1, wherein the first logic layout area is separated from the second logic layout area by a distance of zero.
8. A chip layout method is characterized by comprising the following steps:
determining a ROMKEY standard unit matched with a driving force according to the routing distance between the ROMKEY area and the ROM area or the encryption area, wherein the ROMKEY standard unit is formed according to the layout structure of the ROMKEY unit in any one of claims 1-7;
instantiating the ROMKEY standard units according to the length of the ROMKEY binary key to obtain the required number of ROMKEY standard units;
and calling the ROMKEY standard cell through a layout and wiring tool to perform layout and wiring to form a chip layout.
9. The chip layout method according to claim 8, wherein the forming of the chip layout by using the ROMKEY standard cell called by the layout and routing tool to perform layout and routing comprises:
generating a netlist for defining a binary code key through a synthesis tool;
and calling the ROMKEY standard cell through a layout and wiring tool, and automatically connecting the logic output end of the ROMKEY standard cell according to the binary code defined by the netlist so as to realize the logic output of the corresponding binary code.
10. The chip layout method according to claim 8, wherein the ROMKEY standard cells are arranged in an array in a digital logic region of the chip layout;
or the ROMKEY standard units are distributed in a digital logic area of the chip layout in a scattered mode.
11. A chip, comprising a ROM memory cell and a digital logic area;
the digital logic area comprises 2 N Each ROMKEY standard unit, wherein N is a positive integer greater than or equal to 1; the ROMKEY standard cell is formed according to the layout structure of the ROMKEY cell of any one of claims 1-7.
12. The chip of claim 11, whichCharacterized in that 2 N The ROMKEY standard cells are arranged in the digital logic area in an array form; or, 2 above N The ROMKEY standard cells are distributed in the digital logic area in a scattered mode.
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