CN114902565A - Partially correlated multisampling single slope ADC with incremental selectable counters - Google Patents
Partially correlated multisampling single slope ADC with incremental selectable counters Download PDFInfo
- Publication number
- CN114902565A CN114902565A CN202080091327.8A CN202080091327A CN114902565A CN 114902565 A CN114902565 A CN 114902565A CN 202080091327 A CN202080091327 A CN 202080091327A CN 114902565 A CN114902565 A CN 114902565A
- Authority
- CN
- China
- Prior art keywords
- conversion
- signal
- amplitude
- ramp
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/0607—Offset or drift compensation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/56—Input signal compared with linear ramp
Abstract
The invention provides a single slope analog-to-digital converter (SS-ADC). The SS-ADC includes: a comparator for comparing an analog signal with ramp signals for analog-to-digital (AD) conversion of a reset level and a signal level, respectively, a plurality of times, wherein an amplitude of the ramp signal for at least one AD conversion other than a last AD conversion of the signal level is smaller than an amplitude of the ramp signal for the last AD conversion of the signal level; a counter for incrementing a count value of each clock by increments until the amplitude of the ramp signal reaches the amplitude of the analog signal; a controller for selecting a multiplier factor of a counter increment per counter clock to obtain the count value corresponding to the number of AD conversions of the signal level which is the same as the number of AD conversions of the reset level, in a case where an amplitude of the ramp signal for a part of the AD conversions of the signal level does not reach an amplitude of the analog signal. The invention reduces temporal noise without increasing the switching time.
Description
Technical Field
The present invention relates to an analog-to-digital converter for an image sensor.
Background
Image sensors, such as Complementary Metal Oxide Semiconductor (CMOS) image sensors, Charge Coupled Device (CCD) image sensors, and the like, are classified as one of the most noise sensitive devices because most of them obtain a voltage output with a conversion gain in the order of microvolts. Therefore, several noise reduction techniques, such as multisampling techniques, have been developed. The multiple sampling technique is to average the results of the same N analog to digital (AD) conversions to reduce the temporal noise by a factor of 1/(square root of N). However, this technique also requires time to perform AD conversion N times, and limits the frame rate up-conversion.
Disclosure of Invention
The invention provides a method based on a multisampling technology, which is used for reducing the time noise of a single slope analog-to-digital converter (SS-ADC) and analog inputs thereof (namely a column parallel ADC and a pixel source follower in a CMOS image sensor) and inhibiting the increase of the conversion time thereof.
According to a first aspect, there is provided a single slope analog to digital converter (SS-ADC) comprising: a comparator for comparing an analog signal with ramp signals for analog-to-digital (AD) conversion of a reset level and a signal level, respectively, a plurality of times, wherein an amplitude of the ramp signal for at least one AD conversion other than a last AD conversion of the signal level is smaller than an amplitude of the ramp signal for the last AD conversion of the signal level; a counter for incrementing a count value of each clock by increments until the amplitude of the ramp signal reaches the amplitude of the analog signal; a controller for selecting a multiplier factor of a counter increment per counter clock to obtain the count value corresponding to the number of AD conversions of the signal level which is the same as the number of AD conversions of the reset level, in a case where an amplitude of the ramp signal for a part of the AD conversions of the signal level does not reach an amplitude of the analog signal.
In a first possible implementation manner of the first aspect, an amplitude of the ramp signal for the AD conversion of the signal level other than the last AD conversion is the same as an amplitude of the ramp signal for the AD conversion of the reset level.
In a second possible implementation manner of the first aspect, the ramp signals used for the last two or more AD conversions of the signal level have the same amplitude and are larger than the ramp signal used for the first AD conversion of the signal level.
In a third possible implementation form of the first aspect, an amplitude of the ramp signal for the AD conversion other than the last AD conversion of the signal level is larger than an amplitude of the ramp signal for the AD conversion of the reset level but not larger than an amplitude of the ramp signal for the last AD conversion of the signal level.
In a fourth possible implementation form of the first aspect, the amplitude of the ramp signal for the AD conversion other than the last AD conversion of the signal level includes at least two levels but is not larger than the amplitude of the ramp signal for the last AD conversion of the signal level.
In a fifth possible implementation manner of the first aspect, the controller detects that the amplitude of the ramp signal for a part of the AD conversion of the signal level does not reach the amplitude of the analog signal by detecting the absence of the output of the comparator for the AD conversion.
In a sixth possible implementation form of the first aspect, an amplitude of the ramp signal used for the AD conversion of the signal level is equal to or larger than an amplitude of a ramp signal used for a previous AD conversion; and at least one of the amplitude sequences is smaller than the amplitude of the last AD conversion.
According to a second aspect, there is provided a ramp generator for generating ramp signals for analog to digital (AD) conversion of a reset level and a signal level, respectively, a plurality of times, wherein an amplitude of the ramp signal for at least one AD conversion of the signal level other than a last AD conversion is smaller than an amplitude of the ramp signal for the last AD conversion of the signal level.
According to a third aspect, there is provided an analog to digital (AD) conversion method, the method comprising: comparing an analog signal with ramp signals for analog-to-digital (AD) conversion of a reset level and a signal level, respectively, a plurality of times, wherein an amplitude of the ramp signal for at least one AD conversion other than a last AD conversion of the signal level is smaller than an amplitude of the ramp signal for the last AD conversion of the signal level; incrementally increasing the count value of each clock until the amplitude of the ramp signal reaches the amplitude of the analog signal; in a case where the amplitude of the ramp signal for a part of the AD conversion of the signal level does not reach the amplitude of the analog signal, the incremental multiplier factor is selected to obtain a count value corresponding to the number of times of the AD conversion of the signal level which is the same as the number of times of the AD conversion of the reset level.
Drawings
In order to more clearly describe embodiments of the present invention or technical solutions in the prior art, the drawings required for describing the embodiments or the prior art are briefly introduced below. It is clear that the figures in the following description only show some embodiments of the invention, and that a person skilled in the art can also derive other figures from them without inventive effort.
FIG. 1 is a schematic diagram of a partially Correlated Multiple Sampling SS-ADC (PCMS SS-ADC) provided by an embodiment of the present invention;
fig. 2(a) shows an example of a RAMP waveform for Correlated Double Sampling (CDS);
fig. 2(b) shows an example of a RAMP waveform for Correlated Multiple Sampling (CMS);
fig. 3(a) shows an example of a RAMP waveform for partial multisampling;
FIG. 3(b) shows a small signal comparator output example;
FIG. 3(c) shows a large signal comparator output example;
fig. 4(a) shows an example of the RAMP waveform shown in fig. 3 (a);
FIG. 4(b) shows an example of the small signal CMP _ OUT shown in FIG. 3 (b);
FIG. 4(b1) shows the count value of CMP _ OUT shown in FIG. 3 (b);
FIG. 4(b2) shows data stored in latches;
fig. 4(c) shows an example of the large signal CMP _ OUT shown in fig. 3 (c);
FIG. 4(c1) shows the count value of CMP _ OUT shown in FIG. 3 (c);
FIG. 4(c2) shows data stored in latches;
fig. 5 shows an example of a flow chart of AD conversion provided by an embodiment of the present invention;
FIG. 6 illustrates an exemplary RAMP waveform having multiple RAMPs of a full scale range;
fig. 7 shows an exemplary RAMP waveform in which the magnitude of the falling slope for AD conversion of the signal level (except for the last time) is set to an intermediate level between the magnitude of the falling slope for AD conversion of the reset level and the magnitude of the full-scale range;
fig. 8 shows an exemplary RAMP waveform in which the magnitude of the falling slope for AD conversion of the signal level is gradually increased;
FIG. 9 shows a schematic diagram of the increment selectable counter shown in FIG. 1;
fig. 10(a) shows an example of a RAMP waveform and a small-signal input;
fig. 10(a1) shows an exemplary waveform of CNT _ EN;
FIG. 10(a2) shows an exemplary waveform of INDEX;
fig. 10(a3) shows an exemplary waveform of MSEN;
fig. 10(a4) shows an exemplary waveform of RST _ CNT;
fig. 10(a5) shows an exemplary waveform of INV;
fig. 10(a6) shows an exemplary waveform of the LAT;
fig. 10(a7) shows an exemplary waveform of RST _ LAT;
FIG. 10(b) shows an example of the small signal CMP _ OUT shown in FIG. 3 (b);
FIG. 10(b1) shows the count value of CMP _ OUT shown in FIG. 3 (b);
FIG. 10(b2) shows data stored in latches;
fig. 11(a) shows an example of a RAMP waveform and a large-signal input;
fig. 11(a1) shows an exemplary waveform of CNT _ EN;
FIG. 11(a2) shows an exemplary waveform of INDEX;
fig. 11(a3) shows an exemplary waveform of MSEN;
fig. 11(a4) shows an exemplary waveform of RST _ CNT;
fig. 11(a5) shows an exemplary waveform of INV;
fig. 11(a6) shows an exemplary waveform of LAT;
FIG. 11(a7) shows an exemplary waveform of RST _ LAT;
fig. 11(c) shows an example of a large signal CMP _ OUT shown in fig. 3 (c);
FIG. 11(c1) shows count values of CMP _ OUT shown in FIG. 3 (c);
fig. 11(c2) shows data stored in the latch.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present invention, shall fall within the protection scope of the present invention.
FIG. 1 is a schematic diagram of a partially Correlated Multiple Sampling SS-ADC (PCMS SS-ADC) provided by an embodiment of the present invention. Fig. 1 includes a part of the left pixel circuit: a Floating Diffusion (FD), a selection Switch (SEL), and a current source connected in series between a power supply voltage and ground. The ADC is connected between the drain of the SEL and the current source. The PIXEL signal (PIXEL) as an analog signal is input into an inverting input terminal of the Comparator (CMP) through the capacitor, and the RAMP signal (RAMP) generated by the RAMP generator is input into a non-inverting input terminal of the CMP through the capacitor. The RAMP generator outputs a RAMP waveform for partial multisampling. The RAMP generator may be shared by the SS-ADCs for pixels disposed in the same column. The output of the CMP is input into an increment optional counter, which includes a Counter (CNT) and an increment selector, which is a controller of the CNT. The CNT counts a clock signal (CLK), e.g., counts the number of cycles of the CLK, increments a count value for each cycle of the CLK, which is stored in a latch (not shown in fig. 1) according to a control signal. The increment selector may select an increment per cycle of the CLK so as to obtain the count value corresponding to AD conversion a plurality of times.
Before an example of a RAMP waveform provided by the present invention is explained with reference to fig. 3(a), a typical RAMP waveform is explained with reference to fig. 2(a) and 2 (b). Fig. 2(a) shows an example of a RAMP waveform for Correlated Double Sampling (CDS). The solid line represents the RAMP signal (RAMP) and the dotted line represents the pixel output at the reset level. The reset level and signal level are respectively sampled as follows: the first falling slope is used for AD conversion of the pixel output at the reset level, and the second falling slope is used for AD conversion of the pixel output at the signal level. CNTs are counted from the beginning of the first falling slope and until the first falling slope intersects the dashed line. The count value corresponds to the reset level. If there is no signal from the pixel, the signal level is the same as the reset level, i.e. the level of the dashed line does not change. CNTs are counted from the beginning of the second falling slope and counted until the second falling slope intersects the dashed line. If there is a signal from the pixel, the dashed line drops to a level corresponding to the signal amplitude below the reset level, and the CNT starts counting from the beginning of the second falling slope and counts until the second falling slope intersects the dashed line. The count value corresponds to the signal level. The output level is defined as the difference between the count value corresponding to the signal level and the count value corresponding to the reset level.
Fig. 2(b) shows an example of a RAMP waveform for Correlated Multiple Sampling (CMS). To reduce temporal noise, the reset level is sampled three times, then the signal level is sampled three times, and accordingly the sampled values of the reset level and the sampled values of the signal level are averaged. The output level is defined as the difference between these average values. The number of sampling is not limited to three. Different numbers of samples are applicable. If the number of samples is 4, the temporal noise will be reduced to 1/(square root of 4) — 1/2. As can be seen from fig. 2(a) and 2(b), the time required for the CMS (fig. 2(b)) is increased compared to the CDS (fig. 2 (a)).
Fig. 3(a) shows an example of a RAMP waveform for partial multisampling. The solid line represents the RAMP signal (RAMP). In fig. 3(a), the reset level and the signal level are sampled 4 times, respectively, and only the full scale range is applied to the last falling slope of the AD conversion for the signal level, as compared with fig. 2 (b). In other words, the falling slope of the AD conversion for the signal level (except for the last time) is equal to or larger than the falling slope of the AD conversion for the reset level, and is smaller than the last falling slope of the AD conversion for the signal level. The duration of the latter half of RAMP shown in fig. 3(a) is shorter than the duration of the latter half of RAMP having four falling slopes of the full scale range.
With respect to the broken line in fig. 3(a), the first half represents the pixel output at the reset level, and the second half represents the pixel output at the small-signal level. In fig. 3(a), the small signal level is shown as if it is the same as the reset level. With respect to the dotted line in fig. 3(a), the first half represents the pixel output at the reset level, and the second half represents the pixel output at the large signal level.
Fig. 3(b) shows an example of the comparator output for the pixel output at the reset level and small signal level (as shown by the dashed line in fig. 3 (a)). When the falling slope of RAMP crosses the dashed line downwards, the pulse rises; when the rising edge of RAMP crosses the dashed line, the pulse falls. The CNT counts from the beginning of the falling slope to the rising edge of the comparator output as indicated by the arrow in fig. 3 (b).
Fig. 3(c) shows an example of the comparator outputs of the pixel outputs at the reset level and the large signal level shown by the dotted line in fig. 3 (a). When the falling slope of RAMP crosses the dashed line downwards, the pulse rises; when the rising edge of RAMP crosses the dashed line, the pulse falls. The first four pulses correspond to the reset level and the last pulse corresponds to the large signal level. The second half of the dotted line, where the pixel output is at the large signal level, does not cross the three small falling slopes in the second half of the RAMP, but rather the last falling slope. The rising edge of the comparator output is used to stop counting. For the second half of RAMP in fig. 3(c), the CNTs are counted in 4-fold increments from the beginning of the last falling slope to the rising edge of the comparator output corresponding to the last falling slope, as described below.
Referring to fig. 4(a) to 4(c2), the relationship between the comparator output, the count value of CNT, and the data stored in the latch is described below. Fig. 4(a), 4(b), and 4(c) are the same as fig. 3(a), 3(b), and 3(c), respectively. FIG. 4(b1) shows the count value of CMP _ OUT shown in FIG. 4 (b); fig. 4(b2) shows data stored in the latch. Initially, the count value shown in fig. 4(b1) (COUNTER) is reset to 0, and the value shown in fig. 4(b2) (DATA) is 0. When the first falling slope of RAMP starts, the CNTs start to count. The count value increases linearly. At the rising edge of the CMP _ OUT (comparator output), the CNT stops counting. When the next falling slope of RAMP begins, the CNT resumes counting. The count value is accumulated for 4 falling slopes. The count value (positive number) is converted to a negative value and stored in the latch, and then the count value is reset to 0. The CNT operates in a similar manner for CMP _ OUT corresponding to the second half of the RAMP. The accumulated count value is substantially the same as an accumulated count value of a first half of the RAMP. As shown in the last part of fig. 4(b2), the accumulated count value is added to the data stored in the latch. The data corresponds to a value calculated by subtracting the count value of 4 times AD conversion of the reset value from the count value of 4 times AD conversion of the signal value. A value calculated by dividing the data in the latch by 4 is equal to a difference between an average value of 4 AD conversions of the signal level and an average value of 4 AD conversions of the reset level.
Before converting the count value of the 4 times AD conversion of the reset level to a negative value and storing it in the latch, the value may be divided by 4; the count value of the 4 AD conversions of the signal level may be divided by 4 before storing the value in the latch. In this case, the value finally stored in the latch is the difference between the average value of the 4 times of AD conversion of the signal level and the average value of the 4 times of AD conversion of the reset level.
FIG. 4(c1) shows the count value of CMP _ OUT shown in FIG. 4 (c); fig. 4(c2) shows the data stored in the latch. In fig. 4(a), the values of the dotted line and the dotted line are the same for the first half of the RAMP, and the count value in fig. 4(c1) and the data in fig. 4(c2) are the same as the count value in fig. 4(b1) and the data in fig. 4(b2), respectively.
When the first falling slope of the second half of the RAMP starts, the CNTs start to count. The count value increases linearly as shown in fig. 4(c 1). At a rising edge after the first falling slope of the second half of the RAMP, an incremental selectable counter knows that the signal level is not detected because the first falling slope of the second half of the RAMP does not cross the dotted line and CMP _ OUT corresponding to the first falling slope of the second half of the RAMP is not generated. Then, the count value is reset. As described above, for example, the CNT counts the number of cycles of a clock signal (CLK), and increments a count value for each cycle of the CLK. The CNT increases the increment per cycle of the CLK by three times, that is, the increment (hereinafter referred to as "lift increment") is four times the increment (hereinafter referred to as "normal increment") for the first half of the RAMP. This means that a count value counted 1 time using the "boost increment" corresponds to a count value counted 4 times using the "normal increment". Disabling the CNT at the end of the third falling slope of the second half of the RAMP, as described below.
Even if the signal level is detected in the first falling slope of the latter half of the RAMP, in the case where the signal level is close to the level at the end of the falling slope, the signal level of the second falling slope or the third falling slope may not be detected due to noise. Even in this case, the count value is reset and the increment is increased by three times in the same manner as described above. However, as long as the signal level is detected, assuming that the number of falling slopes used for AD conversion of the signal level is N, the signal level continues to be detected until the (N-1) -th falling slope of the latter half of the RAMP ends.
When the fourth falling slope of the second half of the RAMP starts, the CNTs start to count. In fig. 4(c1), the count value is increased at a rate of 4 times. At the rising edge of CMP _ OUT shown in fig. 4(c), the CNT stops counting. As shown in the last part of fig. 4(c2), the count value is added to the data stored in the latch. This data is equal to a value calculated by subtracting the count value of 4 AD conversions having the reset value of "normal increment" from the count value of 1 AD conversion having the signal value of "lift increment". A value calculated by dividing the data in the latch by 4 is equal to a difference between 1 AD conversion of the signal level and an average value of 4 AD conversions of the reset level.
The value accumulated for 4 times AD conversion of the reset level may be divided by 4 before converting it into a negative value and storing it in the latch. In this case, when any one of the first to third falling slopes of the signal level is not detected, the increment may not be increased by three times. The value finally stored in the latch is the difference between the 1 AD conversion of the signal level and the average value of the 4 AD conversions of the reset level.
Fig. 5 shows an example of a flow chart of AD conversion provided by an embodiment of the present invention. According to a Partial Correlated Multiple Sampling (PCMS) SS-ADC according to the present invention, CNT selects either a CMS mode or a CDS mode by detecting the presence or absence of a comparator output in AD conversion of a signal level (excluding the last AD conversion of the signal level). The amplitude of the falling slope for the AD conversion of the signal level (except for the last AD conversion of the signal level) is smaller than the amplitude of the last falling slope with a full scale range. Thus, the PCMS SS-ADC may select the following operating mode: a CMS mode for small signal levels, or a CDS mode for large signal levels. For the CDS mode, since the AD conversion of the reset level has a count value for N times of sampling, the last AD conversion of the signal level is performed using N-fold increments (the increment of the last signal is N times of the "normal increment").
Referring to fig. 5, in step S1, N times of AD conversion of the reset level is performed and the result is saved. In step S2, AD conversion of the signal level is performed, wherein the amplitude of the ramp is smaller than the full-scale range. In step S3, it is determined whether there is a comparator output. If so, the process proceeds to step S5. If not, in step S4, the counter is reset, the increment of the counter is set to N times, and waiting until the (N-1) th AD conversion of the signal level ends. In step S5, it is determined whether the 1 st to (N-1) th AD conversions of the signal level are all completed. If so, the process passes to step S6. If not, the process proceeds to step S2. In step S6, the last AD conversion of the signal level is performed, where the magnitude of the ramp is the full-scale range. In step S7, the difference between the average value of the AD conversion of the signal level and the average value of the AD conversion of the reset level is output.
In fig. 3(a), the full-scale range is applied only to the last falling slope of the AD conversion for the signal level. The magnitude of the falling slope of the AD conversion for the signal level (excluding the last time) may be varied between the magnitude of the falling slope of the AD conversion for the reset level and the magnitude of the full-scale range. Fig. 6 to 8 show modifications of the RAMP waveform. In any case, the duration of the latter half of RAMP is shorter than the duration of the latter half of RAMP having four falling slopes of the full scale range.
Fig. 6 shows an exemplary RAMP waveform with multiple falling slopes over a Full Scale Range (FSR). The full scale range is applied to the last plurality of falling slopes. Assuming that the number of falling slopes for AD conversion of a signal level is N, the full-scale range is applied to N or less falling slopes for AD conversion of the signal level. In fig. 6, the amplitudes of the last two falling slopes are the full scale range, and the amplitudes of the first two falling slopes of the second half of RAMP are S 0 . If the amplitude of the analog input is not greater than S 0 Then CMS sampled 4 times is applied.
If the amplitude of the analog input is greater than S 0 Then CMS sampled 2 times is applied. In this case, at the first rising edge of the latter half of the RAMP, the increment option counter knows that the signal level is not detected because CMP _ OUT corresponding to the first falling slope of the latter half of the RAMP is not generated. Then, CNT resets the count value, doubles the increment per cycle of CLK, and is disabled at the end of the second falling slope, and then performs AD conversion of the signal level for the last two falling slopes.
Fig. 7 shows an exemplary RAMP waveform in which AD conversion for signal level (last time)Except for) is set to an intermediate level S between the amplitude of the falling slope of the AD conversion for the reset level and the amplitude of the Full Scale Range (FSR) 0 '. If the amplitude of the analog input is not greater than S 0 ', CMS sampling N times is applied. If the amplitude of the analog input is greater than S 0 ', CDS is applied. The RAMP waveform extends the amplitude of the signal level for multiple sampling.
Fig. 8 shows an exemplary RAMP waveform in which the magnitude of the falling slope for AD conversion of the signal level gradually increases. Multiple multisampling patterns may be provided for several amplitude ranges of the analog input. In the case of sampling 4 times, the amplitude for AD conversion of the signal level is set to S 0 、S 0 、S 1 And Full Scale Range (FSR) as shown in fig. 8. If the amplitude of the analog input is not greater than S 0 Then CMS sampled 4 times is applied. If the amplitude of the analog input is greater than S 0 But not more than S 1 Then CMS sampled 2 times is applied. If the amplitude of the analog input is greater than S 1 Then CDS is applied.
If the amplitude of the analog input is greater than S 0 Then at the first rising edge of the second half of the RAMP, the incremental optional counter knows that the signal level was not detected because CMP _ OUT corresponding to the first falling slope of the second half of the RAMP was not generated. CNT then resets the count value, doubling the increment per cycle of CLK, and is disabled at the end of the second falling slope. When the third falling slope of RAMP begins, the CNT resumes counting. If the amplitude of the analog input is not greater than S 1 AD conversion of the signal level is performed for the last two falling slopes.
If the amplitude of the analog input is greater than S 1 Then at the third rising edge of the second half of the RAMP, the incremental optional counter knows that the signal level is not detected because CMP _ OUT corresponding to the third falling slope of the second half of the RAMP is not generated. Then, the CNT resets the count value. The CNT triples the increment per cycle of the CLK,i.e., the increment is four times as large as the "normal increment", and AD conversion of the signal level is performed for the last falling slope. In this case, one of "normal increment", two-time increment, and four-time increment may be specified using an additional signal or an additional bit.
The CNTs shown in fig. 1, 4(b1), and 4(c1) are explained as an addition counter that increments the count value. The CNT may be implemented as a down counter and an up counter; for the AD conversion of the reset level, the down counter decrements the count value, the decrement being a negative value of the "normal increment" as described above; the up-counter increments the count value for AD conversion of the signal level. In this case, when the count value for AD conversion of the reset level is stored in the latch, it is not necessary to convert the count value to a negative value.
Fig. 9 shows a schematic diagram of the incremental alternative counter shown in fig. 1. FIG. 9 shows components other than the CNT and incremental selector shown in FIG. 1, and shows the control signals in detail. "CMP _ OUT", "CNT _ EN", "ADC _ CLK", and "LAT _ OUT" shown in fig. 9 correspond to "CMP _ OUT", "monitor enable", "CLK", and "digital output" shown in fig. 1.
Fig. 10(a) to 10(b2) show waveforms of control signals related to the increment selectable counter when the analog input is a small signal shown by a dotted line in fig. 4 (a). Fig. 10(a) shows the RAMP waveform and the dotted line shown in fig. 4 (a). Fig. 10(b), 10(b1), and 10(b2) are the same as fig. 4(b), 4(b1), and 4(b2), respectively. The duration when CNT _ EN is "high" corresponds to the falling slope of the RAMP. The CMP _ OUT detector (fig. 9) masks ADC _ CLK (fig. 9) using CNT _ EN and CMP _ OUT, i.e., ADC _ CLK is counted from the rising edge of CNT _ EN to the rising edge of CMP _ OUT. Assuming that the number of falling slopes for AD conversion of a signal level is N, INDEX is "high" from the rising edge of the first CNT _ EN pulse to the falling edge of the (N-1) th CNT _ EN pulse of the latter half of the RAMP. When INDEX is "high", the switch can be made from CMS to CDS. A Multiple Sampling Enable (MSEN) selects the CMS or the CDS. For example, when the MSEN is "high", it indicates that the CMS is selected; when the MSEN is "low" this indicates that the CDS is selected. RST _ CNT is used to reset the count value in the counter. When LAT is "high", the count value in the counter is transferred to the latch and the adder-subtractor. If INV is HIGH, the count value (positive number) is converted to a negative value and stored in the latch. If INV is LOW, the count value is stored in the latch as it is. When RST _ LAT is "high", the data stored in the latch is reset to 0.
Fig. 11(a) to 11(c2) show waveforms of control signals associated with the increment selectable counter when the analog input is a large signal as shown by a dotted line in fig. 4 (a). Fig. 11(a) shows the RAMP waveform and the dotted line shown in fig. 4 (a). Fig. 11(c), 11(c1), and 11(c2) are the same as fig. 4(c), 4(c1), and 4(c2), respectively, and fig. 11(a1), 11(a2), and 11(a5) to 11(a7) are the same as fig. 10(a1), 10(a2), and 10(a5) to 10(a7), respectively. Fig. 11(a3) and 11(a4) are different from fig. 10(a3) and 10(a 4). When the first falling slope of the second half of the RAMP starts, and the CNT _ EN becomes "high", the counter (fig. 9) starts counting. The count value increases linearly. At the rising edge of RAMP, the CNT _ EN goes "low". Since the CMP _ OUT does not become "high" when the CNT _ EN is "high", a CMS/CDS determination circuit (fig. 9) selects CDS by making the MSEN "low". Since the counter resumes counting on the rising edge of the CNT _ EN (when the falling slope of the RAMP begins), the RST _ CNT is "high" from the falling edge of the MSEN to the falling edge of the INDEX.
As shown in fig. 10, in the case where the amplitude of the analog input is small, the PCMS SS-ADC operates in the same manner as the conventional CMS and outputs the AD conversion result with a noise reduction factor of 1/(square root of N). On the other hand, in the case where the amplitude of the analog input is large, the AD conversion of the reset level operates in the same manner as in the case where the amplitude is small, and the last AD conversion of the signal level operates using N-fold increments of a counter per count clock.
The invention can be used for reducing the noise level of the CMOS image sensor. In lower light conditions, the present invention halves the noise level by setting the number of multisampling repetitions to 4. If the ramp amplitude for the first 3 AD conversions of the signal level is set to 1/3 of the full scale range, the AD conversion time for the multisampling can be shortened to 1/3 compared to the conventional CMS.
The present invention can be used for fingerprint sensors in addition to CMOS image sensors, since the present invention works for single slope ADCs.
The effect of the above implementation of PCMS SS-ADC is as follows:
(1) the ADC time increase of CMS implementations can be suppressed.
(2) A common RAMP generator can be used to achieve a partial multisampling effect. This means that there is no need to consider waveform matching of a plurality of RAMP channels, and also no need to consider RAMP waveform distortion caused by connection variation of RAMP and comparator.
(3) Since the PCMS SS-ADC only requires modification of the digital circuit block of the conventional SS-ADC, enlargement of the chip area for implementing additional functions can be suppressed.
(4) There is no need to add a new vertical control signal through the crosstalk sensitive comparator area.
The above disclosure is only exemplary embodiments of the present invention and is of course not intended to limit the scope of protection of the invention. It will be understood by those skilled in the art that all or part of the above-described embodiments may be implemented and equivalents thereof may be modified as required by the claims appended hereto.
Claims (9)
1. A single slope analog to digital converter (SS-ADC), comprising:
a comparator for comparing an analog signal with ramp signals for analog-to-digital (AD) conversion of a reset level and a signal level, respectively, a plurality of times, wherein an amplitude of the ramp signal for at least one AD conversion other than a last AD conversion of the signal level is smaller than an amplitude of the ramp signal for the last AD conversion of the signal level;
a counter for incrementing a count value of each clock by increments until the amplitude of the ramp signal reaches the amplitude of the analog signal;
a controller for selecting a multiplier factor of a counter increment per counter clock to obtain the count value corresponding to the number of AD conversions of the signal level which is the same as the number of AD conversions of the reset level, in a case where an amplitude of the ramp signal for a part of the AD conversions of the signal level does not reach an amplitude of the analog signal.
2. The SS-ADC of claim 1, wherein an amplitude of the ramp signal used for the AD conversion of the signal level other than the last AD conversion is the same as an amplitude of the ramp signal used for the AD conversion of the reset level.
3. The SS-ADC of claim 1 wherein the ramp signals for the last two or more AD conversions of said signal level have the same amplitude and are greater than the ramp signal for the first AD conversion of said signal level.
4. The SS-ADC of claim 1, wherein an amplitude of said ramp signal for said AD conversion of said signal level other than the last AD conversion is larger than an amplitude of said ramp signal for said AD conversion of said reset level.
5. The SS-ADC of claim 1 wherein the amplitude of said ramp signal for said AD conversion other than the last AD conversion of said signal level comprises at least two levels.
6. The SS-ADC of claim 1 wherein said controller detects that the amplitude of said ramp signal for a portion of said AD conversion of said signal level has not reached the amplitude of said analog signal by detecting a lack of output by said comparator for said AD conversion.
7. The SS-ADC of claim 1, wherein an amplitude of said ramp signal for said AD conversion of said signal level is equal to or greater than an amplitude of a ramp signal for a previous AD conversion; and at least one of the amplitude sequences is smaller than the amplitude of the last AD conversion.
8. A ramp generator for generating ramp signals for analog-to-digital (AD) conversion of a reset level and a signal level, respectively, a plurality of times, wherein an amplitude of the ramp signal for at least one AD conversion other than a last AD conversion of the signal level is smaller than an amplitude of the ramp signal for the last AD conversion of the signal level.
9. An analog-to-digital (AD) conversion method, comprising:
comparing an analog signal with ramp signals for analog-to-digital (AD) conversion of a reset level and a signal level, respectively, a plurality of times, wherein an amplitude of the ramp signal for at least one AD conversion other than a last AD conversion of the signal level is smaller than an amplitude of the ramp signal for the last AD conversion of the signal level;
incrementing the count value of each clock in increments until the amplitude of the ramp signal reaches the amplitude of the analog signal;
in a case where the amplitude of the ramp signal for a part of the AD conversion of the signal level does not reach the amplitude of the analog signal, the incremental multiplier factor is selected to obtain a count value corresponding to the number of the AD conversion of the signal level that is the same as the number of the AD conversion of the reset level.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2020/070360 WO2021134803A1 (en) | 2020-01-04 | 2020-01-04 | Partial correlated multiple sampling single slope adc with increment selectable counter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114902565A true CN114902565A (en) | 2022-08-12 |
Family
ID=76687028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080091327.8A Pending CN114902565A (en) | 2020-01-04 | 2020-01-04 | Partially correlated multisampling single slope ADC with incremental selectable counters |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114902565A (en) |
| WO (1) | WO2021134803A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5181087B2 (en) * | 2006-08-31 | 2013-04-10 | トリクセル | Single slope analog-to-digital converter |
| CN101964662B (en) * | 2010-10-12 | 2013-01-09 | 浙江大学 | Improved single-slope serial analog-digital converter |
| KR102170619B1 (en) * | 2014-07-03 | 2020-10-28 | 삼성전자주식회사 | Image sensor and device having the image sensor |
| KR102261587B1 (en) * | 2014-12-05 | 2021-06-04 | 삼성전자주식회사 | Image sensor for improving nonlinearty of low code region, method thereof, and device including the same |
| US9960783B2 (en) * | 2015-09-18 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company Ltd. | Conditional correlated multiple sampling single slope analog-to-digital converter, and associated image sensor system and method |
| US10348323B2 (en) * | 2015-11-06 | 2019-07-09 | Ams Sensors Belgium Bvba | Analog-to-digital conversion and method of analog-to-digital conversion |
-
2020
- 2020-01-04 CN CN202080091327.8A patent/CN114902565A/en active Pending
- 2020-01-04 WO PCT/CN2020/070360 patent/WO2021134803A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021134803A1 (en) | 2021-07-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101365408B1 (en) | Counter Circuit, Device Including the Same, and Counting Method | |
| KR100833177B1 (en) | Signal converting circuit and Signal converting method for automatically adjusting offset | |
| KR101448917B1 (en) | Apparatus and Method for converting Analogue to Digital using pseudo multiple sampling | |
| KR100826513B1 (en) | Correlated Double Sampling and Analogue to Digital Converting Apparatus using multiple sampling in CMOS image Sensor | |
| US8111312B2 (en) | Solid-state imaging device, method of driving the same, and camera | |
| JP5181087B2 (en) | Single slope analog-to-digital converter | |
| TW444404B (en) | Autocalibaration of an A/D converter within a CMOS type image sensor | |
| TWI488442B (en) | Integration and analog to digital conversion circuit with common capacitors and operating method thereof | |
| KR20180072134A (en) | Analog-digital converting apparatus, and cmos image sensor thereof | |
| KR101698632B1 (en) | Charge-sharing digital to analog converter and successive approximation analog to digital converter | |
| EP3606043B1 (en) | Analog-to-digital converter circuit, image sensor, and analog-to-digital conversion method | |
| US20020122129A1 (en) | CMOS image sensor improving picture quality | |
| JP4550957B2 (en) | Photodetector | |
| TW201820791A (en) | Analog-to-digital converter | |
| CN109792498B (en) | Analog-to-digital conversion circuit, image sensor, and analog-to-digital conversion method | |
| US10306171B2 (en) | Analog-digital converter, readout circuit and CIS including the same | |
| CN114902565A (en) | Partially correlated multisampling single slope ADC with incremental selectable counters | |
| US8174427B2 (en) | A/D converter and solid-state imaging device | |
| CN114374806B (en) | Monoclinic analog-to-digital converter and image sensor | |
| US8704695B2 (en) | Analog-to-digital converter | |
| JP6903154B2 (en) | Amplifier circuit and analog-to-digital conversion system equipped with it | |
| JP7412551B2 (en) | Adaptive correlated multiple sampling with input signal level shift | |
| US8917098B2 (en) | Converter circuit and method of driving the same | |
| WO2022205126A1 (en) | Single slope analog-to-digital converter, associated image sensor, and method | |
| CN106303311B (en) | Output method of pixel photosensitive value |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |