CN114899224A - Heterojunction structure, semiconductor device structure and manufacturing method thereof - Google Patents

Heterojunction structure, semiconductor device structure and manufacturing method thereof Download PDF

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Publication number
CN114899224A
CN114899224A CN202210411896.7A CN202210411896A CN114899224A CN 114899224 A CN114899224 A CN 114899224A CN 202210411896 A CN202210411896 A CN 202210411896A CN 114899224 A CN114899224 A CN 114899224A
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layer
heterojunction
heterostructure
substrate
active
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王鹏飞
陆磊
王云萍
杨欢
周晓梁
张盛东
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

A heterojunction structure, a semiconductor device structure and a manufacturing method thereof are provided, wherein an intermediate structure layer material is formed between two semiconductor active layers, the intermediate structure layer material can prevent the diffusion of metal elements between the two semiconductor active layers on one hand, and the energy band of the intermediate structure layer material has a lower potential barrier for electrons on the other hand, so that the electrons can freely migrate or largely tunnel between the two semiconductor active layers, and therefore, a more ideal heterojunction interface can be formed between a first active layer and a second active layer, and a deeper heterojunction potential well is obtained. And a more ideal semiconductor heterojunction is formed, so that the performance advantage of the heterojunction in the metal oxide semiconductor device is truly utilized and exerted. The performance of the existing transistor with high mobility and high stability or the performance of the existing diode with high voltage resistance and the like is improved.

Description

Heterojunction structure, semiconductor device structure and manufacturing method thereof
Technical Field
The invention relates to a heterojunction field effect transistor, in particular to a heterojunction structure, a semiconductor device structure and a manufacturing method thereof.
Background
The heterojunction of the semiconductor is a special PN junction and is formed by sequentially depositing more than two layers of different semiconductor material films on the same base. Due to the energy band difference (mainly the difference of the conduction band bottom level and the fermi level) of the two different semiconductors, a potential well and a potential barrier can be formed at the contact interface, respectively, thereby forming a heterojunction (as shown in fig. 1), wherein a large number of electrons can be present in the heterojunction potential well formed at the interface of the two semiconductors. Semiconductor heterojunctions are considered as an effective means for obtaining higher performance semiconductor devices, such as transistors with high mobility and high stability, diodes with high withstand voltage, and the like.
In the existing metal oxide semiconductor heterojunction process, due to the amorphous property of the metal oxide semiconductor and the high-temperature process (such as annealing and the like) commonly used in the preparation of devices, element diffusion easily occurs between two or even multiple metal oxides. This results in the difficulty in forming an ideal semiconductor heterojunction, and the inability to actually utilize and exploit the performance advantages of a heterojunction in a metal oxide semiconductor device. Therefore, the performance of the existing transistor with high mobility and high stability or the existing diode with high voltage resistance and the like needs to be further improved.
Disclosure of Invention
The invention mainly solves the technical problem of providing a heterojunction structure, a semiconductor device structure and a manufacturing method thereof, so that the performance advantage of the heterojunction in a metal oxide semiconductor device is better exerted, and the device performance is further improved.
According to a first aspect, there is provided in one embodiment a heterojunction structure for a semiconductor device, comprising: a heterostructure layer located over the substrate and the substrate;
the heterostructure layer comprises at least two active layers and an intermediate structure layer positioned between the two adjacent active layers, wherein the adjacent active layers have different band gaps so that a heterojunction is formed between the two adjacent active layers, the intermediate structure layer is used for blocking diffusion of metal and oxygen elements, and the thickness and the energy band structure of the intermediate structure layer allow carriers to pass through and be transmitted between the first active layer and the second active layer.
Optionally, the intermediate structural layer is: aluminum oxide, hafnium oxide, tantalum oxide, or titanium oxide.
Optionally, the active layer is IGZO, IZO, ZTO, ITZO, AZO, ZnO, GaO, or InO.
Optionally, the thickness of the intermediate structure layer is 0 to 5 nm.
According to a second aspect, an embodiment provides a heterojunction semiconductor device structure comprising:
a substrate;
the heterostructure layer is any one of the heterojunction structures and is positioned on part of the upper surface of the substrate;
the grid insulating layer is positioned on part of the upper surface of the heterostructure layer;
a gate electrode layer over the gate insulating layer;
a passivation layer covering the gate electrode layer and the gate insulating layer;
and the bottom of the source drain electrode layer is in contact with the heterostructure layer and is positioned at two ends of the gate electrode layer, wherein the passivation layer separates the source drain electrode layer from the gate electrode layer.
According to a third aspect, an embodiment provides a heterojunction semiconductor device structure comprising:
a substrate;
a gate electrode layer on an upper surface of the substrate portion;
the gate insulating layer is positioned on the upper surface of the substrate and covers the gate electrode layer;
the heterostructure layer is any one of the heterojunction structures and is positioned on part of the upper surface of the gate insulating layer;
and the source drain electrode layers are distributed at two ends of the gate electrode layer, and the bottoms of the source drain electrode layers are simultaneously contacted with the heterostructure layer and the gate insulating layer.
According to a fourth aspect, an embodiment provides a heterojunction semiconductor device structure comprising:
a substrate;
a gate electrode layer on an upper surface of the substrate portion;
a gate insulating layer on the upper surface of the substrate and covering the gate electrode layer;
the heterostructure layer is any one of the heterojunction structures and is positioned on part of the upper surface of the gate insulating layer;
the etching barrier layer is positioned on the partial upper surface of the heterostructure layer;
and the source drain electrode layers are distributed at two ends of the gate electrode layer, and the bottoms of the source drain electrode layers and the gate electrode layers are simultaneously contacted with the etching barrier layer, the heterostructure layer and the gate insulating layer.
According to a fifth aspect, an embodiment provides a heterojunction semiconductor device structure, comprising:
a substrate;
the bottom electrode is positioned on the upper surface of the substrate;
the heterostructure layer is positioned on the surface of part of the upper part of the bottom electrode and is any one of the heterostructure layers;
a top electrode on a portion of the surface above the heterostructure layer;
and the passivation layers are distributed at two ends of the top electrode, and the bottom of each passivation layer is simultaneously contacted with the heterostructure layer and the bottom electrode.
According to a sixth aspect, an embodiment provides a heterojunction semiconductor device structure comprising:
a substrate;
the heterostructure layer is any one of the above heterojunction structures and is positioned on part of the upper surface of the substrate;
a gate electrode layer located on a part of the surface above the heterostructure layer;
a passivation layer covering the gate electrode layer;
and the bottom of the source drain electrode layer is in contact with the heterostructure layer and is distributed at two ends of the gate electrode layer, wherein the passivation layer separates the source drain electrode layer from the gate electrode layer.
According to a seventh aspect, there is provided in one embodiment a method of fabricating a heterojunction semiconductor device structure, comprising:
forming a first active layer on a substrate;
forming an intermediate structure layer on an upper surface of the first active layer;
forming a second active layer on an upper surface of the intermediate structure layer, the second active layer and the first active layer having different band gaps such that a heterojunction is formed between the first active layer and the second active layer; the intermediate structure layer can block diffusion of metal and oxygen elements, has a preset thickness, and allows carriers to pass through and to be transmitted between the first active layer and the second active layer due to the thickness and the energy band structure of the intermediate structure layer.
According to the heterojunction structure, the semiconductor device structure and the manufacturing method thereof of the embodiment, in the method, the intermediate structure layer material is formed between the two semiconductor active layers, on one hand, the intermediate structure layer material can block the diffusion of metal elements between the two semiconductor active layers, on the other hand, the energy band of the intermediate structure layer material has a lower barrier for electrons, so that the electrons can freely migrate or largely tunnel between the two semiconductor active layers, and therefore, a more ideal heterojunction interface can be formed between the first active layer and the second active layer, and a deeper heterojunction potential well is obtained. And a more ideal semiconductor heterojunction is formed, so that the performance advantage of the heterojunction in the metal oxide semiconductor device is truly utilized and exerted. The performance of the existing transistor with high mobility and high stability or the performance of the existing diode with high voltage resistance and the like is improved.
Drawings
Figure 1 is a prior art semiconductor heterojunction energy band diagram;
fig. 2 is a semiconductor heterojunction energy band diagram provided in the present embodiment;
FIG. 3 is a schematic structural diagram of a top-gate self-aligned thin film transistor with a heterojunction structure according to the present embodiment;
fig. 4 is a schematic structural diagram of a bottom gate back channel etched thin film transistor to which the heterojunction structure provided in this embodiment is applied;
fig. 5 is a schematic structural diagram of the heterojunction structure applied to the bottom-gate etched barrier thin film transistor provided in this embodiment;
fig. 6 is a schematic structural diagram of a schottky diode applying the heterojunction structure provided in this embodiment;
fig. 7 is a schematic structural diagram of the application of the heterojunction structure provided in this embodiment to a schottky gate transistor.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
As known from the background art, in the existing metal oxide semiconductor heterojunction process, due to the amorphous property of the metal oxide semiconductor and the high temperature process (such as annealing) commonly used in device preparation, element diffusion easily occurs between two or even multiple metal oxides, so that an ideal semiconductor heterojunction is difficult to form, and the performance advantage of the heterojunction in the metal oxide semiconductor device cannot be truly utilized and exerted.
In an embodiment of the present invention, in conjunction with fig. 2, an intermediate structure layer 30 material, such as aluminum oxide, hafnium oxide, tantalum oxide, etc., may be interposed between the two semiconductor active layers. Since the intermediate structure layer 30 can block diffusion of a metal element between two semiconductor active layers, for example, the first active layer 10 and the second active layer 20 are made of two semiconductor materials with different energy bands, electrons can freely migrate or tunnel a large amount between the two semiconductors due to the lower energy band barrier of the intermediate structure layer 30 to electrons, so that a more ideal heterojunction interface can be formed between the first active layer 10 and the second active layer 20, and a deeper heterojunction potential well can be obtained.
The heterojunction structure for a semiconductor device provided in the present embodiment includes: and the heterostructure layer is positioned above the substrate and the substrate. The heterostructure layer comprises at least two active layers and an intermediate structure layer positioned between the two adjacent active layers, wherein the adjacent active layers have different band gaps so that a heterojunction is formed between the two adjacent active layers, the intermediate structure layer can block the diffusion of metal and oxygen elements, and the thickness and the energy band structure of the intermediate structure layer allow carriers to pass through and be transmitted between the first active layer and the second active layer.
The material of the intermediate structure layer in this embodiment may be aluminum oxide, hafnium oxide, tantalum oxide, or titanium oxide. The thickness of the intermediate structure layer is preferably not more than 5nm, and while it is effective, the thickness of the intermediate structure layer is preferably as thin as possible, and may be, for example, about 1nm, 2nm, 3nm, 4nm, or 5 nm.
The material of the active layer may be IGZO, IZO, ZTO, ITZO, AZO, ZnO, GaO, or InO. Two or more active layers can be selected from different active layer materials according to requirements, and the intermediate structure layer can be applied to a semiconductor heterojunction with two layers, three layers or more.
Referring to fig. 3, the present embodiment provides a heterojunction semiconductor device structure, which can be specifically applied to a top-gate self-aligned thin film transistor, and the structure includes: a substrate 100, a heterostructure layer, a gate insulating layer 104, a gate electrode layer 105, a passivation layer 106, and a source drain electrode layer 106.
The substrate 100 may be made of silicon, glass, or other flexible materials, such as PI and PET.
The heterostructure layer includes a semiconductor heterojunction having two, three or more layers of at least two active layers. For example, a double-layer semiconductor heterojunction structure, comprising a first active layer 101, a second active layer 102 and an intermediate structure layer 103 disposed between the two active layers, is located on a portion of the upper surface of the substrate.
The gate insulating layer 104 is located on a portion of the surface above the heterostructure layer.
The gate electrode layer 105 is located over the gate insulating layer 104.
The passivation layer 106 covers the gate electrode layer 105 and the gate insulating layer 104.
The bottom of the source drain electrode layer 107 contacts the heterostructure layer and is located at both ends of the gate electrode layer 105, wherein the passivation layer 106 separates the source drain electrode layer 107 from the gate electrode layer 105.
Referring to fig. 4, the present embodiment provides a heterojunction semiconductor device structure, which may be specifically applied in a bottom gate back channel etched thin film transistor, and the structure includes: a substrate 200, a gate electrode layer 202, a gate insulating layer 201, a heterostructure layer, and a source-drain electrode layer 206.
The substrate 200 may be made of silicon, glass, or other flexible materials, such as PI and PET.
The gate electrode layer 202 is metal over a portion of the surface above the substrate.
A gate insulating layer 201 is located on the upper surface of the substrate 200 and covers the gate electrode layer 202.
The heterostructure layer is located on a portion of the upper surface of the gate insulating layer 201 and includes a double-layered, triple-layered or multi-layered semiconductor heterojunction composed of at least two active layers. For example, a double-layer semiconductor heterojunction structure is shown, which comprises a first active layer 203, a second active layer 205 and an intermediate structure layer 204 arranged between the two active layers.
Source and drain electrode layers 206 are distributed on both sides of the gate electrode layer 202, and the bottom portion contacts the heterostructure layer and the gate insulating layer at the same time.
Referring to fig. 5, the present embodiment provides a heterojunction semiconductor device structure, which can be specifically applied to a bottom gate etched barrier thin film transistor, and the structure includes: a substrate 300, a gate electrode layer 302, a gate insulating layer 301, a heterostructure layer, an etch stop layer 306, and a source-drain electrode layer 307. The substrate 300 may be made of silicon, glass, or other flexible materials, such as PI and PET.
A gate electrode layer 302 is located over a portion of the upper surface of the substrate 300 and is metal.
A gate insulating layer 301 is on the upper surface of the substrate 300 and covers the gate electrode layer 302.
The heterostructure layer is located on a portion of the upper surface of the gate insulating layer 301 and includes a double-layered, triple-layered or multi-layered semiconductor heterojunction composed of at least two active layers. For example, a double-layer semiconductor heterojunction structure is shown, comprising a first active layer 303, a second active layer 305 and an intermediate structure layer 304 arranged between the two active layers.
The etch stop layer 306 is a metal oxide and is located on a portion of the upper surface of the heterostructure layer.
The source drain electrode layer 307 is distributed at both ends of the gate electrode layer 302, and the bottom of the source drain electrode layer 307 simultaneously contacts the etch stopper 306, the heterostructure layer, and the gate insulating layer 301.
Referring to fig. 6, the present embodiment provides a heterojunction semiconductor device structure, which can be specifically applied to a schottky diode, and includes a substrate 400, a bottom electrode 401, a heterostructure layer, a top electrode 405, and a passivation layer 406.
The substrate 400 may be made of silicon, glass, or other flexible materials, such as PI and PET.
The bottom electrode 401 is made of metal and is located on the upper surface of the substrate 400.
The heterostructure layer is located on a portion of the surface above the bottom electrode 400 and includes a bi-layer, tri-layer or more semiconductor heterojunction formed by at least two active layers. For example, a double-layer semiconductor heterojunction structure is shown, which comprises a first active layer 402, a second active layer 404 and an intermediate structure layer 403 arranged between the two active layers.
The top electrode 405 is a metal and is located on a portion of the surface above the heterostructure layer.
The passivation layer 406 is distributed at both ends of the top electrode 405, and the bottom of the passivation layer 406 contacts both the heterostructure layer and the bottom electrode 401.
Referring to fig. 7, the present embodiment provides a heterojunction semiconductor device structure, which may be specifically applied to a schottky gate transistor, and the structure includes: a substrate 500, a heterostructure layer, a gate electrode layer 504, a passivation layer 505, and a source drain electrode layer 506.
The substrate 500 may be made of silicon, glass, or other flexible materials, such as PI and PET.
The heterostructure layer is located on a portion of the upper surface of the substrate 500 and includes a bi-layer, tri-layer or more semiconductor heterojunction formed by at least two active layers. For example, a double-layer semiconductor heterojunction structure is shown, which comprises a first active layer 502, a second active layer 503, and an intermediate structure layer 502 disposed between the two active layers.
The gate electrode layer 504 is a metal, which acts as a schottky top gate electrode, on a portion of the surface above the heterostructure layer. A passivation layer 505 covers the gate electrode layer 504.
Source and drain electrode layers 506 are located at both ends of the gate electrode layer 504, the bottom of the source and drain electrode layers 506 contacts the heterostructure layer, and the passivation layer 505 separates the source and drain electrode layers 506 from the gate electrode layer 504. The present embodiment also provides a method of fabricating a heterojunction semiconductor device structure, comprising:
step 1, forming a first active layer on a substrate.
And 2, forming an intermediate structure layer on the upper surface of the first active layer.
The intermediate structure layer may be prepared by direct sputtering, reactive sputtering, ALD growth, or post-treatment (e.g., oxidation) of elemental materials.
Step 3, forming a second active layer on the upper surface of the intermediate structure layer, wherein the second active layer and the first active layer have different band gaps so that a heterojunction is formed between the first active layer and the second active layer; the intermediate structure layer can block diffusion of metal and oxygen elements, has a preset thickness, and has a thickness and an energy band structure allowing carriers to pass through and be transmitted between the first active layer and the second active layer.
When three or more semiconductor heterojunctions are formed, an intermediate structure layer may be formed between two active layers by direct sputtering, reactive sputtering, ALD growth, or post-treatment (such as oxidation) of a simple substance material, and the material of the intermediate structure layer may be aluminum oxide, hafnium oxide, tantalum oxide, or titanium oxide.
By forming an intermediate structure layer material such as aluminum oxide, hafnium oxide, tantalum oxide and the like between the two semiconductor active layers, on one hand, diffusion of metal elements between the two semiconductor active layers is blocked, and on the other hand, an energy band of the intermediate structure layer material has a lower potential barrier for electrons, so that electrons can freely migrate or largely tunnel through between the two semiconductor active layers, an ideal heterojunction interface can be formed between the first active layer and the second active layer, and a deeper heterojunction potential well is obtained. And a more ideal semiconductor heterojunction is formed, so that the performance advantage of the heterojunction in the metal oxide semiconductor device is truly utilized and exerted. The performance of the existing transistor with high mobility and high stability or the performance of the existing diode with high voltage resistance and the like is improved.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims (10)

1. A heterojunction structure for a semiconductor device, comprising: a heterostructure layer located over the substrate and the substrate;
the heterostructure layer comprises at least two active layers and an intermediate structure layer positioned between the two adjacent active layers, wherein the adjacent active layers have different band gaps so that a heterojunction is formed between the two adjacent active layers, the intermediate structure layer is used for blocking diffusion of metal and oxygen elements, and the thickness and the energy band structure of the intermediate structure layer allow carriers to pass through and be transmitted between the first active layer and the second active layer.
2. The heterojunction structure of claim 1, wherein said intermediate structural layer is: aluminum oxide, hafnium oxide, tantalum oxide, or titanium oxide.
3. The heterojunction structure of claim 1, wherein said active layer is IGZO, IZO, ZTO, ITZO, AZO, ZnO, GaO, or InO.
4. The heterojunction structure of claim 1, wherein said intermediate structural layer has a thickness of 0-5 nm.
5. A heterojunction semiconductor device structure, comprising:
a substrate;
a heterostructure layer, the heterostructure layer being the structure of any of claims 1 to 4, on a portion of the upper surface of the substrate;
the grid insulating layer is positioned on part of the upper surface of the heterostructure layer;
a gate electrode layer over the gate insulating layer;
a passivation layer covering the gate electrode layer and the gate insulating layer;
and the bottom of the source drain electrode layer is in contact with the heterostructure layer and is positioned at two ends of the gate electrode layer, wherein the passivation layer separates the source drain electrode layer from the gate electrode layer.
6. A heterojunction semiconductor device structure, comprising:
a substrate;
a gate electrode layer on an upper surface of the substrate portion;
the gate insulating layer is positioned on the upper surface of the substrate and covers the gate electrode layer;
a heterostructure layer, which is the structure of any one of claims 1 to 4 and is located on a part of the upper surface of the gate insulating layer;
and the source drain electrode layers are distributed at two ends of the gate electrode layer, and the bottoms of the source drain electrode layers are simultaneously contacted with the heterostructure layer and the gate insulating layer.
7. A heterojunction semiconductor device structure, comprising:
a substrate;
a gate electrode layer on an upper surface of the substrate portion;
the gate insulating layer is positioned on the upper surface of the substrate and covers the gate electrode layer;
a heterostructure layer, which is the structure of any one of claims 1 to 4 and is located on a part of the upper surface of the gate insulating layer;
the etching barrier layer is positioned on the partial upper surface of the heterostructure layer;
and the source drain electrode layers are distributed at two ends of the gate electrode layer, and the bottoms of the source drain electrode layers and the gate electrode layers are simultaneously contacted with the etching barrier layer, the heterostructure layer and the gate insulating layer.
8. A heterojunction semiconductor device structure, comprising:
a substrate;
a bottom electrode on the upper surface of the substrate;
a heterostructure layer on a portion of a surface above the bottom electrode, the heterostructure layer being as claimed in any of claims 1 to 4;
a top electrode on a portion of the surface above the heterostructure layer;
and the passivation layers are distributed at two ends of the top electrode, and the bottom of each passivation layer is simultaneously contacted with the heterostructure layer and the bottom electrode.
9. A heterojunction semiconductor device structure, comprising:
a substrate;
a heterostructure layer, the heterostructure layer being the structure of any of claims 1 to 4, on a portion of the upper surface of the substrate;
a gate electrode layer located on a part of the surface above the heterostructure layer;
a passivation layer covering the gate electrode layer;
and the bottom of the source drain electrode layer is in contact with the heterostructure layer and is distributed at two ends of the gate electrode layer, wherein the passivation layer separates the source drain electrode layer from the gate electrode layer.
10. A method of fabricating a heterojunction semiconductor device structure, comprising:
forming a first active layer on a substrate;
forming an intermediate structure layer on an upper surface of the first active layer;
forming a second active layer on an upper surface of the intermediate structure layer, the second active layer and the first active layer having different band gaps such that a heterojunction is formed between the first active layer and the second active layer; the intermediate structure layer can block diffusion of metal and oxygen elements, has a preset thickness, and allows carriers to pass through and to be transmitted between the first active layer and the second active layer due to the thickness and the energy band structure of the intermediate structure layer.
CN202210411896.7A 2022-04-19 2022-04-19 Heterojunction structure, semiconductor device structure and manufacturing method thereof Pending CN114899224A (en)

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