CN114899211A - Display substrate and display device - Google Patents

Abstract

A display substrate and a display device are provided. The sub-pixels in the display substrate comprise light-emitting elements and pixel circuits, the light-emitting elements comprise first electrodes, light-emitting layers and second electrodes, the pixel circuits comprise driving transistors and storage capacitors, and the grid electrodes of the driving transistors are multiplexed into one polar plate of the storage capacitors. The sub-pixels comprise a first color sub-pixel pair comprising a first pixel block and a second pixel block. In the same first color sub-pixel pair, the overlapping condition of the orthographic projections of the second electrode of the light-emitting element of the first pixel block and the gate of the driving transistor of the first pixel block on the substrate is the same as the overlapping condition of the orthographic projections of the second electrode of the light-emitting element of the second pixel block and the gate of the driving transistor of the second pixel block on the substrate, so that the gate nodes of the driving transistors in the two first color sub-pixels have balanced coverage, and the balance between the electrical environment and the light-emitting effect of the two first color sub-pixels is facilitated.

Description

Display substrate and display device

The present application is a divisional chinese patent application entitled "display substrate and display device" at 202080001419.2, which was filed on the chinese country stage at 8/3/2020, the PCT application No. 202080001419.2 is a patent application No. PCT/CN2020/106413, which was filed on 31/7/2020, the PCT application No. PCT/CN2020/106413 claims priority of PCT application No. PCT/CN2019/098708, which was filed on 31/7/2019, and priority of PCT application No. PCT/CN2019/098731, which was filed on 31/7/2019, and the disclosure of the above-mentioned PCT applications is incorporated herein in its entirety as a part of the present application for all purposes.

Technical Field

At least one embodiment of the present disclosure relates to a display substrate and a display device.

Background

With the development of organic light emitting diode display technologies, such as Active Matrix Organic Light Emitting Diode (AMOLED) display technologies, people have higher and higher requirements on display effects, and the design of pixel circuits in display products is crucial to the display characteristics of AMOLED products. At present, how to improve the display characteristics of the organic light emitting display device becomes a key point in the research and development of the organic light emitting display device.

Disclosure of Invention

At least one embodiment of the present disclosure provides a display substrate and a display device.

At least one embodiment of the present disclosure provides a display substrate, including: the liquid crystal display comprises a substrate base plate and a plurality of sub-pixels located on the substrate base plate. Each sub-pixel comprises a light-emitting element and a pixel circuit, the light-emitting element comprises a first electrode, a light-emitting layer and a second electrode which are sequentially stacked, the second electrode is located between the light-emitting layer and the substrate base plate, the pixel circuit comprises a driving transistor and a storage capacitor, the driving transistor and the storage capacitor are located between the second electrode and the substrate base plate, and a grid electrode of the driving transistor is multiplexed as one polar plate of the storage capacitor. The plurality of sub-pixels comprises at least one first color sub-pixel pair and a plurality of other color sub-pixels, each first color sub-pixel pair comprises a first pixel block and a second pixel block, and the minimum distance between the first pixel block and the second pixel block in each first color sub-pixel pair is not larger than the minimum distance between two same color sub-pixels in the plurality of other color sub-pixels; in the same first color sub-pixel pair, the overlapping condition of the orthographic projection of the second electrode of the light-emitting element of the first pixel block and the gate electrode of the driving transistor of the first pixel block on the substrate is the same as the overlapping condition of the orthographic projection of the second electrode of the light-emitting element of the second pixel block and the gate electrode of the driving transistor of the second pixel block on the substrate.

For example, in an embodiment of the present disclosure, the first pixel block and the second pixel block included in the same first color sub-pixel pair are arranged along a row direction, the other color sub-pixels include a second color sub-pixel and a third color sub-pixel, at least one of the second color sub-pixel and the third color sub-pixel and the first color sub-pixel pair are located in an adjacent row, and the display substrate further includes a planarization layer located between the pixel circuit and the second electrode of the light emitting element. The flat layer comprises a plurality of through holes penetrating through the flat layer, the second electrode of the light-emitting element in each sub-pixel is electrically connected with the corresponding pixel circuit through the through holes, the through holes corresponding to the sub-pixels in the adjacent rows are not located on a straight line, and the orthographic projection of the through hole corresponding to one of the two sub-pixels in the adjacent rows on the straight line extending along the column direction is overlapped with the orthographic projection of the effective light-emitting area of the other sub-pixel in the two sub-pixels on the straight line.

For example, in an embodiment of the present disclosure, the display substrate further includes: a plurality of data lines extending in a first direction; a plurality of power signal lines extending in the first direction. The other color sub-pixels include a plurality of second color sub-pixels and a plurality of third color sub-pixels, and the second electrode of the light emitting element of at least one third color sub-pixel overlaps with the two data lines and the two power signal lines in a direction perpendicular to the substrate.

For example, in the embodiment of the present disclosure, the effective light emitting area of the light emitting element of the at least one third color sub-pixel overlaps the two data lines in a direction perpendicular to the substrate.

For example, in an embodiment of the present disclosure, the display substrate further includes: a plurality of data lines extending in the first direction; a plurality of power signal lines extending in the first direction. The other color sub-pixels include a plurality of second color sub-pixels and a plurality of third color sub-pixels, and the second electrode of the light emitting element of at least one of the second color sub-pixels overlaps the two data lines.

For example, in an embodiment of the present disclosure, the plurality of sub-pixels include a plurality of first color sub-pixel pairs arranged along the second direction, the plurality of first color sub-pixel pairs include a plurality of first pixel blocks and a plurality of second pixel blocks alternately arranged along the second direction, and two distances between the effective light emitting area of the first pixel block and the effective light emitting areas of the two second pixel blocks located on both sides of the effective light emitting area of the first pixel block in the second direction are different; the display substrate further comprises a data line extending along a first direction, and an included angle between the second direction and the first direction is in a range of 80-100 degrees.

For example, in an embodiment of the present disclosure, the other color sub-pixels further include a plurality of second color sub-pixels and a plurality of third color sub-pixels, the pixel circuits of the plurality of sub-pixels include pixel circuit rows arranged in a column direction, each pixel circuit row includes pixel circuits arranged in a row direction, and centers of effective light emitting areas of a part of the second color sub-pixels and a part of the third color sub-pixels connected to the pixel circuits in the same pixel circuit row are not on a straight line.

For example, in an embodiment of the present disclosure, the pixel circuit further includes a threshold compensation transistor, a first pole of the threshold compensation transistor is electrically connected to the first pole of the driving transistor, a second pole of the threshold compensation transistor is electrically connected to the gate of the driving transistor, the threshold compensation transistor includes a first gate and a second gate, and the second electrode of the light emitting element of the first pixel block shields one of the first gate and the second gate.

For example, in an embodiment of the present disclosure, the other color sub-pixels include a plurality of second color sub-pixels and a plurality of third color sub-pixels, the second electrode of the light emitting element of the third color sub-pixel includes a body electrode and a connection electrode, the connection electrode is configured to be electrically connected to the pixel circuit, an effective light emitting area of the third color sub-pixel overlaps the body electrode in a direction perpendicular to the substrate, and the body electrode of the third color sub-pixel overlaps at least one of the first gate electrode and the second gate electrode.

For example, in an embodiment of the present disclosure, the second electrode of the light emitting element of at least one color sub-pixel includes a body electrode and a connection electrode configured to be electrically connected to the pixel circuit, and an effective light emitting area of the at least one color sub-pixel overlaps with the body electrode in a direction perpendicular to the substrate; the second electrode of the light emitting element of the at least one color sub-pixel further comprises an auxiliary electrode covering a portion of the active layer between orthographic projections of the first and second gate electrodes on the active layer.

For example, in an embodiment of the present disclosure, the pixel circuit further includes a threshold compensation transistor, a first emission control transistor, a first connection portion, and a second connection portion between the second electrode of the light emitting element and the substrate, a first pole of the threshold compensation transistor being electrically connected to the first pole of the driving transistor, a second pole of the threshold compensation transistor being electrically connected to the gate of the driving transistor through the first connection portion, a first pole of the first emission control transistor being electrically connected to the first pole of the driving transistor, a second pole of the first emission control transistor being electrically connected to the second electrode of the light emitting element through the second connection portion; the pixel circuits of the sub-pixels comprise pixel circuit rows arranged along the column direction, each pixel circuit row comprises a plurality of pixel circuits arranged along the row direction, and two adjacent second connecting parts in the same pixel circuit row are different in shape and size.

For example, in an embodiment of the present disclosure, the display substrate further includes: and the light-emitting control signal line extends along the row direction and is arranged at the same layer as the grid electrode of the driving transistor. The second connection portion overlaps the light emission control signal line and does not overlap the gate electrode of the driving transistor.

For example, in an embodiment of the present disclosure, in the first color sub-pixel pair, the second electrode of each light emitting element includes a body electrode and a connection electrode configured to be electrically connected to the pixel circuit, in a direction perpendicular to the substrate, the effective light emitting area in the first pixel block overlaps the body electrode, and the effective light emitting area in the second pixel block overlaps the body electrode; the first pixel block and the second pixel block have different shapes and sizes of the second electrodes of the light emitting elements except for the main body electrode.

For example, in the embodiment of the present disclosure, the second electrodes of the light emitting elements of the first and second pixel blocks are different in shape and size except for the body electrode and the connection electrode.

The embodiment of the disclosure provides a display substrate, which comprises a substrate and a plurality of sub-pixels positioned on the substrate. Each sub-pixel comprises a light-emitting element and a pixel circuit, wherein the light-emitting element comprises a first electrode, a light-emitting layer and a second electrode which are sequentially stacked, the second electrode is positioned between the light-emitting layer and the substrate, the pixel circuit comprises a first connecting part, a driving transistor and a threshold compensation transistor, the first connecting part is positioned between the second electrode and the substrate, the first connecting part extends along a first direction, a first pole of the threshold compensation transistor is electrically connected with a first pole of the driving transistor, and a second pole of the threshold compensation transistor is electrically connected with a grid electrode of the driving transistor through the first connecting part. The plurality of sub-pixels comprise at least one first color sub-pixel pair and a plurality of other color sub-pixels, each first color sub-pixel pair comprises a first pixel block and a second pixel block which are arranged along a second direction, the minimum distance between the first pixel block and the second pixel block in each first color sub-pixel pair is not larger than the minimum distance between two same color sub-pixels in the plurality of other color sub-pixels, and the included angle between the second direction and the first direction is within the range of 80-100 degrees; in the first pixel block, an overlapping area of an orthographic projection of the second electrode on the substrate base plate and an orthographic projection of the first connecting portion on the substrate base plate is a first overlapping area, in the second pixel block, an overlapping area of an orthographic projection of the second electrode on the substrate base plate and an orthographic projection of the first connecting portion on the substrate base plate is a second overlapping area, and a ratio of the first overlapping area to the second overlapping area is 0.8-1.2.

For example, in an embodiment of the present disclosure, in the first pixel block, the second electrode of the light emitting element covers 60 to 90% of an area of the first connection portion; in the second pixel block, the second electrode of the light emitting element covers 60-90% of the area of the first connection portion.

For example, in an embodiment of the present disclosure, the first pixel block includes a first effective light emitting region, the second pixel block includes a second effective light emitting region, a minimum distance between an orthogonal projection of the first connection portion on a straight line extending along the second direction and an orthogonal projection of the first effective light emitting region on the straight line is a first distance, or an orthogonal projection of the first connection portion on a straight line extending along the second direction overlaps an orthogonal projection of the first effective light emitting region on the straight line; in the second pixel block, a minimum distance between an orthographic projection of the first connecting part on the straight line and an orthographic projection of the second effective light emitting area on the straight line is a second distance, and the first distance is smaller than the second distance; in the first pixel block, the grid electrode of the threshold compensation transistor is positioned on one side of the first connecting part far away from the first effective luminous area; in the second pixel block, the gate of the threshold compensation transistor is located on one side of the first connection portion close to the second effective light emitting area.

For example, in an embodiment of the present disclosure, the second electrode of each of the sub-pixels includes a main body electrode and a connection electrode, in the first pixel block, the shape of the main body electrode is substantially the same as the shape of the first effective light emitting area, an orthographic projection of the first effective light emitting area on the substrate is located within the orthographic projection of the main body electrode on the substrate, and the first effective light emitting area overlaps the first connection portion; in the second pixel block, the shape of the main body electrode is substantially the same as that of the second effective light emitting area, the orthographic projection of the second effective light emitting area on the substrate is positioned in the orthographic projection of the main body electrode on the substrate, and the second effective light emitting area is not overlapped with the first connecting part.

For example, in an embodiment of the present disclosure, in the first color sub-pixel pair, the second electrode further includes an auxiliary electrode connecting the main body electrode and the connection electrode, the connection electrode extends along the first direction, in the first pixel block, the auxiliary electrode is located on a side of the main body electrode away from the second effective light emitting area, and in the second pixel block, the auxiliary electrode is located on a side of the main body electrode away from the first effective light emitting area.

At least one embodiment of the present disclosure provides a display device including the display substrate.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1 is a schematic view of a partial plan structure of a display substrate according to an embodiment of the disclosure;

FIG. 2 is an equivalent diagram of a pixel circuit of each sub-pixel shown in FIG. 1;

fig. 3A is a schematic view of a partial plan structure of a stacked structure of an active semiconductor layer and a first conductive layer of a partial pixel circuit provided in accordance with an embodiment of the present disclosure;

fig. 3B is a schematic partial plan view of a stacked structure of an active semiconductor layer, a first conductive layer, and a second conductive layer according to an embodiment of the disclosure;

FIG. 3C is a schematic illustration of via locations in various insulator layers provided in accordance with an embodiment of the present disclosure;

fig. 3D is a schematic view of a partial planar structure of a source drain metal layer provided according to an embodiment of the present disclosure;

fig. 3E is a schematic diagram of a stacked structure of an active semiconductor layer, a first conductive layer, a second conductive layer, and a source-drain metal layer provided according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a second electrode and an effective light emitting area of a light emitting element of each sub-pixel provided according to an embodiment of the present disclosure;

fig. 5A is a schematic structural diagram of a light-emitting element and a source-drain metal layer laminated structure of each sub-pixel provided according to the embodiment of the present disclosure;

fig. 5B is a schematic view of a stacked structure of a light emitting element, an active semiconductor layer, a first conductive layer, and a source drain metal layer of each sub-pixel provided according to the embodiment of the present disclosure;

fig. 5C is a schematic view of a stacked structure of a light emitting element and an active semiconductor layer, a first conductive layer, a second conductive layer, and a source drain metal layer of each sub-pixel provided according to the embodiment of the present disclosure;

FIG. 5D is a cross-sectional view taken along line A1A2 shown in FIG. 5C;

FIG. 5E is a cross-sectional view taken along line A3A4 shown in FIG. 5C;

FIG. 5F is a cross-sectional view taken along line A5A6 shown in FIG. 5C;

FIG. 5G is a cross-sectional view taken along line A7A8 shown in FIG. 5C;

FIG. 5H is a cross-sectional view taken along line A9A10 shown in FIG. 5C in an example of an embodiment of the present disclosure;

FIG. 5I is a cross-sectional view taken along line A9A10 shown in FIG. 5C in another example of an embodiment of the present disclosure;

FIG. 5J is a cross-sectional view taken along line A11A12 shown in FIG. 5C;

FIG. 6 is a schematic view of a partial cross-sectional structure of a display substrate;

FIG. 7 is a schematic view of a partial cross-sectional structure of another display substrate; and

fig. 8 is a schematic view of a pixel arrangement structure in a display substrate.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

The terms "parallel," "perpendicular," and "the same" as used in the embodiments of the present disclosure include the strict terms "parallel," "perpendicular," "the same," and the terms "substantially parallel," "substantially perpendicular," "substantially the same," and the like, include certain errors, which are within the acceptable range of deviation for a particular value, as determined by one of ordinary skill in the art, in view of the error associated with measuring a particular value (i.e., the limitations of the measurement system). "center" in embodiments of the present disclosure may include a location strictly at the geometric center and a location approximately at the center within a small area around the geometric center. For example, "substantially" can mean within one or more standard deviations, or within 10% or 5% of the stated value.

In the research, the inventors of the present application found that in the GGRB pixel arrangement structure, each pixel includes a red sub-pixel, a blue sub-pixel, and a green sub-pixel pair, each sub-pixel includes a light emitting element and a pixel circuit for driving the light emitting element to emit light, and when there is a difference in gate node load of a driving transistor included in a pixel circuit of two green sub-pixels included in the green sub-pixel pair, a difference occurs in luminance when two green sub-pixels included in the green sub-pixel pair emit light.

The embodiment of the disclosure provides a display substrate and a display device. The display substrate comprises a substrate base plate and a plurality of sub-pixels positioned on the substrate base plate. Each sub-pixel comprises a light-emitting element and a pixel circuit, the light-emitting element comprises a first electrode, a light-emitting layer and a second electrode which are sequentially stacked, the second electrode is located between the light-emitting layer and a substrate, the pixel circuit comprises a first connecting portion, a driving transistor and a threshold compensation transistor, the first connecting portion is located between the second electrode and the substrate, the first connecting portion extends along a first direction, a first pole of the threshold compensation transistor is electrically connected with a first pole of the driving transistor, and a second pole of the threshold compensation transistor is electrically connected with a grid electrode of the driving transistor through the first connecting portion. The plurality of sub-pixels comprise at least one first color sub-pixel pair and a plurality of other color sub-pixels, each first color sub-pixel pair comprises a first pixel block and a second pixel block which are arranged along a second direction, the minimum distance between the first pixel block and the second pixel block in each first color sub-pixel pair is not more than the minimum distance between two same color sub-pixels in the plurality of other color sub-pixels, and the included angle between the second direction and the first direction is within the range of 80-100 degrees; the first pixel block comprises a first effective light emitting area, the second pixel block comprises a second effective light emitting area, and in the first pixel block, the minimum distance between the orthographic projection of the first connecting part on a straight line extending along the second direction and the orthographic projection of the first effective light emitting area on the straight line is a first distance, or the orthographic projection of the first connecting part on the straight line extending along the second direction and the orthographic projection of the first effective light emitting area on the straight line are overlapped; in the second pixel block, the minimum distance between the orthographic projection of the first connecting part on the straight line and the orthographic projection of the second effective light emitting area on the straight line is a second distance, and the first distance is smaller than the second distance; in the first pixel block, the overlapping area of the orthographic projection of the second electrode on the substrate base plate and the orthographic projection of the first connecting part on the substrate base plate is a first overlapping area, in the second pixel block, the overlapping area of the orthographic projection of the second electrode on the substrate base plate and the orthographic projection of the first connecting part on the substrate base plate is a second overlapping area, and the ratio of the first overlapping area to the second overlapping area is 0.8-1.2. In the embodiment of the disclosure, in the two first color sub-pixels included in the first color sub-pixel pair, the ratio of the overlapping areas of the second electrodes of the two light emitting elements and the corresponding two first connecting portions is 0.8 to 1.2, which can reduce the load difference of the gate nodes of the driving transistors in the two first color sub-pixels, thereby reducing the luminance difference of the two first color sub-pixels to improve the display characteristics of the display substrate.

The embodiment of the present disclosure further provides a display substrate, including: the liquid crystal display comprises a substrate base plate and a plurality of sub-pixels located on the substrate base plate. Each sub-pixel comprises a light-emitting element and a pixel circuit, the light-emitting element comprises a first electrode, a light-emitting layer and a second electrode which are sequentially stacked, the second electrode is located between the light-emitting layer and the substrate base plate, the pixel circuit comprises a driving transistor and a storage capacitor, the driving transistor and the storage capacitor are located between the second electrode and the substrate base plate, and a grid electrode of the driving transistor is multiplexed as one polar plate of the storage capacitor. The plurality of sub-pixels comprises at least one first color sub-pixel pair and a plurality of other color sub-pixels, each first color sub-pixel pair comprises a first pixel block and a second pixel block, and the minimum distance between the first pixel block and the second pixel block in each first color sub-pixel pair is not larger than the minimum distance between two same color sub-pixels in the plurality of other color sub-pixels; in the same first color sub-pixel pair, the overlapping condition of the orthographic projections of the second electrode of the light-emitting element of the first pixel block and the gate of the driving transistor of the first pixel block on the substrate is the same as the overlapping condition of the orthographic projections of the second electrode of the light-emitting element of the second pixel block and the gate of the driving transistor of the second pixel block on the substrate, so that the gate nodes of the driving transistors in the two first color sub-pixels have balanced coverage, and the balance between the electrical environment and the light-emitting effect of the two first color sub-pixels is facilitated.

The display substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the drawings.

Fig. 1 is a schematic view of a partial planar structure of a display substrate according to an embodiment of the disclosure. As shown in fig. 1, the display substrate includes a substrate 1 and a plurality of sub-pixels 10 on the substrate 1. For example, as shown in fig. 1, a plurality of sub-pixels 10 are arranged as a plurality of repeating units 20. Each of the repeating units 20 includes one second-color sub-pixel 200, one first-color sub-pixel pair 100, and one third-color sub-pixel 300 arranged in a first direction (X direction shown in the drawing), and the two first- color sub-pixels 110 and 120 included in the first-color sub-pixel pair 100 are arranged in a second direction (Y direction shown in the drawing, a direction different from the first direction). The plurality of repeating units 20 are arranged in the first direction to form a plurality of repeating unit groups, the plurality of repeating unit groups are arranged in the second direction, and adjacent repeating unit groups of the plurality of repeating unit groups are staggered from each other in the first direction, that is, adjacent repeating unit groups have a certain offset in the first direction. Therefore, the same color sub-pixels in adjacent repeating unit groups are not aligned in the second direction. The pixel arrangement modes in the odd-numbered row repeating unit groups are the same, and the pixel arrangement modes in the even-numbered row repeating unit groups are the same.

For example, the amount of offset in the first direction of adjacent repeating unit groups is approximately half the size of the repeating unit 20 in the first direction. For example, the dimension of the repeating unit 20 in the first direction is the pitch of the repeating unit 20 in the first direction. The pitch here refers to a distance between centers of effective light emitting areas of two second color sub-pixels 200 in two adjacent repeating units 20 in the first direction, where the center of an effective light emitting area refers to a geometric center of a planar shape of the effective light emitting area.

For example, the second direction and the first direction are two directions in the same plane, and an included angle between the two directions is in a range of 80 ° to 100 °. For example, the plane is a plane in which pixels are arranged. The repeating unit herein refers to only the repetition of the sub-pixels, and other structures may be different or the same. The repetition of the above description means that the approximate position, shape, and size are almost the same. In some cases, the shapes are slightly different, such as having openings at different locations, for routing or opening needs.

For example, as shown in fig. 1, the effective light emitting area 201 of the second color sub-pixel 200 is shaped as a long bar extending along the second direction. For example, the shape of the effective light emitting region 301 of the third color sub-pixel 300 is a long stripe extending along the second direction. For example, the display substrate further includes a data line 420 on the substrate 1, the data line 420 extending in a first direction. Therefore, the included angle between the extending direction of the effective light emitting area of the second color sub-pixel and the extending direction of the data line is in the range of 80 degrees to 100 degrees. When the extending direction of the opening of a fine metal mask plate (FMM) for evaporating each color sub-pixel is in an included angle of 80-100 degrees, for example 90 degrees, with the extending direction of the data line, the extending direction of the effective light emitting area of the second color sub-pixel is the same as the extending direction of the FMM opening.

For example, as shown in fig. 1, the shapes of the effective light emitting areas 201 and 301 of the second color sub-pixel 200 and the third color sub-pixel 300 include a hexagon or an ellipse. Furthermore, although the shapes of the second color sub-pixel and the third color sub-pixel in the figure include strict corners formed by two line segments, in some embodiments, the shapes of the effective light emitting areas of the second color sub-pixel and the third color sub-pixel may be both rounded corner patterns, such as an ellipse. That is, on the basis of the above-described hexagonal shape, the corners of the effective light emitting areas of the second color sub-pixel and the third color sub-pixel are rounded. For example, when the opening of the pixel defining layer is formed, the corner portion of the opening is rounded, so that the effective light emitting region is formed in a rounded shape. The hexagons in the disclosed embodiments may include standard hexagons or approximate hexagons, e.g., rounded hexagons or the like having a generally hexagonal shape with a hexagonal profile.

For example, the disclosed embodiment schematically shows that the first color sub-pixel pair 100 is a green sub-pixel pair, the second color sub-pixel 200 is a red sub-pixel, and the third color sub-pixel 300 is a blue sub-pixel. But not limited thereto, the names of the respective color sub-pixels may be interchanged. In the embodiment of the present disclosure, a sub-pixel pair including two sub-pixels with the same color is a green sub-pixel pair; along the extending direction of the data line, the width of the effective light emitting area of the red sub-pixel is smaller than that of the effective light emitting area of the blue sub-pixel; the length of the effective light-emitting area of the red sub-pixel is greater than that of the blue sub-pixel.

For example, fig. 2 is an equivalent diagram of a pixel circuit of each sub-pixel shown in fig. 1. As shown in fig. 2, each sub-pixel 10 includes a light-emitting element 11 and a pixel circuit 12 for driving the light-emitting element 11 to emit light, and the light-emitting element 11 includes a first electrode, a light-emitting layer, and a second electrode which are stacked in this order, and the second electrode is located between the light-emitting layer and the base substrate. For example, fig. 5E schematically shows a light-emitting element including a first electrode 310, a light-emitting layer 330, and a second electrode 320, the second electrode 320 being located between the light-emitting layer 330 and the base substrate 1. For example, the display substrate further includes a reset power supply signal line, a scan signal line, a power supply signal line, a reset control signal line, and a light emission control signal line on the substrate 1. For example, in the embodiments of the present disclosure, the names of the first electrode and the second electrode may be interchanged.

For example, as shown in fig. 2, each pixel circuit 12 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. A first pole of the threshold compensation transistor T2 is connected to the first pole of the driving transistor T3, and a second pole of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3; a first pole of the first reset control transistor T7 is connected to the reset power signal line to receive the reset signal Vinit, and a second pole of the first reset control transistor T7 is connected to the light emitting unit; a first pole of the data write transistor T4 is connected to a second pole of the driving transistor T3. For example, as shown in fig. 2, the pixel circuit of each sub-pixel further includes a storage capacitor C, a first light emission control transistor T6, a second light emission control transistor T5, and a second reset transistor T1. The Gate of the data writing transistor T4 is electrically connected to the scanning signal line to receive the scanning signal Gate; a first pole of the storage capacitor C is electrically connected to the power signal line, and a second pole of the storage capacitor C is electrically connected to the gate of the driving transistor T3; the gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive a compensation control signal; the gate of the first Reset transistor T7 is electrically connected with the Reset control signal line to receive a Reset control signal Reset (N + 1); a first pole of the second reset transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit, a second pole of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive the reset control signal reset (n); the gate of the first light emission controlling transistor T6 is electrically connected to the light emission control signal line to receive the light emission control signal EM; a first electrode of the second light emission controlling transistor T5 is electrically connected to the power signal line to receive the first power signal VDD, a second electrode of the second light emission controlling transistor T5 is electrically connected to the second electrode of the driving transistor T3, a gate electrode of the second light emission controlling transistor T5 is electrically connected to the light emission control signal line to receive the light emission control signal EM, and a first electrode of the light emitting element 11 is connected to the voltage terminal VSS. The power supply signal line refers to a signal line that outputs a voltage signal VDD, and may be connected to a voltage source to output a constant voltage signal, for example, a positive voltage signal.

For example, the scan signal and the compensation control signal may be the same, i.e., the gate of the data write transistor T3 and the gate of the threshold compensation transistor T2 may be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gate of the data writing transistor T3 and the gate of the threshold compensating transistor T2 may also be electrically connected to different signal lines, respectively, i.e., the gate of the data writing transistor T3 is electrically connected to the first scanning signal line, and the gate of the threshold compensating transistor T2 is electrically connected to the second scanning signal line, and the signals transmitted by the first scanning signal line and the second scanning signal line may be the same or different, so that the gate of the data writing transistor T3 and the threshold compensating transistor T2 may be separately and independently controlled, increasing the flexibility of controlling the pixel circuit.

For example, the light emission control signals inputted to the first and second light emission control transistors T6 and T5 may be the same, i.e., the gates of the first and second light emission control transistors T6 and T5 may be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 may be electrically connected to different light-emitting control signal lines, and the signals transmitted by the different light-emitting control signal lines may be the same or different.

For example, the reset control signals input to the first and second reset transistors T7 and T1 may be the same, i.e., the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may also be electrically connected to different reset control signal lines, and in this case, the signals on the different reset control signal lines may be the same or different.

For example, as shown in fig. 2, when the display substrate is operated, in the first stage of the screen display, the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second phase of the picture display, data are stored in the node N1 through the data write transistor T4, the driving transistor T3 and the threshold compensation transistor T2; in the third light emitting period, the second light emitting control transistor T5, the driving transistor T3 and the first light emitting control transistor T6 are all turned on, and the light emitting element is turned on to emit light in a forward direction.

It should be noted that, in the embodiment of the present disclosure, the pixel circuit of the sub-pixel may be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, in addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown in fig. 2, which is not limited in the embodiment of the present disclosure. It is sufficient to connect the data writing transistors T4 of the two pixel circuits and connect the N4 nodes of the two pixel circuits to realize the common driving of the same light emitting cell to emit light.

Fig. 3A is a schematic view of a partial planar structure of a stacked structure of an active semiconductor layer and a first conductive layer of a partial pixel circuit provided according to an embodiment of the present disclosure. As shown in fig. 3A, the active semiconductor layer 3100 may be formed using semiconductor material patterning. The active semiconductor layer 3100 may be used to fabricate active layers of the second reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, and the first reset control transistor T7 described above. The active semiconductor layer 3100 includes an active layer pattern (channel region) and a doped region pattern (source-drain doped region) of each transistor of each sub-pixel, and the active layer pattern and the doped region pattern of each transistor in the same pixel circuit are integrally provided.

The active layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region may be electrically connected to each other by being made conductive by doping or the like. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., a source region and a drain region) and an active layer pattern, with the active layers of different transistors being separated by a doped structure.

For example, the active semiconductor layer 3100 may be formed using amorphous silicon, polycrystalline silicon, an oxide semiconductor material, or the like. The source region and the drain region may be regions doped with n-type impurities or p-type impurities.

For example, the display substrate includes a gate insulating layer on a side of the active semiconductor layer away from the substrate, for insulating the active semiconductor layer 3100 from a subsequently formed first conductive layer 3200 (i.e., a gate metal layer). For example, the display substrate includes a first conductive layer 3200, and the first conductive layer 3200 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 3100. The first conductive layer 3200 may include a second pole CC2 of the capacitor C, a plurality of scan signal lines 430 extending in a second direction (Y direction in the drawing), a plurality of reset control signal lines 440, a plurality of light emission control signal lines 450, and gates of the second reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, and the first reset control transistor T7.

For example, as shown in fig. 3A, the gate of the data writing transistor T3 may be a portion where the scan signal line 430 overlaps the active semiconductor layer 3100; the gate of the first light emission control transistor T6 may be a first portion where the light emission control signal line 450 overlaps the active semiconductor layer 3100, and the gate of the second light emission control transistor T5 may be a second portion where the light emission control signal line 450 overlaps the active semiconductor layer 3100. The gate of the second reset transistor T1 is a first portion where the reset control signal line 440 overlaps the active semiconductor layer 3100, and the gate of the first reset control transistor T7 is a second portion where the reset control signal line 440 overlaps the active semiconductor layer 3100. The threshold compensation transistor T2 may be a thin film transistor having a double gate structure, the first gate electrode T2-g1 of the threshold compensation transistor T2 may be a portion where the protruding structure P protruding from the scan signal line 430 overlaps the active semiconductor layer 3100, and the second gate electrode T2-g2 of the threshold compensation transistor T2 may be a portion where the scan signal line 430 overlaps the active semiconductor layer 3100. As shown in fig. 3A, the gate of the driving transistor T1 may be the second pole CC2 of the capacitor C.

Note that each dotted rectangular frame in fig. 3A shows each portion where the active semiconductor layer 3100 overlaps with the first conductive layer 3200, that is, a channel region. As channel regions of the respective transistors, active semiconductor layers on both sides of each channel region are rendered conductive as first and second poles of the respective transistors by a process such as ion doping. The source and drain of the transistor may be symmetrical in structure, so that the source and drain may be physically indistinguishable. In the embodiments of the present disclosure, in order to distinguish transistors, in addition to the gate electrode as the control electrode, one of the electrodes is directly described as a first electrode, and the other electrode is directly described as a second electrode, so that the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure may be interchanged as necessary.

For example, as shown in fig. 3A, the scanning signal line 430, the reset control signal line 440, and the light emission control signal line 450 are arranged in the first direction (X direction). The scanning signal line 430 is located between the reset control signal line 440 and the light emission control signal line 450.

For example, in the first direction, the second pole CC2 of the capacitor C (i.e., the gate of the driving transistor T1) is located between the scan signal line 430 and the light emission control signal line 450. The protrusion structure P protruding from the scan signal line 430 is located at a side of the scan signal line 430 away from the light emission control signal line 450.

For example, a first insulating layer is formed over the first conductive layer 3200 to insulate the first conductive layer 3200 from a second conductive layer 3300 to be formed later.

Fig. 3B is a schematic partial plan view of a stacked structure of an active semiconductor layer, a first conductive layer, and a second conductive layer according to an embodiment of the disclosure. As shown in fig. 3B, the second conductive layer 330 includes a first pole CC1 of the capacitor C and a plurality of reset power signal lines 410 extending in the second direction. The first pole CC1 of the capacitor C at least partially overlaps the second pole CC2 of the capacitor C to form the capacitor C.

For example, the second conductive layer 330 further includes a plurality of caps S, and each of the threshold compensation transistors T2 includes two gates T2-g1 and T2-g2 and an active semiconductor layer 3100 between orthographic projections of the two gates on the active semiconductor layer 3100. The overlay S overlaps the active semiconductor layer 3100 between the two gates in a direction perpendicular to the substrate base.

For example, a second insulating layer is formed over the second conductive layer 3300 to insulate the second conductive layer 3300 from a source/drain metal layer 3400 to be formed later.

For example, fig. 3C is a schematic diagram of a via hole position in each insulating layer provided according to the embodiment of the present disclosure, fig. 3D is a schematic diagram of a partial planar structure of a source and drain metal layer provided according to the embodiment of the present disclosure, and fig. 3E is a schematic diagram of a stacked structure of an active semiconductor layer, a first conductive layer, a second conductive layer, and a source and drain metal layer provided according to the embodiment of the present disclosure. As shown in fig. 3C to 3E, the source-drain metal layer 3400 includes a data line 420 extending in the second direction and a power signal line 460. The data line 420 is electrically connected to the second pole of the data writing transistor T2 through a via 3005 penetrating the gate insulating layer 2 (shown in fig. 5D to 5H), the first insulating layer 3 (shown in fig. 5D to 5H), and the second insulating layer 4 (shown in fig. 5D to 5H). The power signal line 460 is electrically connected to the first pole of the second light emission controlling transistor T5 through a via 3009 penetrating the gate insulating layer 2, the first insulating layer 3, and the second insulating layer 4. The power signal lines 460 and the data lines 420 are alternately arranged in the first direction. The power signal line 460 is electrically connected to the first pole CC1 of the capacitor C (e.g., the first pole 120-CC1 of the capacitor C of the second pixel block 120, or the first pole 300-CC1 of the capacitor C of the third color sub-pixel 300) through a via 3007 penetrating the second insulating layer 4. For example, the second insulating layer 4 is an interlayer insulating layer.

For example, the dual gate type threshold compensation transistor may reduce leakage current. For example, the active semiconductor layer between two channels of the dual-gate threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is turned off, and is susceptible to a transition caused by a peripheral line voltage, thereby affecting the leakage current of the threshold compensation transistor T2, and further affecting the light emission luminance. In order to keep the voltage of the active semiconductor layer between the two channels of the threshold compensation transistor T2 stable, the cap S is designed to form a capacitance with the active semiconductor layer between the two channels of the threshold compensation transistor T2, the cap S can be connected to the power signal line 460 to obtain a constant voltage, and thus the voltage of the active semiconductor layer in a floating state can be kept stable. The overlapping of the covering portion S with the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2 can also prevent the active semiconductor layer between the two gates from being illuminated to change its characteristics, for example, prevent the voltage of the active semiconductor layer from changing, so as to prevent crosstalk from being generated. For example, as shown in fig. 3C to 3E, the power signal line 460 may be electrically connected to the cover S through a via 3003 penetrating the second insulating layer to provide a constant voltage to the cover S.

For example, a passivation layer 5 and a planarization layer 6 (shown in fig. 5D to 5H) may be sequentially disposed on a side of the source/drain metal layer 3400 away from the substrate to protect the source/drain metal layer 3400. For example, the planarization layer 6 may be located on the side of the passivation layer 5 remote from the substrate base plate. Of course, the embodiments of the present disclosure are not limited thereto, for example, the positions of the planarization layer 6 and the passivation layer 5 may be interchanged, that is, the passivation layer may be located on a side of the planarization layer away from the source drain metal layer, or, as shown in fig. 5I, only the planarization layer 6 is provided, and the passivation layer 5 is not provided.

For example, as shown in fig. 3C to 3E and 5D, the pixel circuit of each sub-pixel further includes a first connection portion 510 disposed at the same layer as the data line 420, and the first connection portion 510 extends in the first direction. The second pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the first connection portion 510, the first end of the first connection portion 510 is electrically connected to the gate of the driving transistor T3 by penetrating the gate insulating layer 2, the via 3004 of the first and second insulating layers 3 and 4 is connected to a second pole of the threshold compensation transistor T2 (e.g., the second pole 110-T2-2 of the threshold compensation transistor T2 of the first pixel block 110, or the second pole 120-T2-2 of the threshold compensation transistor T2 of the second pixel block 120, or the second pole 200-T2-2 of the threshold compensation transistor T2 of the second color sub-pixel 200), and the second end of the first connection portion 510 is connected to the gate of the driving transistor T3 (e.g., the gate 110-T3-g of the driving transistor T3 of the first pixel block 110, or the gate 120-T3-g of the driving transistor T3 of the second pixel block 120) through the via 3006 penetrating through the first and second insulating layers 3 and 4. The pixel circuit of each sub-pixel further includes a second connection portion 520 and a third connection portion 530 disposed at the same layer as the data line 420, the second connection portion 520 is connected to the second pole of the first light emission control transistor T6 through a via 3008 penetrating the gate insulating layer 1, the first insulating layer 2, and the second insulating layer 3, one end of the third connection portion 530 is connected to the first pole of the first reset transistor T7 through a via 3002 penetrating the gate insulating layer 1, the first insulating layer 2, and the second insulating layer 3, and the other end of the third connection portion 530 is connected to the reset power signal line 410 through a via 3001 penetrating the second insulating layer. For example, the first connection portion 510 overlaps a first pole CC1 of the capacitor C (e.g., the first pole 110-CC1 of the first pixel block 110, or the first pole 120-CC1 of the second pixel block 120).

For example, fig. 4 is a schematic diagram of a second electrode and an effective light emitting region of a light emitting element of each sub-pixel provided according to an embodiment of the present disclosure, fig. 5A is a schematic diagram of a stacked structure of the light emitting element and a source drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure, fig. 5B is a schematic diagram of a stacked structure of the light emitting element and an active semiconductor layer, a first conductive layer, and a source drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure, and fig. 5C is a schematic diagram of a stacked structure of the light emitting element and an active semiconductor layer, a first conductive layer, a second conductive layer, and a source drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure. As shown in fig. 4 to 5C, each first color sub-pixel pair 100 includes a first pixel block 110 and a second pixel block 120 arranged in the second direction (Y direction), the first pixel block 110 includes the first effective light emitting region 101, and the second pixel block 120 includes the second effective light emitting region 102. In the first pixel block 110, the minimum distance between the orthographic projection of the first connecting part 510 on the straight line extending along the second direction and the orthographic projection of the first effective light emitting region 101 on the straight line is a first distance, or the orthographic projection of the first connecting part 510 on the straight line extending along the second direction and the orthographic projection of the first effective light emitting region 101 on the straight line are overlapped; in the second pixel block 120, a minimum distance between an orthogonal projection of the first connection portion 510 on the straight line and an orthogonal projection of the second effective light emitting region 102 on the straight line is a second distance, and the first distance is smaller than the second distance. In the first pixel block 110, an overlapping area of an orthographic projection of the second electrode 112 on the substrate base and an orthographic projection of the first connection portion 510 on the substrate base is a first overlapping area; in the second pixel block 120, an overlapping area of an orthographic projection of the second electrode 122 on the substrate and an orthographic projection of the first connecting portion 510 on the substrate is a second overlapping area, and a ratio of the first overlapping area to the second overlapping area is, for example, 0.8 to 1.2, for example, 0.9 to 1.1.

In an embodiment of the present disclosure, the display substrate further includes other color sub-pixels, and a minimum distance between the first pixel block and the second pixel block in each first color sub-pixel pair is not greater than a minimum distance between two same color sub-pixels in the plurality of other color sub-pixels. For example, if the first color sub-pixel pair is a green sub-pixel pair and the other color sub-pixels include a red sub-pixel, then the minimum distance between two green sub-pixels in the green sub-pixel pair is less than the minimum distance between two red sub-pixels.

For example, in the first pixel block 110, the minimum distance between the center of the orthographic projection of the first connection portion 510 on the straight line extending in the second direction and the center of the orthographic projection of the first effective light emitting region 101 on the straight line is a first distance; in the second pixel block 120, the minimum distance between the center of the orthographic projection of the first connection portion 510 on the straight line and the center of the orthographic projection of the second effective light emitting region 102 on the straight line is a second distance, and the first distance is smaller than the second distance.

In the first color sub-pixel pair, when the distance between the geometric center of the first effective light emitting area and the edge of the first connection portion of the first pixel block close to the first effective light emitting area is not equal to the distance between the geometric center of the second effective light emitting area and the edge of the first connection portion of the second pixel block close to the second effective light emitting area, the area covered by the two second electrodes of the two first connection portions in the two first color sub-pixels is different, so that the capacitance formed between the first connection portion and the second electrode in the two first color sub-pixels of the same first color sub-pixel pair is different, the gate node loads of the driving transistors in the two first color sub-pixels are different, and the luminance when the two first color sub-pixels emit light is different.

In the embodiment of the disclosure, the ratio of the overlapping area of the two second electrodes and the two first connecting portions in the two first color sub-pixels of the same first color sub-pixel pair is set to be 0.8 to 1.2, for example, 0.9 to 1.1. For example, the overlapping area ratio of the two second electrodes to the two first connecting portions in the two first color sub-pixels of the same first color sub-pixel pair is substantially equal, so that the difference of the gate node loads of the driving transistors in the two first color sub-pixels can be reduced as much as possible, and the luminance of the two first color sub-pixels when emitting light can be ensured to be the same as much as possible.

For example, the ratio of the first overlapping area to the second overlapping area is 1, i.e. the two overlapping areas are identical, thereby ensuring that the luminance when the two first color sub-pixels emit light is the same.

For example, in the first pixel block 110, the second electrode 112 covers 60 to 90% of the area of the first connection portion 510; in the second pixel block 120, the second electrode 122 covers 60 to 90% of the area of the first connection portion 510. For example, in the first pixel block 110, the second electrode 112 covers 70-80% of the area of the first connection portion 510 (the covered area is a benefit of these); in the second pixel block 120, the second electrode 122 covers 70 to 80% of the area of the first connection portion 510. For example, considering that a certain distance is maintained between the second electrode of the second pixel block and the second electrode of the third color sub-pixel (described later), the area of the second electrode of the second pixel block covering the first connection portion cannot be too large, for example, 70%.

For example, as shown in fig. 4 to 5C, the relative positional relationship of the gate of the threshold compensation transistor T2 and the first connection portion 510 in each pixel circuit is substantially the same, for example, the first connection portion 510 is located between the gate of the threshold compensation transistor T2 and the second pole of the data write transistor T4.

For example, the two effective light emitting areas in the first color sub-pixel pair 100 have substantially the same shape and size, and are axially symmetric about a straight line passing through a midpoint of a central connecting line of the two effective light emitting areas and extending along the first direction.

For example, the shapes of the first and second effective light emitting areas 101 and 102 may include pentagons, circles, or drop shapes. For example, the first and second effective light emitting areas 101 and 102 may be shaped as pentagons including a set of parallel opposite sides (parallel to the second direction) and a vertical side (parallel to the first direction) perpendicular to the set of parallel opposite sides, the two vertical sides of the two effective light emitting areas in each first color sub-pixel pair 100 being disposed adjacent to each other, and each pentagon including a sharp corner opposite to the vertical side, the two sharp corners of the two effective light emitting areas in each first color sub-pixel pair 100 being distant from each other. For example, the distance between two sharp corners of two effective light emitting areas in the first color sub-pixel pair 100 is greater than the length of the effective light emitting areas of the second color sub-pixel 200 and the third color sub-pixel 300.

Furthermore, although the shape of the effective light emitting area of the first color sub-pixel in the figure includes a strict corner formed by two line segments, in some embodiments, the shape of the effective light emitting area of the first color sub-pixel may be all rounded, such as a circle or a drop. That is, on the basis of the above-described pentagonal shape, the corners of the effective light-emitting area of the first-color sub-pixel are rounded. For example, when the opening of the pixel defining layer is formed, a portion at the corner of the opening is formed in a rounded shape, and thus the light emitting region is formed in a rounded shape.

For example, as shown in fig. 4 to 5C, the first and second effective light emitting regions 101 and 102 are located between the two first connection portions 510 in the first color sub-pixel pair 100, and the perpendicular bisector M1 of the line connecting the two vertical midpoints of the first and second effective light emitting regions 101 and 102 is located on the side of the perpendicular bisector M2 of the line connecting the two midpoints of the two first connection portions 510 close to the first connection portion 510 of the first pixel block 110. Therefore, the distance from the center of the first effective luminous zone to the corresponding first connecting part is smaller than the distance from the center of the second effective luminous zone to the corresponding first connecting part.

For example, as shown in fig. 4 to 5C, in the first pixel block 110, the gate of the threshold compensation transistor T2 is located on the side of the first connection portion 510 away from the first effective light emitting region 101, i.e., in the first pixel block 110, the first connection portion 510 is closer to the first effective light emitting region 101 than the gate of the threshold compensation transistor T2. In the second pixel block 120, the gate of the threshold compensation transistor T2 is located at a side of the first connection portion 510 close to the second effective light emitting region 102, that is, in the second pixel block 120, the gate of the threshold compensation transistor T2 is closer to the second effective light emitting region 102 than the first connection portion 510. Therefore, the distance from the first connecting part of the second pixel block to the center of the second effective luminous area is larger than the distance from the first connecting part of the first pixel block to the first effective luminous area.

For example, as shown in fig. 4 to 5C, the maximum length of the second electrode 122 of the second pixel block 120 in the second direction is greater than the maximum length of the second electrode 112 of the first pixel block 110 in the second direction, so that the overlapping areas of the second electrodes of the two first color sub-pixels and the corresponding first connection portions are substantially equal.

For example, as shown in fig. 4 to 5C, the second electrode of each sub-pixel includes a body electrode and a connection electrode. For example, the second electrode 112 in the first pixel block 110 includes a main body electrode 1121 and a connection electrode 1122, and the shape of the main body electrode 1121 is substantially the same as the shape of the first effective light emitting region 101, such as a pentagon. For example, the orthographic projection of the first effective light emitting area on the substrate is positioned in the orthographic projection of the main body electrode on the substrate. For example, an orthogonal projection of the body electrode 1121 on the substrate overlaps with an orthogonal projection of the first connection portion 510 on the substrate. For example, the second electrode 122 in the second pixel block 120 includes a body electrode 1221 and a connection electrode 1122, and the shape of the body electrode 1221 is substantially the same as that of the second effective light emitting area 102, such as a pentagon. For example, the orthographic projection of the second effective light emitting area on the substrate is positioned in the orthographic projection of the main body electrode on the substrate. For example, an orthogonal projection of the body electrode 1221 on the substrate does not overlap with an orthogonal projection of the first connection portion 510 on the substrate.

For example, as shown in fig. 4 to 5C, in the first color sub-pixel pair 100, the second electrode further includes an auxiliary electrode connecting the main body electrode and the connection electrode. For example, the second electrode 112 in the first pixel block 110 further includes an auxiliary electrode 1123 connecting the main body electrode 1121 and the connection electrode 1122, and the connection electrode 1122 extends in the first direction. For example, the second electrode 121 in the second pixel block 120 further includes an auxiliary electrode 1223 connecting the body electrode 1221 and the connection electrode 1222.

For example, as shown in fig. 4 to 5C, in the first pixel block 110, the auxiliary electrode 1123 is located on the side of the main body electrode 1121 away from the second effective light emitting region 102, and in the second pixel block 120, the auxiliary electrode 1223 is located on the side of the main body electrode 1221 away from the first effective light emitting region 101. That is, the two auxiliary electrodes of the first color sub-pixel pair are located on the sides of the two effective light emitting areas away from each other.

For example, as shown in fig. 4 to 5C, the second electrode in each first color sub-pixel is an integral structure, that is, the second electrode includes a main electrode, an auxiliary electrode, and a connection electrode. In order to clearly describe the shape and other structural relationships of the second electrode in the first color sub-pixel, the second electrode in the first color sub-pixel is divided into a main electrode, an auxiliary electrode and a connection electrode.

For example, as shown in fig. 4 to 5C, in the first color sub-pixel pair 100, the two main electrodes 1121 and 1221 have substantially the same shape and size, the two auxiliary electrodes 1123 and 1223 have different shapes, and the two connection electrodes 1122 and 1222 have different shapes.

For example, as shown in fig. 4 to 5C, for example, an orthogonal projection of a first edge 1001 distant from the second effective light emitting region 102 in edges extending in the first direction in a portion of the connection electrode 1222 near the auxiliary electrode 1223 on the substrate overlaps with an orthogonal projection of the first connection portion 510 on the substrate. For example, in the second pixel block 120, the second edge 1002 of the auxiliary electrode 1223, which is away from the connection electrode in the Y direction, is located on the side of the first connection portion 510, which is away from the second effective light emitting area 102, so that the auxiliary electrode 1223 covers at least part of the first connection portion 510. For example, a portion of the connection electrode 1222 distant from the auxiliary electrode 1223 is configured to be connected to the second connection portion 520, and a width in the Y direction of a portion of the connection electrode 1222 distant from the auxiliary electrode 1223 is larger than a width in the Y direction of a portion of the connection electrode 1222 near the auxiliary electrode 1223 according to a size in which the via hole is provided in the planarization layer, whereby an edge distant from the second effective light emitting area 102 among edges extending in the first direction in the portion of the connection electrode 1222 distant from the auxiliary electrode 1223 is not on the same straight line 1001 as the first edge 1001.

For example, as shown in fig. 4 to 5C, in the first pixel block 110, a straight line along which the third edge 1003 far from the first effective light emitting area 101 is located in a portion of the connection electrode 1122 close to the auxiliary electrode 1123 in the first direction is located on a side of the first connection portion 510 far from the first effective light emitting area 101. For example, an orthogonal projection of the third edge 1003 of the portion of the connection electrode 1122 near the auxiliary electrode 1123 on the substrate does not overlap with an orthogonal projection of the first connection portion 510 on the substrate. For example, a portion of the connection electrode 1122 distant from the auxiliary electrode 1123 is configured to be connected to the second connection portion 520, and a width in the Y direction of a portion of the connection electrode 1122 distant from the auxiliary electrode 1123 is larger than a width in the Y direction of a portion of the connection electrode 1122 near to the auxiliary electrode 1123 according to a size of the via hole provided in the planarization layer, whereby an edge distant from the first effective light emitting area 101 among edges extending in the first direction in the portion of the connection electrode 1122 distant from the auxiliary electrode 1123 is not on the same straight line as the third edge 1003.

For example, as shown in fig. 4 to fig. 5C, in the first pixel block 110, a fourth edge 1004 of a portion of the auxiliary electrode 1123, which is connected to the connection electrode 1122 (e.g., a first portion 1123-1 of the auxiliary electrode 1123 described later), which is far from the first effective light emitting region 101, is aligned with a third edge 1003 of the connection electrode 1122 to facilitate the fabrication of the second electrode.

For example, in the second pixel block 120, the edge of the portion of the auxiliary electrode 1223 close to the connection electrode 1222, which is far from the second effective light emitting area 102, is not aligned with the first edge 1001 of the connection electrode 1222. For example, in the second pixel block 120, the second edge 1002 of the portion of the auxiliary electrode 1223 away from the connection electrode 1222, which extends in the first direction, away from the second active light emitting area 102 is not aligned with the first edge 1001 of the connection electrode 1222. For example, in the second pixel block 120, the line on which the second edge 1002 of the auxiliary electrode 1223 is located on the side of the line on which the first edge 1001 of the connection electrode 1221 is located away from the second effective light emitting area 102 to cover the first connection portion 510. For example, the connecting edge between the first edge 1001 and the second edge 1002 may be a straight line edge intersecting the X direction, but is not limited thereto, and may also be a polygonal line edge or a curved line edge.

The first edge, the second edge, the third edge, and the fourth edge are shown schematically as straight edges to facilitate manufacturing, but are not limited thereto, and may also be curved edges or broken line edges as long as the extending direction is along the X direction.

Because the third edge of the connection electrode of the first pixel block is positioned on one side of the connection electrode far away from the first effective luminous area, the edge of the part, connected with the connection electrode, of the auxiliary electrode and the third edge of the connection electrode are positioned on the same straight line, so that the first connection part can be covered, and the edge, away from the first connection part, of the part, close to each other, of the auxiliary electrode and the connection electrode can be designed on the same straight line so as to be convenient to manufacture.

If the second edge of the auxiliary electrode of the second pixel block and the first edge of the connection electrode of the second pixel block are located on the same straight line, the area of the auxiliary electrode of the second pixel block covering the first connection part is different from the area of the auxiliary electrode of the first pixel block covering the corresponding first connection part, which may cause the brightness difference of the two first color sub-pixels. Therefore, in the embodiment of the present disclosure, the first edge of the connection electrode of the second pixel block and the second edge of the auxiliary electrode are not located on one side, and the straight line where the second edge of the auxiliary electrode is located on one side, away from the second effective light emitting area, of the straight line where the first edge of the connection electrode is located, so that the overlapping areas of the auxiliary electrode and the first connection portion in the two first color sub-pixels of the first color sub-pixel pair are substantially the same, and the load difference of the gate nodes of the driving transistors in the two first color sub-pixels is reduced, thereby reducing the luminance difference of the two first color sub-pixels to improve the display characteristics of the display substrate.

For example, as shown in fig. 3C to 5C, the pixel circuit of each sub-pixel further includes a second connection portion 520 disposed at the same layer as the first connection portion 510, and the second connection portion 520 is electrically connected to the second pole of the first light emission controlling transistor T6 through a via 3008 penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. And the connecting electrode of the second electrode of each sub-pixel is connected with the second connecting part through a via hole penetrating through the flat layer, so that the connection with the first light-emitting control transistor is realized.

For example, in the first pixel block 110, the second connection portion 520 is farther from the first effective light emitting region 101 than the first connection portion 510 in the second direction, and thus the connection electrode 1122 is farther from the first effective light emitting region 101 than the first connection portion 510 in the second direction. For example, in the second pixel block 120, the second connection portion 520 is closer to the second effective light emitting region 102 than the first connection portion 510 in the second direction, and thus the connection electrode 1222 is closer to the second effective light emitting region 102 than the first connection portion 510 in the second direction.

For example, as shown in fig. 3C to 5C, a planarization layer is disposed between the film layer where the second connection portion 520 is located and the film layer where the connection electrode is located, or a passivation layer and a planarization layer are disposed between the film layer where the second connection portion 520 is located and the film layer where the connection electrode is located. The planarization layer includes a plurality of via holes 3010 therethrough, and the connection electrode in each sub-pixel is electrically connected to the second connection portion 520 through the via hole 3010. For example, the corresponding via 3010 in the first pixel block 110 is farther from the first effective light emitting region 101 than the first connection portion 510 in the first pixel block 110 in the second direction, and thus the connection electrode 1122 is farther from the first effective light emitting region 101 than the first connection portion 510 in the second direction. For example, the via 3010 corresponding to the second pixel block 120 is closer to the second effective light emitting region 102 than the first connection portion 510 in the second pixel block 120 in the second direction, and thus the connection electrode 1222 is closer to the second effective light emitting region 102 than the first connection portion 510 in the second direction.

For example, as shown in fig. 4 to 5J, in the first pixel block 110, the first gate 110-T2-g1 of the threshold compensation transistor T2 is located at a side of the second gate 110-T2-g2 close to the first effective light emitting area 101 in the second direction, a straight line where the third edge 1003 of the connection electrode 1122 is located overlaps the first gate T2-g1, and an edge of the auxiliary electrode 1123 (e.g., a second portion 1123-2 of the auxiliary electrode 1123 described later) away from the first effective light emitting area 101 is located at a side of the first gate T2-g1 away from the first effective light emitting area 101 so that the auxiliary electrode 1123 covers the first gate T2-g 1. For example, as shown in fig. 5G, the protruding structure P and the cover S (described later) each overlap with the active semiconductor layer of the threshold compensation transistor T2. In the embodiment of the disclosure, the auxiliary electrode covering the first gate of the threshold compensation transistor is disposed in the first pixel block, so that external light can be prevented from directly irradiating the channel region of the threshold compensation transistor, and characteristic deviation of the threshold compensation transistor caused by illumination when the display substrate displays is avoided.

For example, as shown in fig. 4 to 5C, in the first pixel block 110, the auxiliary electrode 1123 includes a first portion 1123-1 and a second portion 1123-2 connected to each other, the first portion 1123-1 is connected to the connection electrode 1122, the second portion 1123-2 covers at least a portion of the first gate T2-g1 of the threshold compensation transistor T2, a fourth edge 1004 of the first portion 1123-1 extending in the first direction is located on the same straight line as the third edge 1003 of the connection electrode 1122, and an edge of the second portion 1123-2 extending in the first direction is farther from the first effective light emitting region 101 than the fourth edge 1004 in the Y direction. For example, the second section 1123-2 is located on a side of the second gate T2-g2 of the threshold compensation transistor T2 away from the connection electrode 1122 in the first direction. For example, in the first pixel block 110, the auxiliary electrode 1123 covers a portion of the active layer between the first gate electrode T2-g1 of the threshold compensation transistor T2 and the second gate electrode T2-g2 of the threshold compensation transistor T2.

In the embodiment of the disclosure, the protrusion protruding to the side away from the first effective light emitting area is disposed in the auxiliary electrode of the first pixel block to cover the first gate of the threshold compensation transistor and a part of the active layer between the first gate and the second gate, so that it can be ensured that the second electrode of the first pixel block can cover a channel region of the threshold compensation transistor even if a certain degree of alignment shift exists in the forming process, thereby preventing the transistor characteristics from shifting due to illumination, and further preventing the writing of the gate potential of the driving transistor from being affected.

In the embodiment of the disclosure, the threshold compensation transistor has a double-gate structure and has two channel regions, the second gate of the threshold compensation transistor in the first pixel block is not covered by the second electrode, and in order to ensure that at least one channel region of the threshold compensation transistor is in a blocked state to ensure the characteristics of the threshold compensation transistor, a protrusion protruding to a side far away from the first effective light emitting region is provided in the auxiliary electrode of the first pixel block, so that the first gate of the threshold compensation transistor can be completely covered by the second electrode.

For example, the second electrode of the first pixel block covers one of two gates of the threshold compensation transistor, and the second electrode of the second pixel block covers two gates of the threshold compensation transistor.

For example, in a direction perpendicular to the substrate, the body electrode of the second electrode of the first pixel block overlaps the cover S, and the body electrode of the second pixel block overlaps the cover S.

For example, as shown in fig. 1 to 5C, the second electrode 320 of the third color sub-pixel 300 further includes an auxiliary electrode 323 located on a side of the main electrode 321 away from the connection electrode 322 and connected to the main electrode 321. The shape of the main body electrode 321 of the third color sub-pixel 300 is the same as that of the effective light emitting area 301, for example, both of the main body electrode and the effective light emitting area are hexagonal or elliptical, and the connection electrode 322 is connected to the second connection portion 520 through a via 3010 penetrating through the planarization layer to realize connection with the first light emitting control transistor T6.

For example, as shown in fig. 1 to 5H, in the third color sub-pixel 300, the second gate 300-T2-g2 of the threshold compensation transistor T2 is located at one side of the first gate 300-T2-g1 close to the effective light emitting region 301 of the third color sub-pixel 300, and the auxiliary electrode 323 covers a portion of the active layer between the second gate T2-g2 and the first gate T2-g 1. For example, as shown in fig. 5H, the protruding structure P and the cover S (described later) each overlap with an active semiconductor layer of the threshold compensation transistor T2. In the embodiment of the disclosure, the threshold compensation transistor is a dual-gate structure and has two channel regions, the first gate of the threshold compensation transistor in the third color sub-pixel is not covered by the second electrode, and in order to ensure that at least one channel region of the threshold compensation transistor is in a shielded state to ensure the characteristics of the threshold compensation transistor, a protruding bump is arranged on one side of the main body electrode of the third color sub-pixel, which is far away from the connection electrode, to form an auxiliary electrode, so that one channel region of the threshold compensation transistor can be completely covered even if a certain degree of alignment shift exists in the process of forming the second electrode, the transistor characteristics are prevented from shifting due to illumination, and further writing of the gate potential of the driving transistor is prevented from being influenced.

For example, the light-emitting element may be a light-emitting element or an inorganic light-emitting element.

For example, as shown in fig. 5D, the second electrode of each color sub-pixel is provided with a pixel defining layer 7 on the side away from the substrate, the pixel defining layer 7 includes an opening 070 to expose a portion of the second electrode, and when a subsequent organic light emitting layer is formed in the opening 070 of the pixel defining layer 7, the organic light emitting layer is in contact with the second electrode, so that the portion can drive the organic light emitting layer to emit light.

For example, fig. 6 is a schematic partial cross-sectional structure of a display substrate. As shown in fig. 6, the display substrate includes a film layer 010, and the film layer 010 includes a substrate, an active semiconductor layer on the substrate, and at least one conductive layer on a side of the active semiconductor layer away from the substrate. The display substrate further includes a source-drain metal layer 011 on the film layer 010, for example, the source-drain metal layer 011 may include data lines, power signal lines, and the like. The display substrate further includes a planarization layer 012 located on a side of the source-drain metal layer 011 away from the film layer 010, an anode 013 located on a side of the planarization layer 012 away from the source-drain metal layer 011, and a pixel defining layer 014 located on a side of the anode 013 away from the planarization layer 012. The pixel defining layer 014 includes a plurality of openings 015-017 for defining light emitting areas of the sub-pixels. The plurality of openings 015-.

As shown in fig. 6, the thickness of the source-drain metal layer 011, which may be 0.6-0.9 μm, for example, causes unevenness in the surface of the planarization layer 012 facing the anode 013 on the source-drain metal layer 011. For example, the distance between the surface of the planarization layer 012 located directly above the source-drain metal layer 011 (e.g., data lines, power signal lines, and patterns of the same material as the data lines and the power signal lines) which is distant from the film 010 and the surface of the film 010 which is distant from the planarization layer 012 is h1, and the distance between the surface of the planarization layer 012 which is distant from the film 010 and the surface of the film 010 which is distant from the planarization layer 012 at a position directly above a region where the source-drain metal layer 011 is not provided is h2, and h1> h 2.

As shown in fig. 6, in the opening 016, the source-drain metal layer 011 is provided directly below a part of the planarization layer 012 and the source-drain metal layer 011 is not provided directly below the other part, so that the surface of the planarization layer 012 facing the anode 013 in the opening 016 is uneven, resulting in uneven surface of the anode 013 on the planarization layer 012. For example, with respect to the anode 013 located in the opening 016, the distance between the surface of the anode 013 located directly above the source-drain metal layer 011, which is away from the film layer 010, and the surface of the film layer 010, which is away from the anode 013, is h3, and the distance between the surface of the anode 013, which is away from the film layer 010, at the position where the source-drain metal layer 011 is not provided, and the surface of the film layer 010, which is away from the anode 013, is h4, and h3> h 4. This "tilts" the anode 013 in the opening 016. Similarly, the anode 013 in the opening 015 is also "tilted", and the "tilt direction" of the anode 013 in the opening 015 is different from the "tilt direction" of the anode 013 in the opening 016 according to the position difference of the source-drain metal layer 011, so that the intensities of light emission in different directions of the sub-pixels corresponding to the opening 015 and the opening 016 are different. When the direction indicated by the arrow in the Y direction is the right, the light intensities emitted from the sub-pixel light emitting regions defined by the openings 015 and 016 are not the same. The source-drain metal layer 011 is not disposed directly below the anode 013 within the opening 017, so the surface of the anode 013 within the opening 017 is substantially flat without "tilt", and the light emitting regions of the sub-pixels defined by the opening 017 emit light in different directions with the same intensity. For the light emitting regions of the adjacent three different color sub-pixels defined by the openings 015-. The display device adopting the display substrate has large visual angle color cast, and when people watch the display device, the display device has the color cast phenomenon that one side becomes red and the other side becomes green.

For example, in the first pixel block, the orthographic projection of the second electrode on the substrate is overlapped with the orthographic projection of the gate electrode of the driving transistor on the substrate; in the second pixel block, an orthographic projection of the second electrode on the substrate overlaps with an orthographic projection of the gate electrode of the driving transistor on the substrate.

For example, in each color sub-pixel, the overlapping area of the orthographic projection of the second connecting part on the substrate and the orthographic projection of the first electrode of the capacitor on the substrate is small.

For example, as shown in fig. 5C and 5J, the second electrode of the second color sub-pixel covers the via holes 3009 and 3021 connecting the source-drain metal layer and the active semiconductor layer.

In another example of the embodiment of the present disclosure, as shown in fig. 3A to 5C, the plurality of data lines 420 includes a plurality of first data lines 421, and the plurality of power signal lines 460 includes a plurality of first power line signal lines 461. For example, in a third direction perpendicular to the substrate, the second electrode 220 of the second color sub-pixel 200 overlaps the first data line 421, the first power signal line 461 and the second connection portion 520, and in a portion where the first data line 421, the first power signal line 461 and the second connection portion 520 overlap the second electrode 220, the first power signal line 461 and the first data line 421 are located at both sides of the second connection portion 520, and a ratio of a minimum distance d1 (shown in fig. 5B) between edges where the second connection portion 520 and the first power signal line 461 are close to each other to a minimum distance d2 (shown in fig. 5B) between edges where the second connection portion 520 and the first data line 421 are close to each other is 0.8-1.2. For example, a ratio of a minimum distance between edges of the second connection part 520 and the first power signal line 461 that are close to each other to a minimum distance between edges of the second connection part 520 and the first data line 421 that are close to each other is 0.9 to 1.1. For example, a ratio of a minimum distance between edges where the second connection part 520 and the first power signal line 461 are close to each other to a minimum distance between edges where the second connection part 520 and the first data line 421 are close to each other is 1.

In the embodiment of the disclosure, the distances between the second connecting part and the adjacent data line and power signal line are set to be approximately equal, so that the height difference between the middle area (the area without overlapping with the data line and the power signal line) and the two side areas (the area with overlapping with the data line and the power signal line) of the second electrode of the second color sub-pixel can be reduced, the flatness of the second electrode of the second color sub-pixel is improved, and the color shift is improved.

For example, the minimum distance between the first data line 421 and the first power signal line 461 may be 20-25 micrometers, and the maximum dimension of the second connection part 520 along the Y direction may be 15-20 micrometers. The embodiments of the present disclosure are not limited thereto as long as the distance between the first data line, the second connection portion, and the first power signal line is not less than 3 micrometers.

For example, as shown in fig. 3A to 5C, in the third direction, the effective light emitting region 202 of each second color sub-pixel 200 overlaps with the first data line 421, the first power signal line 461 and the second connection portion 520, and in the portion where the first data line 421, the first power signal line 461 and the second connection portion 520 overlap with the effective light emitting region 201 of the second color sub-pixel 200, the ratio of the distance between the edges where the second connection portion 520 and the first power signal line 461 are close to each other to the distance between the edges where the second connection portion 520 and the first data line 421 are close to each other is 0.8 to 1.2, for example, 0.9 to 1.1, so that the height difference between the middle region and the two side regions of the second color sub-pixel second electrode can be reduced, and the flatness of the second electrode in the effective light emitting region of the second color sub-pixel can be improved to improve color shift.

For example, as shown in fig. 3A to 5C, in the portion of the second connection portion 520 overlapping the effective light emitting region 202 of the second color sub-pixel 200, the distance between the second connection portion 520 and the first data line 421 is substantially equal to the distance between the second connection portion 520 and the first power signal line 461, and the flatness of the second electrode in the effective light emitting region of the second color sub-pixel can be further ensured to improve color shift.

For example, as shown in fig. 3A to 5C, distances to both end points of the effective light emitting region 201 of the second color sub-pixel 200 in the Y direction (direction intersecting the data line extending direction) are substantially equal and an orthogonal projection of a straight line extending in the X-th direction on the substrate overlaps with an orthogonal projection of the second connection portion 520 on the substrate. For example, the orthogonal projection of a straight line extending in the X direction through the midpoint of the line connecting the two end points of the effective light emitting areas 201 of the second color sub-pixels 200 opposing each other in the Y direction on the substrate overlaps with the orthogonal projection of the second connection portion 520 on the substrate. For example, an orthogonal projection of a straight line passing through a midpoint of a connection line of two end points of the effective light emitting area 201 of the second color sub-pixel 200 in the Y direction (a direction intersecting the extending direction of the data line) and extending in the X direction on the substrate overlaps an orthogonal projection of the second connection portion 520 on the substrate. Therefore, in the embodiment of the disclosure, with respect to the distribution positions of the first data line and the first power signal line, the center line of the effective light emitting area 201 of the second color sub-pixel 200 extending along the first direction overlaps with the second connection portion, so that the symmetry of the second electrode can be improved, and the color shift can be improved.

For example, as shown in fig. 3A to 5C, the second connection part 520 includes a first sub-connection part 521 connected to each other and a first pad 522 positioned at a side of the first sub-connection part 521 close to the first power signal line 461, and the second electrode 220 of the second color sub-pixel 200 is electrically connected to the second pole of the first light emission controlling transistor T6 through the first sub-connection part 521. For example, the first spacer and the first sub-connection portion are of a unitary structure. The second connecting portion is schematically divided into the first sub-connecting portion and the first pad block, so that the position relationship between the second connecting portion and the second electrode of the second color sub-pixel and the effective light emitting area can be clearly shown.

For example, as shown in fig. 3A to 5C, the first sub-connection 521 has a rectangular shape extending in the X-direction, and a straight line passing through the center of the effective light emitting region 201 of the second color sub-pixel 200 and extending in the X-direction does not coincide with a second straight line passing through the center of the first sub-connection 521 and extending in the X-direction. For example, a center line passing through the center of the effective light emitting region 201 of the second color sub-pixel 200 is located at a side of a center line passing through the center of the first sub-connecting portion 521 near the first pad 522. Therefore, the whole first sub-connection portion is shifted to the left (the direction indicated by the arrow in the Y direction is the right) relative to the center line of the second color sub-pixel extending in the X direction, and if the first pad is not provided, the height difference between the two sides of the center line of the second electrode of the second color sub-pixel is large, the symmetry of the second electrode is not good, and color shift is easily generated in the Y direction. In the embodiment of the disclosure, the first pad is disposed between the first sub-connection portion and the first power signal line, so that the overlapping position of the second connection portion and the second electrode of the second color sub-pixel is located in the middle area of the effective light emitting area of the second color sub-pixel, the height difference between the middle area and the two side areas of the second electrode of the second color sub-pixel can be reduced, the symmetry is improved, and it is beneficial to ensure that the luminous intensities of the effective light emitting areas are consistent in all directions, so as to improve color cast.

For example, as shown in fig. 3A to 5C, the second connection part 520 in the second color sub-pixel 200 has an L-shape, and the size of the first sub-connection part 521 is larger than that of the first pad 522 along the X-direction. For example, the second electrode 220 of the second color sub-pixel 200 includes a main body electrode 221 and a connection electrode 222 connected to each other, and the shape of the main body electrode 221 is the same as that of the effective light emitting area 201, for example, both are hexagonal or elliptical. For example, the orthographic projection of the effective light emitting area of the second color sub-pixel on the substrate is positioned in the orthographic projection of the main body electrode on the substrate. For example, in a direction perpendicular to the substrate base, a portion of the first sub-link 521 overlaps the body electrode 221, another portion of the first sub-link 521 overlaps the connection electrode 222 and is connected to the connection electrode 222 through the via hole 3010 in the planarization layer, and the first pad block 521 overlaps only the body electrode 221 without overlapping the connection electrode 222. For example, the via 3010 (e.g., a first via 3011 to be described later) is farther from the effective light emitting area 201 of the second color sub-pixel 200 than the first pad 522. For example, more than 90% of the orthographic projection of the second connection part 520 of the second color sub-pixel 200 on the substrate falls within the orthographic projection of the second electrode 220 on the substrate. In the embodiment of the present disclosure, the first pad may be only disposed at the position of the second electrode of the first color sub-pixel, so as to cooperate with the first sub-connection portion to improve the flatness and symmetry of the second electrode. In the embodiment of the present disclosure, the first pad is not disposed except the position of the second electrode, but the shape of the second connection portion in the second color sub-pixel may also be designed according to the process conditions and the actual requirements of the product.

For example, as shown in fig. 3A to 5C, the effective light emitting area 201 of the second color sub-pixel 200 overlaps with the third connection portion 530 along the third direction, and a straight line passing through the geometric center of the effective light emitting area 201 and extending along the X direction overlaps with the third connection portion 530. For example, the connection electrode 222 is located on a side of a straight line passing through the geometric center of the effective light emitting region 201 and extending in the Y direction away from the third connection portion 530. For example, the third connection portion 530 is substantially located in the middle region of the effective light emitting region 201 of the second color sub-pixel 200. For example, the second connection portion 520 and the third connection portion 530 are respectively located at two sides of a straight line passing through the center of the effective light emitting area 201 of the second color sub-pixel 200 and extending in the Y direction, that is, the second connection portion 520 and the third connection portion 530 are respectively located at two sides of a center line of the effective light emitting area 201 of the second color sub-pixel 200 extending in the Y direction. For example, the second connection portion 520 is located at one side of a straight line passing through the center of the effective light emitting area 201 of the second color sub-pixel 200 and extending in the Y direction, and at least a portion of the third connection portion 530 is located at the other side of the straight line. Compared with the data lines and the power signal lines which are distributed in the areas on two sides of the effective light emitting area, in the embodiment of the disclosure, the source drain metal layers covered by the middle area of the second electrode of the second color sub-pixel are fewer, and by arranging the first cushion block and arranging the overlapped parts of the third connecting part and the second connecting part comprising the first cushion block and the effective light emitting area of the second color sub-pixel in the middle area of the effective light emitting area, the height difference between the middle area and the areas on two sides of the second electrode in the effective light emitting area can be reduced, the flatness is improved, and the color cast is improved.

For example, as shown in fig. 3A to 5C, the data lines 420 further include a plurality of second data lines 422, and the second data lines 422 and the first data lines 421 are disposed in the same layer and are alternately disposed. The plurality of power signal lines 460 further includes a plurality of second power signal lines 462, and the plurality of second power signal lines 462 are disposed in the same layer and alternate with the plurality of first power signal lines 461. For example, in the third direction, the second electrode 220 of each second color sub-pixel 200 overlaps the first data line 421, the first power signal line 461, the second connection portion 520, the second data line 422 and the second power signal line 462, and in the overlapping portion, the second power signal line 462 is located on the side of the first data line 421 away from the second connection portion 520, and the second data line 422 is located on the side of the first power signal line 461 away from the second connection portion 520. That is, the second electrode 220 of the second color sub-pixel 200 overlaps the two data lines 420 and the two power signal lines 460, and the first data line 421 and the second power signal line 462 are disposed at one side of the second connection part 520, and the second data line 422 and the first power signal line 461 are disposed at the other side of the second connection part 520.

For example, as shown in fig. 3A to 5C, the effective light emitting region 201 of each second color sub-pixel 200 overlaps the first data line 421, the first power signal line 461, the second data line 422 and the second power signal 462 line, and in the overlapping portion, the ratio of the overlapping area of the first power signal line 461 and the second data line 422 and the effective light emitting region 201 to the overlapping area of the second power signal line 462 and the first data line 421 and the effective light emitting region 201 is 0.8 to 1.2, for example, 0.9 to 1.1. In the embodiment of the disclosure, the two side areas of the effective light emitting area of the second color sub-pixel are overlapped with the data line and the power signal line, and the overlapped areas of the source drain metal layers positioned at the two sides of the second connecting part of the second color sub-pixel and the effective light emitting area are approximately equal, so that the effective light emitting area of the second color sub-pixel and the overlapped parts of the source drain metal layers have better symmetry, and color cast is favorably prevented.

For example, as shown in fig. 3A to 5C, the first data line 421 overlapping the second electrode 220 of the second color sub-pixel 200 is electrically connected to the second pole of the data write transistor T4 of the first pixel block 110, and the second power signal line 462 overlapping the second electrode 220 of the second color sub-pixel 200 is electrically connected to the first pole of the second light emission control transistor T5 of the first pixel block 110. For example, the first data line 421 and the second power signal line 420 overlapping the second electrode 220 of the second color sub-pixel 200 each overlap the second electrode 112 of the first pixel block 110. For example, the second electrode 112 of the first pixel block 110 has two overlapping portions with the first data line 421 and the second power signal line 462, and the two overlapping portions are respectively located at both sides of a straight line that divides the effective light emitting area of the first pixel block 110 into two portions having equal areas and extends in the first direction. Therefore, the second electrode of the first pixel block has better symmetry and flatness in the Y direction, and is beneficial to preventing color cast.

For example, as shown in fig. 3A to 5C, the first power signal line 461 overlapping the second electrode 220 of the second-color sub-pixel 200 is electrically connected to the first pole of the second emission control transistor T5 of the second-color sub-pixel 200, and the second data line 422 overlapping the second electrode 220 of the second-color sub-pixel 200 is electrically connected to the second pole of the data write transistor T4 of the second-color sub-pixel. For example, the second electrode 122 of the second pixel block 120 has two overlapping portions with the second data line 422 and the first power signal line 461, and the two overlapping portions are respectively located at both sides of a straight line passing through the center of the second effective light emitting area 201 of the second pixel block 120 and extending in the X direction. Therefore, the second electrode of the second pixel block has better symmetry and flatness in the Y direction, and is beneficial to preventing color cast.

For example, as shown in fig. 3A to 5C, an edge of the main body electrode 1221 of the second pixel block 120 away from the auxiliary electrode 1223 overlaps the first connection portion 510 of the second color sub-pixel 200 in a direction perpendicular to the substrate.

For example, as shown in fig. 3A to 5C, the second electrode 320 of each third color sub-pixel 300 overlaps with the first data line 421, the first power supply signal line 461, the second data line 422 and the second power supply signal line 462 in a direction perpendicular to the substrate. For example, the effective light emitting region 301 of each third color sub-pixel 300 overlaps with the first data line 421, the first power signal line 461, the second data line 422 and the second power signal line 462 along a direction perpendicular to the substrate. For example, the first data line 421 and the second power signal line 462 are located at one side of a center line extending in the X direction of the effective light emitting area 301 of the third color sub-pixel 300, and the second data line 422 and the first power signal line 461 are located at the other side of the center line. For example, in the overlapping portion of the second electrode 320 and the first data line 421, the first power signal line 461, the second data line 422, and the second power signal line 462 of each third color sub-pixel 300 along the direction perpendicular to the substrate, the ratio of the overlapping area of the first power signal line 461 and the second data line 442 with the effective light emitting region 301 to the overlapping area of the second power signal line 462 and the first data line 421 with the effective light emitting region 301 is, for example, 0.8 to 1.2, for example, 0.9 to 1.1. The second electrode 320 of the third color sub-pixel 300 overlaps the source-drain metal layer at the two side regions (the regions where the data lines and the power signal lines overlap the second electrodes), and the overlapping portions are approximately symmetrically distributed, which is beneficial to reducing color shift.

For example, the second electrode 320 and the effective light emitting region 301 of the third color sub-pixel 300 overlap the second connection portion 520, and in the first data line 421, the first power signal line 461, and the portion where the second connection portion 520 overlaps the second electrode 320, the first power signal line 461 and the first data line 421 are located at both sides of the second connection portion 520, and a ratio of a minimum distance between edges where the second connection portion 520 and the first power signal line 461 are close to each other to a minimum distance between edges where the second connection portion 520 and the first data line 421 are close to each other is not greater than 2.5, for example, not greater than 2. For example, a straight line passing through the center of the effective light emitting region 301 of the third color sub-pixel 300 and extending in the X direction overlaps the second connection portion 520. In the embodiment of the present disclosure, the second connection portion of the third color sub-pixel is disposed in the middle area of the effective light emitting area, so that the height difference of the second electrode at the positions of the middle area and the two side areas (the areas where the data line and the power signal line overlap with the effective light emitting area) of the effective light emitting area can be reduced, which is beneficial to reducing color cast.

For example, as shown in fig. 3A to 5C, the second connection portion 520 of the third color sub-pixel 300 includes a second sub-connection portion 523 and a second pad block 524 connected to each other, and the second pad block 524 is located at a side of the second sub-connection portion 523 close to the center of the effective light emitting area 301 of the third color sub-pixel 300. For example, in the direction perpendicular to the substrate, the second pad block 524 overlaps the effective light emitting region 301, and the second sub-connection portion 523 does not overlap the effective light emitting region 301. For example, the second sub-connecting portion and the second cushion block are of an integral structure. The second connecting portion is schematically divided into the second sub-connecting portion and the second pad block, so that the position relationship between the second connecting portion and the second electrode of the third color sub-pixel and the position relationship between the second connecting portion and the effective light emitting area can be clearly shown.

For example, as shown in fig. 3A to 5C, the second electrode 320 of the third color sub-pixel 300 includes a main body electrode 321 and a connection electrode 322 connected to each other, and the shape of the main body electrode 321 of the third color sub-pixel 300 is the same as that of the effective light emitting area 301, for example, both of the main body electrode 321 and the connection electrode are hexagonal or elliptical. For example, the orthographic projection of the effective light emitting area of the third color sub-pixel on the substrate is positioned in the orthographic projection of the main body electrode on the substrate. For example, the body electrode 321 overlaps the second pad block 524, and the connection electrode 322 overlaps the second sub-connection 523 and is connected to the second sub-connection 523 in a direction perpendicular to the substrate base plate. For example, the body electrode 321 and the second sub-connecting portion 523 do not substantially overlap in a direction perpendicular to the substrate base plate.

For example, as shown in fig. 3A to 5C, the first connection portion 510 of the third color sub-pixel 300 overlaps the effective light emitting region 301 along a direction perpendicular to the substrate, and at least a portion of the first connection portion 510 and the second pad block 524 of the third color sub-pixel 300 are respectively located at two sides of a fourth straight line passing through the center of the effective light emitting region 301 and extending along the Y direction. In the embodiment of the disclosure, the effective light emitting area and the second electrode of the third color sub-pixel are overlapped with the first connecting portion, and the second pad is disposed at the edge of the effective light emitting area far away from the first connecting portion, so that the height difference of the middle area of the second electrode of the third color sub-pixel in the X direction can be reduced, and the color shift of the third color sub-pixel can be improved.

For example, as shown in fig. 3A to 5C, the second sub-connection portion 523 of the second connection portion 520 of the third color sub-pixel 300 has a rectangular shape, a side of the second sub-connection portion 523 adjacent to the first power signal line 461 is connected to the second electrode 320 through a via hole 3010 in a planarization layer, and a side of the second sub-connection portion 523 adjacent to the first data line 421 is connected to the second pole of the first light emission control transistor T6 through a via hole 3008 passing through the gate insulating layer, the first insulating layer, and the second insulating layer. The rectangular shape in the embodiments of the present disclosure includes a standard rectangular shape and an approximately rectangular shape, for example, the approximately rectangular shape may include a shape having a substantially rectangular overall outline such as a rounded rectangle.

For example, as shown in fig. 3A to 5C, the second pad 524 in the second connection part 520 of the third color sub-pixel 300 is rectangular in shape, and two sides of the second pad 524 extending in the X direction are respectively flush with two sides of the second sub-connection part 523 extending in the X direction, so that the second connection part of the third color sub-pixel is rectangular in shape. In the embodiment of the disclosure, the second pad block is added to reduce the height difference of the middle area of the second electrode of the third color sub-pixel in the X direction and the height difference of the second electrode in the Y direction, and the second connection part is rectangular in shape, so that the manufacturing is facilitated.

FIG. 7 is a schematic view of a partial cross-sectional structure of another display substrate. The display substrate shown in fig. 7 includes the film layer 010, the source-drain metal layer 011, the planarization layer 012, the anode 013, and the pixel defining layer 014 shown in fig. 6. As shown in fig. 7, the planarization layer 012 in the display substrate includes a via 018 so that the anode 013 can be electrically connected to the source-drain metal layer 011. The pixel defining layer 014 includes an opening 019 to expose a portion of the anode 013, and when a subsequent organic light emitting layer is formed in the opening 019, the organic light emitting layer is in contact with the anode 013 to form an effective light emitting region.

As shown in fig. 7, the via 018 is located outside the effective light emitting area, and since the anode 013 located around the via 018 is inclined, a certain distance should be set between the effective light emitting area and the via 018, so as to ensure flatness of the anode 013 in the effective light emitting area, thereby preventing color cast of the display substrate.

Fig. 8 is a schematic view of a pixel arrangement structure in a display substrate. As shown in fig. 8, the display substrate includes a data line 042 extending along the X direction, the display substrate further includes a red subpixel 021, a green subpixel pair 022, and a blue subpixel 023, and the effective light emitting areas of the red subpixel 021 and the blue subpixel 023 extend along the Y direction. For example, each sub-pixel includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the light-emitting element includes an anode, a light-emitting layer, and a cathode sequentially stacked in a direction away from the substrate, and the anode is connected to the connection portion 031 through the via 0310 to be connected to a thin film transistor in the pixel circuit. For example, the via holes 0310 corresponding to the red, green, and blue subpixels 021, 022, and 023 are aligned in the Y direction. For example, the anode 0211 of the red subpixel 021 is connected to the connecting portion 031 through the via 0310, and a long side of the effective light emitting area 0211 of the red subpixel 021, which is close to the via 0310, is provided with a notch to avoid the via 0310, and an appropriate distance (preset distance) between the effective light emitting area 0211 and the via 0310 is ensured, for example, 3 μm. Similarly, the long edge of the effective light emitting area of the blue sub-pixel 023 near the via 0310 also needs to be provided with a notch to avoid the via 0310, and to ensure the preset distance between the effective light emitting area and the via 0310. The predetermined distance refers to a minimum distance (e.g., 3 μm) between the edge of the effective light-emitting area and the edge of the via hole, so as to ensure that the via hole does not affect the light-emitting direction of the edge of the effective light-emitting area.

For example, the minimum distance between the edge of the third via of the first pixel block and the edge of the effective light emitting areas of the second color sub-pixel and the fourth color sub-pixel is approximately equal and is greater than 3 micrometers. For example, the minimum distance between the fourth via of the second pixel block and the edges of the effective light emitting areas of the second color sub-pixel and the fourth color sub-pixel is more than 3 micrometers.

For example, an orthogonal projection of the second electrode of the second color sub-pixel on the substrate overlaps with an orthogonal projection of the reset power supply signal line on the substrate.

In another example of the embodiment of the present disclosure, as shown in fig. 4 to 5F, the second electrode 220 of the second color sub-pixel 200 is connected to the second connection portion 520 through a first via 3011 penetrating through the planarization layer, and the second electrode 320 of the third color sub-pixel 300 is connected to the second connection portion 520 through a second via 3012 penetrating through the planarization layer. The minimum distance between the orthographic projection of the effective light emitting area 201 of the second color sub-pixel 200 on a straight line along the X direction (the extending direction of the data line 420) and the orthographic projection of the effective light emitting area 301 of the third color sub-pixel 300 on the straight line is smaller than the sum of the sizes of the first via and the projection of the preset pitch between the edge of the first via and the edge of the effective light emitting area on the straight line. The first via 3011 is located on a side of the effective emitting region 201 of the second color sub-pixel 200 close to the effective emitting region 301 of the third color sub-pixel 300 in the X direction, the second via 3012 is located on a side of the effective emitting region 301 of the third color sub-pixel 300 close to the effective emitting region 201 of the second color sub-pixel 200 in the X direction, and a first connection line 3101 connecting the first via 3011 and the second via 3012 is not parallel to the Y direction. For example, orthographic projections of the first via 3011, the fourth via 3014 and the third via 3013 on the substrate overlap with orthographic projections of the light emission control signal line 450 on the substrate. For example, an orthogonal projection of the second via 3012 on the substrate base does not overlap with an orthogonal projection of the light emission control signal line 450 on the substrate base. The first connecting line is a straight line.

For example, a first connection line 3101 connecting the first via 3011 and the second via 3012 may refer to a connection line of a center of the first via and a center of the second via; or a connection line between a point of the first via closest to the effective light emitting area of the second color sub-pixel and a point of the second via farthest from the effective light emitting area of the third color sub-pixel; the connection line of the point of the first via hole which is farthest away from the effective light emitting area of the second color sub-pixel and the point of the second via hole which is closest to the effective light emitting area of the third color sub-pixel can also be referred to.

For example, the second electrode of the second color sub-pixel and the second electrode of the third color sub-pixel do not overlap in the second direction.

In the embodiment of the present disclosure, a distance between the effective light emitting area of the second color sub-pixel and the effective light emitting area of the third color sub-pixel in the X direction is smaller, for example, smaller than a sum of sizes of the first via and the preset pitch, if the first via is disposed in the pitch between the effective light emitting area of the second color sub-pixel and the effective light emitting area of the third color sub-pixel in the X direction, a collision between positions of the first via and the effective light emitting area of the second color sub-pixel may occur, and light emission of the second color sub-pixel is affected. In the embodiment of the disclosure, the positions of the vias (e.g., at least one of the first vias and the second vias) in the planarization layer are adjusted according to the positions of the effective light emitting areas of the second color sub-pixel and the third color sub-pixel, for example, a connection line of the first via and the second via corresponding to the second color sub-pixel and the third color sub-pixel is not parallel to the extending direction of the scanning signal line, so that the planarity of the second electrodes of the second color sub-pixel and the third color sub-pixel can be ensured, the uniformity of the light emitting intensity of the effective light emitting areas in each direction can be ensured, and the color cast can be effectively improved.

For example, as shown in fig. 4 to 5C, an included angle between the first connection line 3101 and the Y direction is 5 ° to 15 °, and the embodiments of the present disclosure can reduce the probability of color cast of the second color sub-pixel and the third color sub-pixel by adjusting the positions of the first via hole and the second via hole.

For example, as shown in fig. 4 to 5C, the second via 3012 is located on a side of the second straight line 3102 passing through the first via 3011 and extending along the Y direction, close to the effective light emitting area 201 of the second color sub-pixel 200. For example, an orthogonal projection of the first via 3011 on a straight line extending in the X direction does not overlap an orthogonal projection of the second via 3012 on the straight line. In the embodiment of the present disclosure, the distance between the effective light emitting area of the second color sub-pixel and the first via hole and the distance between the effective light emitting area of the third color sub-pixel and the second via hole are set to be larger, so that it can be ensured that the via holes do not affect the flatness of the second electrode located in the effective light emitting area, so that the luminous intensities of the effective light emitting areas in all directions are consistent, and the color cast is effectively improved.

For example, as shown in fig. 4 to 5C, in the second color sub-pixel 200, the second connection part 520 is electrically connected to the second pole of the first light emission controlling transistor T6 through the first connection hole 3021 penetrating the gate insulating layer, the first insulating layer, and the second insulating layer; in the third color sub-pixel 300, the second connection portion 520 is electrically connected to the second pole of the first light emission controlling transistor T6 through a second connection hole 3022 passing through the gate insulating layer, the first insulating layer and the second insulating layer, and a second connection line 3200 connecting the first connection hole 3021 and the second connection hole 3022 is parallel to the Y direction. For example, the second connection line 3200 connecting the first connection hole 3021 and the second connection hole 3022 may refer to a connection line of the center of the first connection hole and the center of the second connection hole; or a connection line between a point of the first connection hole closest to the effective light emitting area of the second color sub-pixel and a point of the second connection hole farthest from the effective light emitting area of the third color sub-pixel; it can also refer to the connection line between the point of the first connection hole farthest from the effective light emitting area of the second color sub-pixel and the point of the second connection hole closest to the effective light emitting area of the third color sub-pixel.

For example, as shown in fig. 4 to 5C, the effective light emitting area 201 of the second color sub-pixel 200 includes a first long side 1011 and a second long side 1012 extending along the Y direction, the second long side 1012 is located at a side of the first long side 1011 away from the first via 3011, and an extension line of the first long side 1011 overlaps with the second via 3012 along a third direction perpendicular to the substrate. For example, an orthogonal projection of the second via hole 3012 on a straight line extending in the X direction overlaps with an orthogonal projection of the second connection hole 3022 on the straight line. In the embodiment of the present disclosure, when the position of the second via hole is adjusted, the position of the second via hole penetrating through the planarization layer is not adjusted in the X direction with respect to the position of the second connection hole penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer in consideration of the position of the second connection hole, so that the influence on the entire pixel circuit structure can be reduced.

For example, as shown in fig. 4 to 5C, the effective light emitting area 301 of the third color sub-pixel 300 includes a third long side 1013 and a fourth long side 1014 extending along the Y direction, the fourth long side 1014 is located at a side of the third long side 1013 away from the second via 3012, and an extension line of the fourth long side 1014 overlaps with the first via 3011 along a direction perpendicular to the substrate. For example, in the direction perpendicular to the substrate, the first connection hole 3021 overlaps the effective light emitting region 201 of the second color sub-pixel 200, the first via 3011 is farther from the effective light emitting region 201 of the second color sub-pixel 200 than the first connection hole 3021, and the orthographic projection of the first via 3011 on a straight line extending in the X direction does not overlap the orthographic projection of the first connection hole 3021 on the straight line. In the embodiment of the disclosure, when adjusting the position of the first via hole, not only the position of the first via hole penetrating through the planarization layer is slightly adjusted in the X direction relative to the position of the first connection hole penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer, but also the distance between the first via hole and the effective light emitting area of the second color sub-pixel is ensured, so as to prevent the influence on the uniformity of the light emitting intensity of the effective light emitting area in each direction.

For example, as shown in fig. 4 to 5C, the shortest distance between the first long side 1011 of the effective light emitting region 201 of the second color sub-pixel 200 and the orthographic projection of the first via 3011 on the substrate is a first distance, the shortest distance between the third long side 1013 of the effective light emitting region 301 of the third color sub-pixel 300 and the orthographic projection of the second via 3012 on the substrate is a second distance, and the ratio of the first distance to the second distance is 0.8 to 1.2, for example, 0.9 to 1.1. For example, the first distance and the second distance are substantially equal. For example, the first distance and the second distance are each greater than 3 microns. The above-mentioned "shortest distance between the first long side 1011 and the orthographic projection of the first via 3011 on the substrate" refers to a distance between a point of the orthographic projection of the first via, which is closest to the orthographic projection of the first long side, and the orthographic projection of the first long side. The above-mentioned "shortest distance between the third long side 1013 and the orthogonal projection of the second via 3012 on the substrate" refers to a distance between the point of the orthogonal projection of the second via closest to the third long side and the orthogonal projection of the third long side. In the embodiment of the disclosure, the distance between the via hole formed in the planarization layer and the edge of the effective light emitting area of the sub-pixel is set to be larger, so that the via hole can be prevented from affecting the planarization of the second electrode in the effective light emitting area, thereby ensuring the uniformity of the light emitting intensity in each direction and effectively improving the color cast.

For example, as shown in fig. 4 to 5C, the first long side 1011 of the effective emitting region 201 of the second color sub-pixel 200 is a straight side, and the third long side 1013 of the effective emitting region 301 of the third color sub-pixel 300 is a straight side. In the embodiment of the disclosure, the positions of the first via hole and the second via hole are adjusted, so that the effective light emitting area is not affected by the positions of the via holes, and meanwhile, the edge of the effective light emitting area is prevented from being designed into a notched shape for avoiding the via holes, so that the design of an opening of a special-shaped pixel limiting layer is avoided, and the problems in the process of manufacturing the pixel structure can be reduced.

For example, as shown in fig. 4 to 5C, the second electrode 112 of the first pixel block 110 in the first color sub-pixel pair 100 is connected to the second connection portion 520 through a third via 3013 penetrating through the planarization layer, the second electrode 122 of the second pixel block 120 in the first color sub-pixel pair 100 is connected to the second connection portion 520 through a fourth via 3014 penetrating through the planarization layer, and a first connection line 3103 connecting the third via 3013 and the fourth via 3014 is substantially parallel to the Y direction. According to the embodiment of the disclosure, the third via hole and the fourth via hole are arranged on a straight line extending along the Y direction, so that the distance between the via hole and the corresponding effective light emitting area is ensured, and the process manufacturing is facilitated.

For example, a first connection line 3103 connecting the third via 3013 and the fourth via 3014 may refer to a connection line of a center of the third via and a center of the fourth via; the connecting line between the point of the third via hole closest to the first effective light emitting area and the point of the fourth via hole closest to the second effective light emitting area can also be referred to; it may also refer to a connection line between a point of the third via hole farthest from the first effective light emitting area and a point of the fourth via hole farthest from the second effective light emitting area.

For example, as shown in fig. 4 to 5C, the straight line of the first connection line 3103 passes through the first via 3011 and does not pass through the second via 3012. In the embodiment of the present disclosure, the first via hole connected to the second electrode of the second color sub-pixel, the third via hole connected to the second electrode of the first color sub-pixel pair, and the fourth via hole are substantially located on a straight line parallel to the scan signal line, so that the distance between the first via hole and the corresponding effective light emitting area is greater than 3 micrometers, and the manufacturing is also convenient.

For example, as shown in fig. 4 to 5C, along a third direction perpendicular to the substrate, a line along which the third long side 1013 of the effective light emitting region 301 of the second color sub-pixel 300 is located overlaps both the third via 3013 and the fourth via 3014.

For example, as shown in fig. 4 to 5C, a third via 3013 or a fourth via 3014 is disposed between the first via 3011 and the second via 3012 along the Y direction. That is, the third via hole and the fourth via hole are disposed at both sides of the first via hole in the Y direction, or the third via hole and the fourth via hole are disposed at both sides of the second via hole in the Y direction.

For example, as shown in fig. 4 to 5C, in the first sub-pixel block 110, the second connection part 520 is electrically connected to the second pole of the first light emitting control transistor T6 through a third connection hole 3023 penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer; in the second sub-pixel block 120, the second connection portion 520 is electrically connected to the second pole of the first light emission controlling transistor T6 through a fourth connection hole 3024 penetrating through the gate insulating layer, the first insulating layer, and the second insulating layer, and a fourth connection line 3400 connecting the third connection hole 3023 and the fourth connection hole 3024 substantially coincides with the second connection line 3200.

For example, a fourth connection line 3400 connecting the third connection hole 3023 and the fourth connection hole 3024 may refer to a connection line of the center of the third connection hole and the center of the fourth connection hole; the connecting line between the point of the third connecting hole closest to the first effective light emitting area and the point of the fourth connecting hole closest to the second effective light emitting area can also be referred to; the connecting line of the point of the third connecting hole farthest from the first effective light-emitting area and the point of the fourth connecting hole farthest from the second effective light-emitting area can also be referred to.

In the embodiment of the present disclosure, the first direction represents an extending direction of the data line, the second direction represents an extending direction of the scan signal line, and names of the two directions may be interchanged; in the embodiment of the present disclosure, the first connection portion denotes a connection portion connecting the second pole of the threshold compensation transistor and the gate electrode of the driving transistor, the second connection portion denotes a connection portion connecting the second pole of the first light emission control transistor and the second electrode of the light emitting element, and the third connection portion denotes a connection portion connecting the first pole of the first reset transistor and the reset power signal line, and the names of the three connection portions may be interchanged.

As shown in fig. 3A to 5J, the display substrate includes a substrate 1 and a plurality of sub-pixels 10 on the substrate 1. Each sub-pixel 10 includes a light emitting element 11 and a pixel circuit 12, the light emitting element 11 includes a first electrode, a light emitting layer, and a second electrode stacked in this order, the second electrode is located between the light emitting layer of the substrate 1 and the substrate 1, the pixel circuit includes a driving transistor T3 and a storage capacitor C located between the second electrode and the substrate 1, and the gate of the driving transistor T3 is multiplexed as one plate of the storage capacitor C. The plurality of sub-pixels 10 comprises at least one first color sub-pixel pair 100 and a plurality of other color sub-pixels, each first color sub-pixel pair 100 comprises a first pixel block 110 and a second pixel block 120, and the minimum distance between the first pixel block 110 and the second pixel block 120 in each first color sub-pixel pair 100 is not greater than the minimum distance between two same color sub-pixels in the plurality of other color sub-pixels of the substrate 1; in the same pair 100 of first color sub-pixels, the overlapping condition of the orthographic projection of the second electrode of the light-emitting element 11 of the first pixel block 110 and the gate of the driving transistor T3 of the first pixel block 110 on the substrate 1 is the same as the overlapping condition of the orthographic projection of the second electrode of the light-emitting element 11 of the second pixel block 120 and the gate of the driving transistor T3 of the second pixel block 120 on the substrate 1, so that the gate nodes of the driving transistors in the two first color sub-pixels can have balanced coverage, which is beneficial to balancing the electrical environment and the light-emitting effect of the two first color sub-pixels.

The above-mentioned "overlapping condition of the orthographic projection" includes a condition that the orthographic projection of the second electrode of the light emitting element overlaps or does not overlap with the orthographic projection of the gate electrode of the driving transistor, and the same two "overlapping condition of the orthographic projection" may mean that in the first pixel block and the second pixel block, both the orthographic projection of the second electrode of the light emitting element and the orthographic projection of the gate electrode of the driving transistor overlap, or neither of the orthographic projection of the second electrode of the light emitting element and the orthographic projection of the gate electrode of the driving transistor overlap.

For example, as shown in fig. 3A to 5J, the first pixel block 110 and the second pixel block 120 included in the same first color sub-pixel pair 100 are arranged along the row direction, the other color sub-pixels include the second color sub-pixel 200 and the third color sub-pixel 300, and at least one of the second color sub-pixel 200 and the third color sub-pixel 300 and the first color sub-pixel pair 100 are located on adjacent rows. The display substrate further comprises a planarization layer 6 between the pixel circuitry and the second electrode of the light emitting element 11. The planarization layer 6 includes a plurality of vias 3010 penetrating therethrough, the second electrode of the light emitting element in each sub-pixel is electrically connected to the corresponding pixel circuit through the via, the vias 3010 corresponding to the sub-pixels in adjacent rows are not on a straight line, and an orthogonal projection of a via corresponding to one of two sub-pixels respectively located in adjacent rows on a straight line extending in the column direction overlaps an orthogonal projection of an effective light emitting region of the other of the two sub-pixels on a straight line. Through setting the via hole positions of the sub-pixels in the adjacent rows, the overlapping of the via hole of a certain sub-pixel and the effective light emitting area of the sub-pixel can be avoided, the flatness of the second electrode of the sub-pixel is prevented from being influenced, and the light emitting direction is further influenced.

For example, as shown in fig. 3A to 5J, the second electrode of the light emitting element of at least one third color sub-pixel 300 overlaps with two data lines 420 and two power signal lines 460 in a direction perpendicular to the substrate base plate 1, which is advantageous for improving the flatness of the second electrode of the third color sub-pixel.

For example, as shown in fig. 3A to 5J, in a direction perpendicular to the substrate 1, the effective light emitting area of the light emitting element of at least one third color sub-pixel 300 overlaps with two data lines 420, which is beneficial to reducing the probability of color cast of the third color sub-pixel.

For example, as shown in fig. 3A to 5J, the second electrode of the light emitting element of at least one second color sub-pixel 200 overlaps two data lines 420 along a direction perpendicular to the substrate 1, which is beneficial to improving the flatness of the second electrode of the second color sub-pixel.

For example, as shown in fig. 3A to 5J, the plurality of sub-pixels 10 include a plurality of first color sub-pixel pairs 100 arranged along the second direction, the plurality of first color sub-pixel pairs 100 include a plurality of first pixel blocks 110 and a plurality of second pixel blocks 120 alternately arranged along the second direction of the substrate 1, and two distances between the effective light emitting areas of the first pixel blocks 110 and the effective light emitting areas of the two second pixel blocks 120 located at both sides of the effective light emitting area of the first pixel block 110 in the second direction are different; the display substrate further comprises a data line extending along the first direction, and an included angle between the second direction and the first direction is in a range of 80-100 degrees.

For example, as shown in fig. 3A to 5J, the pixel circuits of the plurality of sub-pixels include pixel circuit rows arranged in the column direction, each pixel circuit row includes pixel circuits arranged in the row direction, and centers of the effective light emitting areas of a part of the second color sub-pixels 200 and a part of the third color sub-pixels 300 connected to the pixel circuits in the same pixel circuit row are not on one straight line. The two distances between the effective light emitting areas of the first pixel block and the effective light emitting areas of the two second pixel blocks located on two sides of the effective light emitting area of the first pixel block in the second direction are different, and the centers of the effective light emitting areas of the partial second color sub-pixels and the partial third color sub-pixels connected with the pixel circuits in the same pixel circuit row are not in the same straight line, so that the uniformity of the sub-pixel light emission in the display substrate is improved.

For example, as shown in fig. 3A to 5J, the pixel circuit further includes a threshold compensation transistor T2, a first pole of the threshold compensation transistor T2 is electrically connected to the first pole of the driving transistor T3, a second pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, the threshold compensation transistor T2 includes a first gate T2-g1 and a second gate T2-g2, and the second electrode of the light emitting element 11 of the first pixel block 110 shields one of the first gate T2-g1 and the second gate T2-g2, which is beneficial to improve the stability of the threshold compensation transistor voltage.

For example, as shown in fig. 3A to 5J, the second electrode 320 of the light emitting element of the third color sub-pixel 300 includes a body electrode 321 and a connection electrode 322, the connection electrode 322 is configured to be electrically connected to the pixel circuit, the effective light emitting area of the third color sub-pixel 300 overlaps the body electrode 321 in a direction perpendicular to the substrate 1, and the body electrode 321 of the third color sub-pixel 300 overlaps the threshold compensation transistor T2 including at least one of the first gate T2-g1 and the second gate T2-g2, which is beneficial to improving the stability of the threshold compensation transistor voltage.

For example, as shown in fig. 3A to 5J, the second electrode of the light emitting element of the at least one color sub-pixel includes a body electrode and a connection electrode configured to be electrically connected to the pixel circuit, and the effective light emitting area of the at least one color sub-pixel overlaps with the body electrode in a direction perpendicular to the substrate 1; the second electrode of the light emitting element of the at least one color sub-pixel further includes an auxiliary electrode covering a portion of the active layer between the orthographic projections of the first and second gate electrodes T2-g1 and T2-g2 on the active layer, and the threshold compensation transistor T2.

For example, as shown in fig. 3A to 5J, the pixel circuit further includes a first light emission controlling transistor T6, a first connection portion 510, and a second connection portion 520, the second pole of the threshold compensating transistor T2 is electrically connected to the gate of the driving transistor T3 through the first connection portion 510, the first pole of the first light emission controlling transistor T6 is electrically connected to the first pole of the driving transistor T3, and the second pole of the first light emission controlling transistor T6 is electrically connected to the second electrode of the light emitting element through the second connection portion 520; the pixel circuits of the plurality of sub-pixels include pixel circuit rows arranged in the column direction, each pixel circuit row includes a plurality of pixel circuits arranged in the row direction, and adjacent two second connection portions 520 in the same pixel circuit row are different in shape and size.

For example, as shown in fig. 3A to 5J, the display substrate further includes: the light emission control signal line 450 extends in the row direction and is disposed at the same level as the gate of the driving transistor T3. The second connection part 520 overlaps the light emission control signal line 450 without overlapping the gate of the driving transistor T3, thereby preventing the second connection part from overlapping the gate of the driving transistor (i.e., one plate of the capacitor) to increase the load.

For example, as shown in fig. 3A to 5J, in the first color sub-pixel pair 100, the second electrode of each light emitting element includes a body electrode and a connection electrode configured to be electrically connected to the pixel circuit, and in a direction perpendicular to the substrate 1, the effective light emitting area 101 in the first pixel block 110 overlaps with the body electrode 1121, and the effective light emitting area 102 in the second pixel block 120 overlaps with the body electrode 1221; the second electrodes of the light emitting elements of the first pixel block 110 and the second pixel block 120 are different in shape and size except for the main body electrode.

For example, as shown in fig. 3A to 5J, the second electrodes of the light emitting elements of the first pixel block 110 and the second pixel block 120 are different in shape and size except for the main body electrode and the connection electrode.

Another embodiment of the present disclosure provides a display device, which includes any one of the display substrates described above.

For example, the display device provided by the embodiment of the present disclosure may be an organic light emitting diode display device.

For example, in the display device provided by the embodiment of the disclosure, in a first color sub-pixel pair, for example, in two first color sub-pixels included in a green color sub-pixel pair, a ratio of overlapping areas of the second electrodes of the two light emitting elements and the corresponding two first connection portions is 0.8 to 1.2, for example, 0.9 to 1.1, and a load difference of gate nodes of driving transistors in the two first color sub-pixels can be reduced, so that a luminance difference of the two first color sub-pixels is reduced to improve display characteristics of the display substrate.

For example, in the display device provided by the embodiment of the present disclosure, by disposing the auxiliary electrode covering one of the two gates of the threshold compensation transistor in the first color sub-pixel pair, for example, in one green sub-pixel of the green sub-pixel pair, external light can be prevented from being directly incident on the channel region of the threshold compensation transistor, and characteristic shift of the threshold compensation transistor caused by light irradiation during display on the display substrate can be avoided, thereby preventing influence on writing of the gate potential of the driving transistor.

For example, the display device provided by the embodiment of the present disclosure sets the distances between the second connection portion of the second color sub-pixel, for example, the red sub-pixel, and the adjacent data line and power signal line to be substantially equal, so that the height difference between the middle region (the region not overlapping the data line and the power signal line) and the two side regions (the region overlapping the data line and the power signal line) of the second electrode of the second color sub-pixel can be reduced, the flatness of the second electrode of the second color sub-pixel can be improved, and the color shift can be improved.

For example, in the display device provided by the embodiment of the disclosure, the effective light emitting region and the second electrode of the third color sub-pixel, for example, the blue sub-pixel, overlap with the first connection portion, and the second pad is disposed at the edge of the effective light emitting region away from the first connection portion, so that the height difference of the middle region of the second electrode of the third color sub-pixel in the extending direction of the scanning signal line and the extending direction of the data line can be reduced, which is beneficial to improving the color shift of the third color sub-pixel.

For example, in the display device provided by the embodiment of the present disclosure, the position of the via hole (for example, at least one of the first via hole and the second via hole) in the planarization layer is adjusted according to the positions of the effective light emitting areas of the second color sub-pixel and the third color sub-pixel, for example, a connection line of the first via hole and the second via hole respectively corresponding to the second color sub-pixel and the third color sub-pixel is not parallel to the extending direction of the scanning signal line, so that the planarity of the second electrodes of the second color sub-pixel and the third color sub-pixel can be ensured, the uniformity of the light emitting intensity of the effective light emitting areas in all directions is ensured, and the color cast is effectively improved.

The following points need to be explained:

(1) in the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to general designs.

(2) Features of the same embodiment of the disclosure and of different embodiments may be combined with each other without conflict.

The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.

Claims (20)

1. A display substrate, comprising:

a substrate base plate;

the pixel circuit comprises a driving transistor and a storage capacitor, wherein the driving transistor and the storage capacitor are arranged between the second electrode and the substrate base plate, and the grid electrode of the driving transistor is multiplexed as one polar plate of the storage capacitor;

wherein the plurality of sub-pixels comprises at least one first color sub-pixel pair and a plurality of other color sub-pixels, each first color sub-pixel pair comprises a first pixel block and a second pixel block, and the minimum distance between the first pixel block and the second pixel block in each first color sub-pixel pair is not greater than the minimum distance between two same color sub-pixels in the plurality of other color sub-pixels;

in the same first color sub-pixel pair, the overlapping condition of the orthographic projection of the second electrode of the light-emitting element of the first pixel block and the gate electrode of the driving transistor of the first pixel block on the substrate is the same as the overlapping condition of the orthographic projection of the second electrode of the light-emitting element of the second pixel block and the gate electrode of the driving transistor of the second pixel block on the substrate.

2. The display substrate of claim 1, wherein the first and second pixel blocks of a same first color sub-pixel pair are arranged in a row direction, the other color sub-pixels comprise second and third color sub-pixels, at least one of the second and third color sub-pixels is located in an adjacent row to the first color sub-pixel pair,

the display substrate further includes a planarization layer between the pixel circuit and the second electrode of the light emitting element,

wherein the planarization layer includes a plurality of via holes therethrough, the second electrode of the light emitting element in each of the sub-pixels being electrically connected to the corresponding pixel circuit through the via holes,

the via holes corresponding to the sub-pixels positioned in the adjacent rows are not positioned on a straight line, and the orthographic projection of the via hole corresponding to one of the two sub-pixels respectively positioned in the adjacent rows on the straight line extending along the column direction is overlapped with the orthographic projection of the effective light emitting area of the other one of the two sub-pixels on the straight line.

3. The display substrate of claim 1, further comprising:

a plurality of data lines extending in a first direction;

a plurality of power signal lines extending in the first direction,

wherein the other color sub-pixels include a plurality of second color sub-pixels and a plurality of third color sub-pixels, and the second electrode of the light emitting element of at least one third color sub-pixel overlaps with two data lines and two power supply signal lines in a direction perpendicular to the substrate.

4. The display substrate according to claim 3, wherein an effective light emitting area of the light emitting element of the at least one third color sub-pixel overlaps with the two data lines in a direction perpendicular to the substrate.

5. The display substrate of claim 1, further comprising:

a plurality of data lines extending in a first direction;

a plurality of power signal lines extending in the first direction,

and the other color sub-pixels comprise a plurality of second color sub-pixels and a plurality of third color sub-pixels, and the second electrode of the light-emitting element of at least one second color sub-pixel is overlapped with the two data lines along the direction vertical to the substrate.

6. The display substrate according to claim 1, wherein the plurality of sub-pixels include a plurality of pairs of first color sub-pixels arranged in a second direction, the plurality of pairs of first color sub-pixels including a plurality of first pixel blocks and a plurality of second pixel blocks alternately arranged in the second direction, two distances between the effective light emitting areas of the first pixel blocks and the effective light emitting areas of the two second pixel blocks located on both sides of the effective light emitting area of the first pixel block in the second direction being different;

the display substrate further comprises a data line extending along a first direction, and an included angle between the second direction and the first direction is in a range of 80-100 degrees.

7. The display substrate of claim 6, wherein the other color sub-pixels further comprise a plurality of second color sub-pixels and a plurality of third color sub-pixels,

the pixel circuits of the plurality of sub-pixels include pixel circuit rows arranged in a column direction, each pixel circuit row includes pixel circuits arranged in a row direction, and centers of effective light emitting areas of a part of the second color sub-pixels and a part of the third color sub-pixels connected to the pixel circuits in the same pixel circuit row are not on a straight line.

8. The display substrate of claim 1, wherein the pixel circuit further comprises a threshold compensation transistor having a first pole electrically connected to the first pole of the driving transistor and a second pole electrically connected to the gate of the driving transistor, the threshold compensation transistor comprising a first gate and a second gate, the second electrode of the light emitting element of the first pixel block obscuring one of the first gate and the second gate.

9. The display substrate according to claim 8, wherein the other-color sub-pixels include a plurality of second-color sub-pixels and a plurality of third-color sub-pixels, the second electrode of the light-emitting element of the third-color sub-pixel includes a body electrode and a connection electrode, the connection electrode is configured to be electrically connected to the pixel circuit, an effective light-emitting area of the third-color sub-pixel overlaps the body electrode in a direction perpendicular to the substrate, and the body electrode of the third-color sub-pixel overlaps at least one of the first gate electrode and the second gate electrode.

10. The display substrate according to claim 8, wherein the second electrode of the light emitting element of at least one color sub-pixel comprises a body electrode and a connection electrode configured to be electrically connected to the pixel circuit, an effective light emitting area of the at least one color sub-pixel overlapping the body electrode in a direction perpendicular to the substrate;

the second electrode of the light emitting element of the at least one color sub-pixel further comprises an auxiliary electrode covering a portion of the active layer between orthographic projections of the first and second gate electrodes on the active layer.

11. The display substrate according to claim 1, wherein the pixel circuit further comprises a threshold compensation transistor, a first emission control transistor, a first connection portion, and a second connection portion between the second electrode of the light emitting element and the substrate, a first pole of the threshold compensation transistor being electrically connected to the first pole of the driving transistor, a second pole of the threshold compensation transistor being electrically connected to the gate of the driving transistor through the first connection portion, a first pole of the first emission control transistor being electrically connected to the first pole of the driving transistor, a second pole of the first emission control transistor being electrically connected to the second electrode of the light emitting element through the second connection portion;

the pixel circuits of the sub-pixels comprise pixel circuit rows arranged along the column direction, each pixel circuit row comprises a plurality of pixel circuits arranged along the row direction, and two adjacent second connecting parts in the same pixel circuit row are different in shape and size.

12. The display substrate of claim 11, further comprising:

a light emission control signal line extending in the row direction and disposed at the same layer as the gate electrode of the driving transistor,

wherein the second connection portion overlaps the light emission control signal line and does not overlap the gate electrode of the driving transistor.

13. The display substrate according to claim 1, wherein in the first color sub-pixel pair, the second electrode of each light emitting element includes a body electrode and a connection electrode configured to be electrically connected to the pixel circuit, and in a direction perpendicular to the substrate, the effective light emitting area in the first pixel block overlaps with the body electrode, and the effective light emitting area in the second pixel block overlaps with the body electrode;

the first pixel block and the second pixel block have different shapes and sizes of the second electrodes of the light emitting elements except for the main body electrode.

14. The display substrate according to claim 13, wherein portions of the second electrodes of the light emitting elements of the first pixel block and the second pixel block other than the main body electrode and the connection electrode are different in shape and size.

15. A display substrate, comprising:

a substrate base plate;

a plurality of sub-pixels located on the substrate, each sub-pixel including a light emitting element and a pixel circuit, the light emitting element including a first electrode, a light emitting layer, and a second electrode sequentially stacked, the second electrode being located between the light emitting layer and the substrate, the pixel circuit including a first connection portion located between the second electrode and the substrate, a driving transistor, and a threshold compensation transistor, the first connection portion extending in a first direction, a first pole of the threshold compensation transistor being electrically connected to a first pole of the driving transistor, a second pole of the threshold compensation transistor being electrically connected to a gate of the driving transistor through the first connection portion,

the plurality of sub-pixels comprise at least one first color sub-pixel pair and a plurality of other color sub-pixels, each first color sub-pixel pair comprises a first pixel block and a second pixel block which are arranged along a second direction, the minimum distance between the first pixel block and the second pixel block in each first color sub-pixel pair is not greater than the minimum distance between two same color sub-pixels in the plurality of other color sub-pixels, and the included angle between the second direction and the first direction is within the range of 80-100 degrees;

in the first pixel block, an overlapping area of an orthographic projection of the second electrode on the substrate base plate and an orthographic projection of the first connecting portion on the substrate base plate is a first overlapping area, in the second pixel block, an overlapping area of an orthographic projection of the second electrode on the substrate base plate and an orthographic projection of the first connecting portion on the substrate base plate is a second overlapping area, and a ratio of the first overlapping area to the second overlapping area is 0.8-1.2.

16. The display substrate according to claim 15, wherein in the first pixel block, the second electrode of the light emitting element covers 60 to 90% of an area of the first connection portion; in the second pixel block, the second electrode of the light emitting element covers 60-90% of the area of the first connection portion.

17. The display substrate according to claim 15, wherein the first pixel block comprises a first effective light emitting region, the second pixel block comprises a second effective light emitting region, a minimum distance between an orthographic projection of the first connecting portion on a straight line extending along the second direction and an orthographic projection of the first effective light emitting region on the straight line in the first pixel block is a first distance, or an orthographic projection of the first connecting portion on a straight line extending along the second direction overlaps with an orthographic projection of the first effective light emitting region on the straight line; in the second pixel block, a minimum distance between an orthographic projection of the first connecting part on the straight line and an orthographic projection of the second effective light emitting area on the straight line is a second distance, and the first distance is smaller than the second distance;

in the first pixel block, the grid electrode of the threshold compensation transistor is positioned on one side of the first connecting part far away from the first effective luminous area; in the second pixel block, the gate of the threshold compensation transistor is located on one side of the first connection portion close to the second effective light emitting area.

18. The display substrate according to claim 17, wherein the second electrode of each of the sub-pixels includes a main body electrode and a connection electrode, the shape of the main body electrode is substantially the same as the shape of the first effective light emitting area in the first pixel block, an orthogonal projection of the first effective light emitting area on the substrate is located within an orthogonal projection of the main body electrode on the substrate, and the first effective light emitting area overlaps the first connection portion; in the second pixel block, the shape of the main body electrode is substantially the same as that of the second effective light emitting area, the orthographic projection of the second effective light emitting area on the substrate is positioned in the orthographic projection of the main body electrode on the substrate, and the second effective light emitting area is not overlapped with the first connecting part.

19. The display substrate of claim 18, wherein the second electrode further comprises an auxiliary electrode connecting the main body electrode and the connection electrode in the first color sub-pixel pair, the connection electrode extending in the first direction,

in the first pixel block, the auxiliary electrode is located on one side of the main body electrode, which is far away from the second effective light emitting area, and in the second pixel block, the auxiliary electrode is located on one side of the main body electrode, which is far away from the first effective light emitting area.

20. A display device comprising the display substrate of claims 1-19.

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