CN114899198A

CN114899198A - Array substrate, display panel and display device

Info

Publication number: CN114899198A
Application number: CN202210727178.0A
Authority: CN
Inventors: 吴忠厚; 周思思; 张露; 张金方; 朱修剑
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd
Priority date: 2022-06-24
Filing date: 2022-06-24
Publication date: 2022-08-12

Abstract

The application discloses array substrate, display panel and display device. The array substrate comprises a substrate, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially far away from the substrate, wherein insulating layers are arranged among adjacent film layers in the first metal layer, the second metal layer, the third metal layer and the fourth metal layer; the array substrate further comprises a first initialization signal line and a second initialization signal line, the first initialization signal line and the second initialization signal line are used for transmitting different initialization signals, and the first initialization signal line and the second initialization signal line extend along the first direction and are located on the fourth metal layer. According to the embodiment of the present application, rationality of signal line arrangement can be provided.

Description

Array substrate, display panel and display device

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

The display device may use pixel circuits to drive light emitting elements to emit light. With the development of display technologies, requirements for power consumption of display devices, display effects with low refresh rates, and the like are increasingly high. In order to reduce power consumption of the display device and ensure display effect, LTPO (Low Temperature Polycrystalline Oxide) technology may be used, and the pixel circuit may include both a Low Temperature Polycrystalline silicon thin film transistor and an Oxide thin film transistor.

However, in the related art, the arrangement of the signal lines in the array substrate using the LTPO technology is not reasonable.

Disclosure of Invention

The embodiment of the application provides an array substrate, a display panel and a display device, which can provide rationality of signal line arrangement.

In a first aspect, an embodiment of the present application provides an array substrate, including a substrate, and a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer that are sequentially away from the substrate, where an insulating layer is disposed between adjacent film layers in the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer;

the array substrate further comprises a first initialization signal line and a second initialization signal line, the first initialization signal line and the second initialization signal line are used for transmitting different initialization signals, and the first initialization signal line and the second initialization signal line extend along the first direction and are located on the fourth metal layer.

In a possible implementation manner of the first aspect, the array substrate further includes a fifth metal layer, where the fifth metal layer is located on a side of the fourth metal layer away from the substrate;

the array substrate further comprises at least one of a first auxiliary line and a second auxiliary line;

the first auxiliary line extends along the second direction, is positioned on the fifth metal layer and is connected with the first initialization signal line through the first through hole;

the second auxiliary line extends along the second direction, is positioned on the fifth metal layer and is connected with the second initialization signal line through a second through hole;

preferably, in the first direction, the first auxiliary lines and the second auxiliary lines are alternately arranged, and the first direction and the second direction intersect;

preferably, at least two pixel circuits arranged in the first direction are disposed between adjacent first auxiliary lines and second auxiliary lines.

In one possible implementation of the first aspect, the array substrate further includes a pixel circuit, the pixel circuit including a driving transistor, a first transistor, a second transistor, and a first electrode of a light emitting element;

a first pole of the first transistor is electrically connected with the first initialization signal line, and a second pole of the first transistor is electrically connected with the grid electrode of the driving transistor;

a first pole of the second transistor is electrically connected with the second initialization signal line, and a second pole of the second transistor is electrically connected with the first electrode of the light-emitting element;

preferably, the first transistor is an indium gallium zinc oxide thin film transistor;

preferably, the second transistor is a low-temperature polysilicon thin film transistor;

preferably, the array substrate further includes:

the first semiconductor layer is positioned between the substrate and the first metal layer, and the active layer of the second transistor is positioned on the first semiconductor layer;

and the second semiconductor layer is positioned between the second metal layer and the third metal layer, and the active layer of the first transistor is positioned on the second semiconductor layer.

In a possible implementation manner of the first aspect, the array substrate further includes a first connection portion, the pixel circuit further includes a third transistor, the first connection portion is located on the fourth metal layer, the gate of the driving transistor is located on the first metal layer, the first connection portion is connected to the gate of the driving transistor through a third via, and the first connection portion is connected to the source or the drain of the third transistor through the fourth via;

preferably, the second initialization signal line comprises a plurality of first segments and a plurality of second segments, the first segments and the second segments are alternately connected, and an orthographic projection part of the second segments on the substrate surrounds an orthographic projection of the fourth vias on the substrate in the second direction and on the side of the fourth vias far away from the driving transistor;

preferably, in the second direction, the first segment is located between the driving transistor and the second segment, the first segment extends in the first direction, a part of the line segment of the second segment extends in the first direction, and the first direction and the second direction intersect.

In a possible implementation manner of the first aspect, the array substrate includes a plurality of pixel circuit groups arranged in a first direction, each pixel circuit group includes two pixel circuits, and two pixel circuits in the pixel circuit groups are arranged in a mirror image manner;

preferably, the pixel circuit comprises a plurality of low-temperature polycrystalline silicon thin film transistors, active layers of the plurality of low-temperature polycrystalline silicon thin film transistors are mutually connected through a second connecting part, and the second connecting part is a polycrystalline silicon semiconductor connecting part;

preferably, in the first direction, the active layers of the plurality of low temperature polysilicon thin film transistors adjacent to each other and belonging to two pixel circuits in different pixel circuit groups are connected to each other by a third connection portion, and the third connection portion is a polysilicon semiconductor connection portion.

the array substrate further comprises a first power line, the extending direction of the first power line is crossed with the extending direction of the first initialization signal line and the second initialization signal line, and the first power line is located on the fifth metal layer;

preferably, the first power line includes a plurality of third segments and a plurality of fourth segments, the third segments and the fourth segments are alternately connected, in the second direction, an orthogonal projection of the driving transistor on the substrate is located between orthogonal projections of adjacent third segments on the substrate, a size of the third segments in the first direction is larger than a size of the fourth segments in the first direction, and an orthogonal projection of the first electrode of the light emitting element on the substrate at least partially overlaps an orthogonal projection of the third segments on the substrate.

In a possible implementation manner of the first aspect, the array substrate further includes a fourth connection portion, the fourth connection portion is located on the fourth metal layer, and at least two first power lines adjacent to each other in the first direction are connected by the fourth connection portion;

the pixel circuit further comprises a storage capacitor, the storage capacitor comprises a first polar plate and a second polar plate, the second polar plate is located on the second metal layer, and the fourth connecting part is connected with the second polar plate through a fifth through hole;

preferably, the first plate is located on the first metal layer, and the gate of the driving transistor is reused as the first plate.

In one possible implementation manner of the first aspect, the array substrate further includes a first scan line, a second scan line, a third scan line, a fourth scan line, and a light-emitting control line, all of which extend in the first direction;

the second scanning line, the fourth scanning line and the light-emitting control line are all positioned on the first metal layer;

the first scanning line and the third scanning line are both positioned on the third metal layer;

preferably, the array substrate further includes a pixel circuit, the pixel circuit includes a first transistor and a third transistor, the first transistor and the third transistor are indium gallium zinc oxide thin film transistors, the array substrate further includes a fifth scan line and a sixth scan line, the first scan line is connected to the first gate of the first transistor, the fifth scan line is connected to the second gate of the first transistor, the third scan line is connected to the first gate of the third transistor, the sixth scan line is connected to the second gate of the third transistor, and the fifth scan line and the sixth scan line are both located on the second metal layer;

preferably, the orthographic projection of the first scan line on the substrate and the orthographic projection of the fifth scan line on the substrate at least partially overlap;

preferably, the orthographic projection of the third scanning line on the substrate and the orthographic projection of the sixth scanning line on the substrate at least partially overlap;

preferably, the array substrate comprises a plurality of rows of pixel circuits, the second scanning lines connected with the ith row of pixel circuits are multiplexed into the fourth scanning lines connected with the (i + 1) th row of pixel circuits, and i is an integer greater than 0.

Based on the same inventive concept, in a second aspect, embodiments of the present application provide a display panel including the array substrate according to any one of the embodiments of the first aspect.

Based on the same inventive concept, in a third aspect, the present application provides a display device including the display panel according to the embodiment of the second aspect.

According to the array substrate, the display panel and the display device provided by the embodiment of the application, because the first initialization signal line and the second initialization signal line are both located on the fourth metal layer, the first initialization signal line and/or the second initialization signal line are/is required to be connected to the active layer located on the first semiconductor layer or the active layer located on the second semiconductor layer, the connection between the first initialization signal line and the active layer can be realized only by arranging one through hole, the connection between the second initialization signal line and the active layer can be realized only by arranging one through hole, and two through holes and one section of metal wiring are required to be arranged. The number of the required through holes can be reduced, and extra metal wiring is not required to be arranged, so that the occupied area of the pixel circuit can be reduced, and high pixel density can be realized; in addition, the quantity of via holes and metal wires is reduced, and the light transmittance can be improved.

Drawings

Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.

Fig. 1 is a schematic top view illustrating an array substrate according to an embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional view illustrating an array substrate according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a pixel circuit in an array substrate according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram illustrating a local area of an array substrate according to an embodiment of the present disclosure;

fig. 5 is a schematic cross-sectional view illustrating an array substrate according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a local area of an array substrate according to another embodiment of the present disclosure;

fig. 7 is a schematic structural diagram illustrating a local area of an array substrate according to yet another embodiment of the present application;

fig. 8 is a schematic structural diagram illustrating a local area of an array substrate according to yet another embodiment of the present application;

fig. 9 is a schematic structural diagram illustrating a local area of an array substrate according to yet another embodiment of the present application;

FIG. 10 is a schematic sectional view taken along line A-A of FIG. 4;

fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

In the embodiments of the present application, the term "connected" may mean that two components are directly connected, or may mean that two components are connected via one or more other components.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the corresponding claims (the claimed subject matter) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without contradiction.

Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically explains the problems existing in the related art:

as mentioned in the background art, LTPO technology may be employed in pursuit of low power consumption and good display effect. That is, the pixel circuit may include both the low temperature polysilicon thin film transistor and the oxide thin film transistor. Before the data signal is written into the grid electrode of the driving transistor, the grid electrode of the driving transistor can be initialized to ensure that the data signal can be effectively written; before the light emitting phase, a first electrode (e.g. an anode) of the light emitting element may be initialized to avoid the image sticking problem. The inventors have studied and found that different initialization signal lines may be used to transmit different initialization signals to the gate of the driving transistor and the first electrode of the light emitting element, respectively, to satisfy different initialization requirements of the gate of the driving transistor and the first electrode of the light emitting element.

The inventor further researches and discovers that the grid electrode of the driving transistor can be connected with the oxide thin film transistor, and the initialization signal line can be connected with the grid electrode of the driving transistor through the oxide thin film transistor, because the low-temperature polycrystalline oxide thin film transistor has the characteristics of low leakage current and low power consumption. As an example, the initialization signal line may be disposed on a side of the active layer of the oxide thin film transistor close to the substrate, however, in the current manufacturing process, in order to achieve connection between the initialization signal line and the active layer of the oxide thin film transistor (the active layer may include a channel region and source and drain regions on both sides thereof, and the initialization signal line may be connected to the source or drain region of the active layer), a metal trace needs to be disposed on a metal layer on a side of the active layer of the oxide thin film transistor away from the substrate, and the metal trace is connected to the initialization signal line through one via and connected to the active layer of the oxide thin film transistor through another via.

It can be seen that in order to connect the initialization signal line to the active layer of the oxide thin film transistor, the above example requires two vias and a metal trace. However, the larger the number of the vias and the metal traces, the larger the area occupied by the pixel circuit. If the area occupied by the pixel circuit is set to be smaller, the through holes and the routing lines are not arranged in enough space; if enough space is ensured for placing the via and the trace, the area occupied by the pixel circuit needs to be set larger, which is contrary to the pursuit of high pixel density.

In view of the above research findings of the inventors, embodiments of the present application provide an array substrate, a display panel and a display device, and embodiments of the array substrate, the display panel and the display device provided by embodiments of the present application will be described below with reference to the accompanying drawings.

First, the array substrate provided in the embodiments of the present application will be described.

For example, the array substrate provided by the embodiments of the present application may be a substrate used in a display device. As shown in fig. 1, the array substrate 100 may include a pixel circuit 10, and the pixel circuit 10 may drive the light emitting device to emit light for display. For example, the plurality of pixel circuits 10 may be distributed in an array in the first direction X and the second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X and the second direction Y may be perpendicular to each other. The first direction X may be a row direction and the second direction Y may be a column direction. Of course, the row and column directions may be interchanged.

As shown in fig. 2, in the thickness direction of the array substrate 100, the array substrate 100 may include a substrate 01, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4, which are sequentially stacked. Insulating layers are arranged among adjacent film layers in the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4.

Fig. 2 also illustrates the first semiconductor layer 11 and the second semiconductor layer 12 for a better understanding of the present application as a whole. The first semiconductor layer 11 may be located between the substrate 01 and the first metal layer M1, and the second semiconductor layer 12 may be located between the second metal layer M2 and the third metal layer M3. For example, a first gate insulating layer GI1 may be disposed between the first metal layer M1 and the first semiconductor layer 11, a capacitor insulating layer IMD may be disposed between the second metal layer M2 and the first metal layer M1, a first interlayer insulating layer ILD1 may be disposed on a side of the second metal layer M2 away from the substrate 01, a second gate insulating layer GI2 may be disposed between the first interlayer insulating layer ILD1 and the second semiconductor layer 12, a third gate insulating layer GI3 may be disposed between the third metal layer M3 and the second semiconductor layer 12, a second interlayer insulating layer ILD2 may be disposed between the third metal layer M3 and the fourth metal layer M4, and a first planarization PLN1 may be disposed on a side of the second interlayer insulating layer ILD2 away from the substrate 01. Fig. 2 is merely exemplary and is not intended to limit the present application.

It should be noted that the cross-sectional drawings in this application are only for describing the film structure of the array substrate in the thickness direction of the array substrate, and do not refer to the cross-sectional structure of a specific position of the array substrate.

As shown in fig. 1, the array substrate 100 may further include a first initialization signal line Vref1 and a second initialization signal line Vref2, and the first initialization signal line Vref1 and the second initialization signal line Vref2 may be connected to different nodes of the pixel circuit 10 for transmitting different initialization signals to the different nodes of the pixel circuit 10 to initialize the different nodes of the pixel circuit.

The extending directions of the first and second initialization signal lines Vref1 and Vref2 may be the same. For example, the first and second initialization signal lines Vref1 and Vref2 may each extend in the first direction X as a whole, and the first and/or second initialization signal lines Vref1 and Vref2 may be straight line segments, or may include straight line segments and curved line segments.

The first and second initialization signal lines Vref1 and Vref2 may both be located at the fourth metal layer M4. For example, an active layer of a part of transistors in the pixel circuit may be disposed on the first semiconductor layer 11, and an active layer of another part of transistors may be disposed on the second semiconductor layer 12. Since the first initialization signal line Vref1 and the second initialization signal line Vref2 are both located in the fourth metal layer M4, no matter the first initialization signal line Vref1 and/or the second initialization signal line Vref2 need to be connected to the active layer located in the first semiconductor layer 11 or the active layer located in the second semiconductor layer 12, the connection between the first initialization signal line Vref1 and the active layer can be realized only by providing one via hole, and the connection between the second initialization signal line Vref2 and the active layer can be realized only by providing one via hole. Compared with the example in which the initialization signal line and the active layer are connected only by arranging two via holes and one section of metal routing, the embodiment of the application can reduce the number of the required via holes without arranging additional metal routing, thereby being beneficial to reducing the area occupied by the pixel circuit and further being beneficial to realizing high pixel density; in addition, the number of the via holes and the metal routing wires is reduced, and the light transmittance can be improved.

In some alternative embodiments, as shown in fig. 3, the pixel circuit may include a driving transistor DT, a first transistor T1, and a second transistor T2, and the first electrode of the light emitting element D may also be disposed on the array substrate.

A first pole of the first transistor T1 is connected to the first initialization signal line Vref1, and a second pole of the first transistor T1 is connected to the gate electrode of the driving transistor DT. A first electrode of the second transistor T2 is connected to the second initialization signal line Vref2, and a second electrode of the second transistor T2 is connected to the first electrode of the light emitting element D. With the first transistor T1 turned on, the first initialization signal on the first initialization signal line Vref1 may be transmitted to the gate of the driving transistor DT, thereby initializing the gate of the driving transistor DT. With the second transistor T2 turned on, the second initialization signal on the second initialization signal line Vref2 can be transmitted to the first electrode of the light emitting element D, thereby initializing the first electrode of the light emitting element D.

The first electrode of the light emitting element D may be an anode of the light emitting element D.

Illustratively, the first transistor T1 may be an oxide thin film transistor, and particularly may be an indium gallium zinc oxide thin film transistor. Since the indium gallium zinc oxide thin film transistor has a characteristic of low leakage current, the gate potential stability of the driving transistor DT can be improved. An active layer of the first transistor T1 may be disposed on the second semiconductor layer 12 as shown in fig. 2. The second transistor T2 may be a low temperature polysilicon thin film transistor. The second transistor T2 may be disposed at the first semiconductor layer 11 as shown in fig. 2.

For example, as shown in fig. 4, the first initialization signal line Vref1 may be connected to the first pole of the first transistor T1 through the sixth via h 6. The second initialization signal line Vref2 may be connected to the first pole of the second transistor T2 through the seventh via h 7.

For example, as shown in fig. 3, the pixel circuit may further include a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst.

The gate of the first transistor T1 may be connected to the first scan line S1. The gate of the second transistor T2 may be connected to the fourth scan line S4.

A first pole of the third transistor T3 is connected to the second pole of the driving transistor DT, a second pole of the third transistor T3 is connected to the gate electrode of the driving transistor DT, and a gate electrode of the third transistor T3 is connected to the third scanning line S3.

A first pole of the fourth transistor T4 is connected to the data line Vdata, a second pole of the fourth transistor T4 is connected to the first pole of the driving transistor DT, and a gate of the fourth transistor T4 is connected to the second scan line S2.

A first electrode of the fifth transistor T5 is connected to the first power source line VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor DT, and a gate electrode of the fifth transistor T5 is connected to the light emission control line EM.

A first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor DT, a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element D, and a gate electrode of the sixth transistor T6 is connected to the emission control line EM.

A first plate of the storage capacitor Cst is connected to the gate electrode of the driving transistor DT, and a second plate of the storage capacitor Cst is connected to the first power line VDD. The first power line VDD may be used to transmit a constant positive voltage signal.

The second electrode of the light emitting element D is connected to a second power line VSS. The second electrode of the light emitting element may be a cathode. The second power line VSS may be used to transmit a constant negative voltage signal.

Herein, one of the first and second poles of the transistor may be a source of the transistor, and the other may be a drain of the transistor.

Illustratively, the first transistor T1 and the third transistor T3 may be oxide thin film transistors, and particularly, may be indium gallium zinc oxide transistors. The driving transistor DT, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be all low temperature polysilicon thin film transistors.

In some alternative embodiments, as shown in fig. 5, the array substrate may further include a fifth metal layer M5, where the fifth metal layer M5 is located on a side of the fourth metal layer M4 away from the substrate 01. The fifth metal layer M5 and the fourth metal layer M4 may be insulated from each other by a first planarization layer PLN1, and a second planarization layer PLN2 may be further disposed on a side of the fifth metal layer M5 away from the substrate 01.

As shown in fig. 6 and 7, the array substrate may further include at least one of a first auxiliary line 21 and a second auxiliary line 22. Fig. 6 and 7 show that the array substrate includes first auxiliary lines 21 and second auxiliary lines 22. In addition, fig. 7 only shows the first initialization signal line Vref1, the second initialization signal line Vref2, the first auxiliary line 21, the second auxiliary line 22 and the connecting via, and other film layers are shown in a hidden manner.

The first auxiliary line 21 extends in the second direction Y, and the first auxiliary line 21 is located at the fifth metal layer M5. The first auxiliary line 21 is connected to the first initialization signal line Vref1 through a first via h 1. The plurality of first auxiliary lines 21 may be arranged in the first direction X. According to the embodiment of the present application, the plurality of first initialization signal lines Vref1 and the plurality of first auxiliary lines 21 may form a grid structure, and the voltage drop of the first initialization signal line Vref1 may be reduced, thereby improving the uniformity of the first initialization signal received by the pixel circuits at different positions.

The second auxiliary lines 22 extend in the second direction Y, and the second auxiliary lines 22 are located at the fifth metal layer M5. The second auxiliary line 22 is connected to the second initialization signal line Vref2 through a second via h 2. The plurality of second auxiliary lines 22 may be arranged in the first direction X. Similarly, the plurality of second initialization signal lines Vref2 and the plurality of second auxiliary lines 22 may form a grid structure, which may reduce the voltage drop of the second initialization signal lines Vref2, thereby improving the uniformity of the second initialization signals received by the pixel circuits at different positions.

For example, as shown in fig. 6 or 7, the first auxiliary lines 21 and the second auxiliary lines 22 may be alternately arranged in the first direction X.

Illustratively, as shown in fig. 6, at least two pixel circuits that are arrangeable along the first direction X are disposed between adjacent first auxiliary lines 21 and second auxiliary lines 22. The drawings herein illustrate two pixel circuits that may be arranged along the first direction X between adjacent first auxiliary lines 21 and second auxiliary lines 22, which is not intended to limit the present application.

In some alternative embodiments, as shown in fig. 4, the third transistor T3 may be connected to the gate g of the driving transistor DT through the first connection portion 31. For example, the first connection portion 31 may be located at the fourth metal layer M4, and the gate g of the driving transistor DT may be located at the first metal layer M1. The source or drain of the third transistor T3 is disposed on the same layer as the active layer thereof, and the active layer of the third transistor T3 may be located on the second semiconductor layer 12. The first connection portion 31 may be connected to the gate g of the driving transistor DT through a third via h3, and the first connection portion 31 may be connected to the second pole of the third transistor T3 through a fourth via h 4. The second pole of the third transistor T3 is a source or a drain.

In some alternative embodiments, referring to fig. 4 and fig. 7 in combination, the second initialization signal line Vref2 may include a plurality of first segments 201 and a plurality of second segments 202, and the first segments 201 and the second segments 202 may be alternately connected, that is, adjacent first segments 201 are connected by the second segments 202, and adjacent second segments 202 are connected by the first segments 20. In the second direction Y and on a side of the fourth via h4 away from the driving transistor DT, an orthographic projection of the second segment 202 on the substrate 01 partially surrounds an orthographic projection of the fourth via h4 on the substrate 01. That is, the second segment 202 may detour at a side of the fourth via h4 away from the driving transistor DT. First segment 201 and second segment 202 are located in fourth metal layer M4. Since the first connection portion 31 and the second initialization signal line Vref2 are both located in the fourth metal layer M4, by bypassing the second segment 202 on the side of the fourth via h4 away from the driving transistor DT, the first connection portion 31 and the second initialization signal line Vref2 can be prevented from crossing each other, and thus signal crosstalk can be avoided.

Herein, for clarity of explanation of the structure of the second initialization signal line Vref2, the second initialization signal line Vref2 is divided into the first segment 201 and the second segment 202, and the first segment 201 and the second segment 202 may be integrally formed, that is, the second initialization signal line Vref2 may not be physically demarcated as a whole.

For example, the first segment 201 may extend along the first direction X, and the first segment 201 is located between the driving transistor DT and the second segment 202 in the second direction Y. A partial line segment of the second segment 202 may extend in the first direction X.

In some alternative embodiments, as shown in fig. 1, the pixel circuits 10 arranged in the first direction X may be divided into a plurality of pixel circuit groups PU, and each pixel circuit group PU may include two pixel circuits 10.

As shown in fig. 6, fig. 6 shows a total of eight pixel circuits in the ith row, the ith +1 th row, the jth column, the jth +1 th column, the jth +2 th column and the jth +3 th column. Two pixel circuits located at the jth column and the jth +1 column of the ith row can belong to one pixel circuit group PU, and two pixel circuits located at the jth +2 column and the jth +3 column of the ith row can belong to one pixel circuit group PU; two pixel circuits located at the jth column and the jth +1 column of the (i + 1) th row may belong to one pixel circuit group PU, and two pixel circuits located at the jth +2 column and the jth +3 column of the (i + 1) th row may belong to one pixel circuit group PU. i and j are integers greater than 0.

As shown in fig. 6, two pixel circuits in the pixel circuit group may be arranged in a mirror image. Assuming that there is an interface between two pixel circuits in the pixel circuit group, the interface is perpendicular to the plane of the array substrate, and the mirror image arrangement means that the two pixel circuits in the pixel circuit group are symmetrically arranged about the interface. The transistors at the same positions of the two pixel circuits may be symmetrical to each other, for example, the driving transistors DT of the two pixel circuits may be symmetrical to each other, the first transistors of the two pixel circuits may be symmetrical to each other, and so on.

According to the embodiment of the application, the space utilization rate can be improved through the mirror image setting mode, so that more pixel circuits can be arranged in a limited space, and the pixel density is further improved.

For example, as shown in fig. 3, the driving transistor DT, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 in the pixel circuit may be low temperature polysilicon thin film transistors.

The inventor researches and discovers that the preparation process of the active layer of the low-temperature polycrystalline silicon thin film transistor comprises high-temperature processes, such as annealing and activating processes, and static electricity in the high-temperature processes can have irreversible influence on the performance of the active layer, so that the performance of the corresponding transistor is influenced. In the high temperature process, electrostatic influence of different degrees may be caused to the active layers of the transistors at different positions, which may cause inconsistent performance of the transistors of the pixel circuits at different positions, thereby affecting display uniformity.

As shown in fig. 8, the active layers of the plurality of ltps tfts may be connected to each other through a second connection portion 32, and the second connection portion 32 may be a polysilicon semiconductor connection portion. For example, an active layer of a low temperature polysilicon thin film transistor may be located at the first semiconductor layer 11. In order to more clearly illustrate the active layer and the second connection portion of the low temperature polysilicon thin film transistor, fig. 8 shows only the film structure of the first semiconductor layer 11 in the pixel circuits of the ith row, the (i + 1) th row, the jth column, the (j + 1) th column, the (j + 2) th column and the (j + 3) th column. The active layer of each low temperature polysilicon thin film transistor can comprise a channel region and a source region and a drain region which are arranged at two sides of the channel region, the channel region is overlapped with the grid electrode of the low temperature polysilicon thin film transistor, and the source region and the drain region can be not overlapped with the grid electrode of the low temperature polysilicon thin film transistor. In FIG. 8, b _DT Showing the active layer of the drive transistor DT, b ₂ Denotes an active layer of a second transistor T2, b ₄ Showing the active layer of the fourth transistor T4, b ₅ Showing the active layer of the fifth transistor T5 b ₆ An active layer of the sixth transistor T6 is shown.

According to the embodiment of the application, the active layers of the low-temperature polycrystalline silicon thin film transistors in the same pixel circuit are connected with each other through the second connecting portion 32, so that the active layers of the low-temperature polycrystalline silicon thin film transistors in the same pixel circuit form a continuous semiconductor wiring, static electricity generated in the preparation process can be uniformly distributed on the continuous semiconductor wiring, the reliability and the uniformity of performance in subsequent high-temperature processes are further improved, the driving capability of the pixel circuit is basically consistent, the display uniformity is realized, and the display effect is improved.

Illustratively, in the first direction X, the active layers of the plurality of low temperature polysilicon thin film transistors adjacent to each other and belonging to two pixel circuits in different pixel circuit groups may be connected to each other by a third connection portion 33, and the third connection portion 33 may also be a polysilicon semiconductor connection portion. For example, the active layer b of the fifth transistor T5 in two pixel circuits belonging to different pixel circuit groups ₅ The connection may be achieved by a third connection 33.

According to the embodiment of the application, the active layers of the low-temperature polycrystalline silicon thin film transistors in different pixel circuits form a continuous semiconductor routing line, and the display uniformity can be further improved.

Note that the node potentials of the two pixel circuits and the node potential connected to the third connection portion 33 should be the same at the same time. For example, the first pole of the fifth transistor T5 in the pixel circuit is connected to the first power supply line VDD, and the potential of the first power supply line VDD is a constant potential, so the first poles of the fifth transistors T5 in two pixel circuits belonging to different pixel circuit groups may be connected to each other through the third connection portion 33.

In some alternative embodiments, as shown in fig. 6, the extending direction of the first power line VDD may cross the extending direction of the first and second initialization signal lines Vref1 and Vref 2. In the case where the first and second initialization signal lines Vref1 and Vref2 extend in the first direction X, the first power supply line VDD may extend in the second direction Y as a whole. The first power line VDD may be located at the fifth metal layer M5 as shown in fig. 5.

In order to illustrate the structure of the first power line VDD more clearly, as shown in fig. 9, the first power line VDD may include a plurality of third segments 203 and a plurality of fourth segments 204, and the third segments 203 and the fourth segments 204 are alternately connected. That is, the fourth segment 204 may be connected between two adjacent third segments 203, and the third segment 203 may be connected between two adjacent fourth segments 204. Herein, for clarity of explanation of the structure of the first power line VDD, the first power line VDD is divided into the third segment 203 and the fourth segment 204, and the third segment 203 and the fourth segment 204 may be an integrally formed structure, that is, the first power line VDD may not have a physical boundary as a whole.

The inventors have studied and found that if the first electrode of the light emitting element is provided on a film layer which is not flat enough, a problem of color shift is caused. To improve the color shift problem, referring to fig. 6 and 9 in combination, in the second direction Y, the orthographic projection of the driving transistor DT on the substrate 01 may be located between the orthographic projections of the adjacent third segments 203 on the substrate 01. There may be an overlap between the orthographic projection of the fourth segment 204 on the substrate 01 and the orthographic projection of the driving transistor DT on the substrate 01. A dimension of the third segment 203 in the first direction X may be larger than a dimension of the fourth segment 204 in the first direction X, and an orthogonal projection of a first electrode (not shown in fig. 6 and 9) of the light emitting element on the substrate 01 at least partially overlaps with an orthogonal projection of the third segment 203 on the substrate 01. Since the driving transistor DT is connected to other elements (e.g., the first transistor T1, the third transistor T3, the storage capacitor Cst, etc.), a plurality of via holes need to be formed around the driving transistor DT to connect the driving transistor to other elements, and the via holes may affect the flatness of the film layer, since the third segment 203 is far away from the driving transistor DT, it can be understood that there are fewer via holes in the region where the third segment 203 is located, so that the overlapping region of the first electrode of the light emitting element and the third segment 203 is relatively flat, and the larger the size of the third segment 203 in the first direction X is, the higher the flatness of the first electrode of the light emitting element can be, so as to improve or even avoid the problem of color shift.

For example, the area where the third segment 203 is located may be free of through holes, so as to further ensure the flatness of the film layer in the area where the third segment 203 is located.

Illustratively, two third segments 203 in the same pixel circuit group and adjacent in the first direction X may be connected to each other. For example, two third segments 203 adjacent to each other in the first direction X in the same pixel circuit group may be integrally formed.

With continuing reference to fig. 4, fig. 6 and fig. 9, in some alternative embodiments, the array substrate may further include a fourth connection portion 34, and the fourth connection portion 34 may be located on a fourth metal layer M4 shown in fig. 2 or fig. 5, and is connected between at least two adjacent first power lines VDD in the first direction X through the fourth connection portion 34. For example, the fourth connection portion 34 may be connected between two fourth segments 204 adjacent in the first direction X. For another example, two fourth segments 204 adjacent to each other in the first direction X in different pixel circuit groups are connected by the fourth connection portion 34. In the embodiment of the present invention, the fourth connection portion 34 is provided to correspond to the first power supply line VDD formed in a grid pattern, so that the voltage drop of the first power supply line VDD can be reduced.

Of course, the fourth connecting portion 34 may also be connected between two third segments 203 adjacent in the first direction X.

Illustratively, two fourth segments 204 in different pixel circuit groups and adjacent to each other in the first direction X, one of the fourth segments 204 may be connected to the fourth connection portion 34 through an eighth via h8, and the other fourth segment 204 may be connected to the fourth connection portion 34 through a ninth via h 9. In addition, the fourth connection portion 34 may connect the third connection portion 33 through the tenth via h10, and the third connection portion 33 connects the first poles of two adjacent fifth transistors T5 in different pixel circuit groups, so that the first power line VDD is connected to the first pole of the fifth transistor T5 through the fourth and third connection portions 34, 33.

With continued reference to fig. 4, 6 and 9, the storage capacitor Cst may include a first plate c1 and a second plate c2, the second plate c2 may be located on the second metal layer M2, and the fourth connecting portion 34 may be connected to the second plate c2 through a fifth via h 5. In this way, the first power line VDD is connected to the second plate c2 through the fourth connection portion 34, and is connected to the second plate c2 through a via hole relative to the fourth segment 204, since the fourth segment 204 is located at the fifth metal layer M5, and the fourth connection portion 34 is located at the fourth metal layer M4, the fourth connection portion 34 is connected to the second plate c2 through the fifth via hole h5, so that the depth of the via hole can be reduced.

For example, the first plate c1 may be located on the first metal layer M1, and the gate g of the driving transistor DT may be reused as the first plate c 1.

It is to be understood that the orthographic projections of the first plate c1 and the second plate c2 on the substrate 01 should at least partially overlap. The area of the second plate c2 may be larger than that of the first plate c1, the first connection portion 31 is connected to the gate g of the driving transistor DT through the third via hole h3, when the gate g is multiplexed as the first plate c1, that is, the first connection portion 31 is connected to the first plate c1 through the third via hole h3, the third via hole h3 needs to pass through the second plate c2, the second plate c2 may have a hollow region, so that the third via hole h3 passes through the hollow region, the second plate c2 is prevented from contacting with the third via hole h3, and signal crosstalk is avoided.

In some alternative embodiments, as shown in fig. 4, a portion of the second scan line S2 overlapping the active layer of the fourth transistor T4 may be multiplexed as a gate of the fourth transistor T4. A portion of the fourth scan line S4 overlapping the active layer of the second transistor T2 may be multiplexed as a gate of the second transistor T2. The portions of the emission control line EM overlapping the active layers of the fifth and sixth transistors T5 and T6 may be multiplexed as the gate electrode of the fifth and sixth transistors T5 and T6, respectively. The second scan line S2, the fourth scan line S4, and the light emission control line EM may all be located at the first metal layer M1.

A portion of the first scan line S1 overlapping the active layer of the first transistor T1 may be multiplexed as a gate of the first transistor T1. A portion of the third scan line S3 overlapping the active layer of the third transistor T3 may be multiplexed as a gate of the third transistor T3. The first scan line S1 and the third scan line S3 may both be located on the third metal layer M3.

The first scan line S1, the second scan line S2, the third scan line S3, the fourth scan line S4, and the light emission control lower EM may all extend in the first direction X as a whole. The second scanning line S2, the third scanning line S3, the fourth scanning line S4, and the EM under light emission control may be straight lines. The first initialization signal line Vref1 is connected to the first pole of the first transistor T1 through the sixth via h6, and in order to avoid contact crosstalk between the first scan line S1 and the sixth via h6, a partial line segment of the first scan line S1 may bypass the sixth via h6 on a side close to the driving transistor DT in the second direction Y.

For example, in the case that the first transistor T1 and the third transistor T3 are oxide thin film transistors, and may specifically be indium gallium zinc oxide transistors, both the first transistor T1 and the third transistor T3 may be a double-gate structure including a top gate and a bottom gate, so that the leakage current of the first transistor T1 and the third transistor T3 is further reduced, and the stability of the gate potential of the driving transistor DT is further improved.

For example, as shown in fig. 10, the array substrate may further include a fifth scan line S5 and a sixth scan line S6, and the fifth scan line S5 and the sixth scan line S6 may both be located on the second metal layer M2. The first scan line S1 is connected to the first gate g11 of the first transistor T1, the fifth scan line S5 is connected to the second gate g12 of the first transistor T1, the third scan line S3 is connected to the first gate g31 of the third transistor T3, and the sixth scan line S6 is connected to the second gate g32 of the third transistor T3.

The first gate g11 may be understood as a top gate of the first transistor T1, and the second gate g12 may be understood as a bottom gate of the first transistor T1. The first gate g31 may be understood as a top gate of the third transistor T3, and the second gate g32 may be understood as a bottom gate of the third transistor T3. A portion of the first scan line S1 overlapping the active layer b1 of the first transistor T1 may be multiplexed as the first gate g11, and a portion of the fifth scan line S5 overlapping the active layer b1 of the first transistor T1 may be multiplexed as the second gate g 12. A portion of the third scan line S3 overlapping the active layer b3 of the third transistor T3 may be multiplexed as the first gate g31 of the third transistor T3, and a portion of the sixth scan line S6 overlapping the active layer b3 of the third transistor T3 may be multiplexed as the second gate g 32.

Illustratively, a fifth connection part 35 may be connected between the active layer b1 of the first transistor T1 and the active layer b3 of the third transistor T3. The fifth connection portion 35 may be an oxide semiconductor connection portion. The active layer b1 of the first transistor T1, the active layer b3 of the third transistor T3, and the fifth connection portion 35 may be located on the second semiconductor layer 12.

For example, the first connection part 31 may be connected to the fifth connection part 35 through the fourth via h4, thereby achieving connection between the first transistor T1 and the gate electrode of the driving transistor DT and connection between the third transistor and the gate electrode of the driving transistor DT.

As shown in fig. 10, the orthographic projection of the first scan line S1 on the substrate 01 and the orthographic projection of the fifth scan line S5 on the substrate 01 may at least partially overlap. The orthographic projection of the third scan line S3 on the substrate 01 and the orthographic projection of the sixth scan line S6 on the substrate 01 may at least partially overlap. For clarity of the drawing, fig. 4 only marks the first scanning line S1 and the third scanning line S3. It will be appreciated that the orthographic projection of the first scan line S1 on the substrate 01 and the orthographic projection of the fifth scan line S5 on the substrate 01 may completely overlap. The orthogonal projection of the third scan line S3 on the substrate 01 and the orthogonal projection of the sixth scan line S6 on the substrate 01 may completely overlap.

For example, the pixel circuits may be arranged in a plurality of rows, and as shown in fig. 4, the second scan line S2 to which the pixel circuit of the ith row is connected may be multiplexed into the fourth scan line S4 to which the pixel circuit of the (i + 1) th row is connected, i being an integer greater than 0. This reduces the number of scan lines. It is understood that the gate of the second transistor T2 in the pixel circuit of the (i + 1) th row receives the same signal as the fourth transistor T4 in the pixel circuit of the (i) th row.

As an example, fig. 6 also shows a data line Vdata, which may extend in the second direction Y. The data line Vdata may be located at the fifth metal layer M5. For example, the data line Vdata may be connected to the first pole of the fourth transistor T4 through the eleventh via h 11.

As an example, as shown in fig. 4, the array plate may further include a sixth connection part 36, a twelfth via h12, and a thirteenth via h 13. The sixth connection part 36 may be located at the fourth metal layer M4, the sixth connection part 36 may be connected to the active layer of the third transistor T3 through a twelfth via h12, and the sixth connection part 36 may be connected to the active layer of the driving transistor DT through a thirteenth via h 13.

As an example, as shown in fig. 4, the array plate may further include a seventh connection portion 37, a fourteenth via h14, and a fifteenth via h 15. The seventh connection portion 37 may be located on the fourth metal layer M4, the seventh connection portion 37 may be connected to the active layers of the second transistor T2 and the sixth transistor T6 through a fourteenth via h14, and a fifteenth via h15 is connected to the seventh connection portion 37. The first electrode of the light emitting element may be connected to the seventh connection portion 37 (not shown in the drawings) through the fifteenth via h 15.

It should be noted that the via numbers marked herein are only used to distinguish different vias, and do not indicate the preparation sequence of the vias. In addition, in order to avoid that the marks of the via holes are too concentrated to affect the clarity of the drawing, the marks of the via holes are dispersed in different pixel circuits in the drawing.

Based on the same inventive concept, embodiments of the present application further provide a display panel including the array substrate according to any of the above embodiments. Fig. 11 illustrates a schematic structural diagram of a display panel according to an embodiment of the present application. As shown in fig. 11, the display panel 200 includes the array substrate 100 according to any of the embodiments and the light emitting layer 301 on the array substrate 100. Illustratively, the Light Emitting layer 301 may be an Organic Light Emitting layer, i.e., the display panel 200 may be an Organic Light Emitting Diode (OLED) display panel. Of course, the display panel may be other types of display panels, and the present application is not limited thereto.

The application also provides a display device comprising the display panel provided by the application. Referring to fig. 12, fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 12 provides a display device 1000 including the display panel 200 according to any of the above embodiments of the present application. The embodiment of fig. 12 is only an example of a mobile phone, and the display device 1000 is described, it is to be understood that the display device provided in the embodiment of the present application may be other display devices with a display function, such as a wearable product, a computer, a television, a tablet computer, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the stretchable display panel provided in the embodiment of the present application, and specific reference may be made to the specific description of the stretchable display panel in the foregoing embodiments, which is not repeated herein.

In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate is characterized by comprising a substrate, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially far away from the substrate, wherein insulating layers are arranged among adjacent film layers in the first metal layer, the second metal layer, the third metal layer and the fourth metal layer;

the array substrate further comprises a first initialization signal line and a second initialization signal line, the first initialization signal line and the second initialization signal line are used for transmitting different initialization signals, and the first initialization signal line and the second initialization signal line extend along a first direction and are located on the fourth metal layer.

2. The array substrate of claim 1, further comprising a fifth metal layer on a side of the fourth metal layer away from the substrate;

the array substrate further includes at least one of a first auxiliary line and the second auxiliary line;

the first auxiliary line extends along a second direction, is positioned on the fifth metal layer and is connected with the first initialization signal line through a first through hole;

preferably, in a first direction, the first auxiliary lines and the second auxiliary lines are alternately arranged, and the first direction and the second direction intersect;

preferably, at least two pixel circuits arranged in the first direction are disposed between the adjacent first auxiliary lines and the second auxiliary lines.

3. The array substrate according to claim 1, further comprising a pixel circuit including a driving transistor, a first transistor, a second transistor, and a first electrode of a light emitting element;

a first pole of the second transistor is electrically connected to the second initialization signal line, and a second pole of the second transistor is electrically connected to a first electrode of the light emitting element;

preferably, the second transistor is a low-temperature polycrystalline silicon thin film transistor;

preferably, the array substrate further includes:

a first semiconductor layer located between the substrate and the first metal layer, an active layer of the second transistor being located in the first semiconductor layer;

4. The array substrate of claim 3, wherein the array substrate further comprises a first connection portion, the pixel circuit further comprises a third transistor, the first connection portion is located on the fourth metal layer, the gate of the driving transistor is located on the first metal layer, the first connection portion is connected to the gate of the driving transistor through a third via, and the first connection portion is connected to the source or the drain of the third transistor through a fourth via;

preferably, the second initialization signal line includes a plurality of first segments and a plurality of second segments, the first segments and the second segments are alternately connected, and an orthographic projection of the second segments on the substrate surrounds an orthographic projection of the fourth vias on the substrate in the second direction and on a side of the fourth vias away from the driving transistor;

preferably, in the second direction, the first segment is located between the driving transistor and the second segment, the first segment extends in the first direction, a partial line segment of the second segment extends in the first direction, and the first direction and the second direction intersect.

5. The array substrate of any one of claims 1 to 4, wherein the array substrate comprises a plurality of pixel circuit groups arranged in the first direction, each pixel circuit group comprises two pixel circuits, and two pixel circuits in the pixel circuit groups are arranged in a mirror image manner;

preferably, the pixel circuit comprises a plurality of low temperature polysilicon thin film transistors, active layers of the plurality of low temperature polysilicon thin film transistors are connected with each other through a second connecting part, and the second connecting part is a polysilicon semiconductor connecting part;

preferably, in the first direction, active layers of a plurality of low-temperature polysilicon thin film transistors adjacent to and belonging to two pixel circuits in different pixel circuit groups are connected to each other through a third connection portion, and the third connection portion is a polysilicon semiconductor connection portion.

6. The array substrate of claim 3, further comprising a fifth metal layer on a side of the fourth metal layer away from the substrate;

the array substrate further comprises a first power line, the extending direction of the first power line is crossed with the extending direction of the first initialization signal line and the extending direction of the second initialization signal line, and the first power line is located on the fifth metal layer;

preferably, the first power line includes a plurality of third segments and a plurality of fourth segments, the third segments and the fourth segments are alternately connected, in the second direction, an orthogonal projection of the driving transistor on the substrate is located between orthogonal projections of adjacent third segments on the substrate, a size of the third segments in the first direction is larger than a size of the fourth segments in the first direction, and an orthogonal projection of the first electrode of the light emitting element on the substrate at least partially overlaps with an orthogonal projection of the third segments on the substrate.

7. The array substrate of claim 6, further comprising a fourth connection portion located on the fourth metal layer, wherein at least two first power lines adjacent to each other in the first direction are connected to each other through the fourth connection portion;

the pixel circuit further comprises a storage capacitor, the storage capacitor comprises a first polar plate and a second polar plate, the second polar plate is located on the second metal layer, and the fourth connecting portion is connected with the second polar plate through a fifth through hole;

preferably, the first polar plate is located on the first metal layer, and a gate of the driving transistor is reused as the first polar plate.

8. The array substrate according to claim 1 or 2, wherein the array substrate further comprises a first scanning line, a second scanning line, a third scanning line, a fourth scanning line and a light-emitting control line all extending along the first direction;

preferably, the orthographic projection of the first scanning line on the substrate and the orthographic projection of the fifth scanning line on the substrate at least partially overlap;

preferably, an orthogonal projection of the third scan line on the substrate and an orthogonal projection of the sixth scan line on the substrate at least partially overlap;

preferably, the array substrate includes a plurality of rows of pixel circuits, the second scan lines connected to the pixel circuits in the ith row are multiplexed into the fourth scan lines connected to the pixel circuits in the (i + 1) th row, and i is an integer greater than 0.

9. A display panel comprising the array substrate according to any one of claims 1 to 8.

10. A display device characterized by comprising the display panel according to claim 9.