CN114899104B - Manufacturing method of shielded gate trench power device - Google Patents

Manufacturing method of shielded gate trench power device Download PDF

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CN114899104B
CN114899104B CN202210828997.4A CN202210828997A CN114899104B CN 114899104 B CN114899104 B CN 114899104B CN 202210828997 A CN202210828997 A CN 202210828997A CN 114899104 B CN114899104 B CN 114899104B
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layer
substrate
forming
pad oxide
trench
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CN114899104A (en
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闵源
张鼎丰
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Yuexin Semiconductor Technology Co.,Ltd.
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Guangzhou Yuexin Semiconductor Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/76—Patterning of masks by imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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Abstract

The invention provides a manufacturing method of a shielded gate trench power device, which comprises the following steps: providing a substrate, wherein a pad oxide layer covers the substrate; forming an etching barrier layer to cover the pad oxide layer; forming a trench, wherein the ratio of the etching rate of the etching barrier layer to the etching rate of the pad oxide layer is 1.1:1 to 1: 1; forming a shielding gate structure in the trench; forming a layer of isolating material; and performing a grinding process by taking the surface of the substrate as a grinding stop layer to expose the surface of the substrate. In the invention, the first recess with partial depth is filled by the sacrificial layer, and the etching rate of the etching barrier layer is equal to or slightly greater than that of the pad oxide layer during etching, so that the overhang problem of the side wall of the trench can be reduced or avoided. In addition, the surface of the substrate is used as a grinding stop layer, so that the grinding stop layer is not required to be additionally arranged, the process flow is simplified, and the subsequent filling thickness and grinding thickness can be reduced, thereby saving the material cost and improving the production efficiency.

Description

Manufacturing method of shielded gate trench power device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a shielded gate trench power device.
Background
In order to reduce the size of the power device and improve the performance of the power device, a trench structure is introduced into the power device to form a trench type power device. The groove type power device is an important component of an electronic circuit, and has high breakdown voltage and small leakage current in a cut-off state; in the conducting state, the conducting resistance is low, and the voltage of the conducting tube is reduced; during switching, the switching speed is fast, and the switching circuit has the obvious advantages of low on-state loss, low off-state loss, low switching loss and the like, and has become a main power device in the fields of integrated circuits and the like.
Taking the conventional ONO (silicon oxide-silicon nitride-silicon oxide) structure as a Hard Mask (HM, Hard Mask) to form a trench in a substrate as an example, as shown in fig. 1a, an ONO structure composed of a silicon oxide layer 21 ', a silicon nitride layer 22', and a silicon oxide layer 23 'is formed on a substrate 10', and as shown in fig. 1b, the ONO structure is patterned to form a patterned Hard Mask and a trench 11 'is formed in the substrate 10' by using the patterned Hard Mask, and an overhang 12 '(overhang hang) is formed on a sidewall of the formed trench 11', and the existence of the overhang 12 'makes Void (Void) defects easily generated when a shield gate structure and an isolation layer are formed in the trench 11', which seriously affects yield. On the other hand, in order to reduce the influence of the overhang 12 'on the yield, a Pull Back process (Pull Back) has to be additionally added to eliminate the overhang 12', which not only causes the process to be complicated, but also increases the manufacturing cost.
Disclosure of Invention
The invention aims to provide a manufacturing method of a shielded gate trench power device, which is used for simplifying the manufacturing process of the shielded gate trench power device and reducing the cost.
In order to solve the above technical problem, the present invention provides a method for manufacturing a shielded gate trench power device, including: providing a substrate, wherein a pad oxide layer covers the substrate; forming an etching barrier layer, wherein the etching barrier layer covers the pad oxide layer; forming an opening exposing the substrate in the etching barrier layer and the pad oxide layer, forming a groove in the substrate by using the opening, wherein the ratio of the etching rate of the etching barrier layer to the etching rate of the pad oxide layer is 1.1: 1-1: 1 when the opening and the groove are formed by etching; forming a shielding gate structure in the trench, wherein the shielding gate structure is positioned at the bottom of the trench; forming an isolation material layer, wherein the isolation material layer covers the shielding gate structure and the etching barrier layer and fills the groove; and performing a polishing process by taking the surface of the substrate as a polishing stop layer to expose the surface of the substrate, wherein the polishing selection ratio of the pad oxide layer to the substrate is more than 30: 1; and removing part of the thickness of the isolation material layer in the groove, taking the rest isolation material layer as an isolation layer, wherein the isolation layer is used for isolating the shielding gate structure.
Optionally, the substrate includes silicon, and the pad oxide layer includes silicon oxide.
Optionally, the pad oxide layer is formed by a thermal oxidation process.
Optionally, the grinding process is a chemical mechanical grinding process, and the grinding fluid of the grinding process includes ceria suspended particles.
Optionally, the material of the etching barrier layer is the same as that of the pad oxide layer.
Optionally, the material of the etch stop layer includes silicon oxide, and the etch stop layer is formed by using a CVD process.
Optionally, the thickness of the pad oxide layer is 100 angstroms to 1000 angstroms, and the thickness of the etch stop layer is 2000 angstroms to 7000 angstroms.
Optionally, the step of forming the trench includes: forming a patterned photoresist layer on the etching barrier layer; forming an opening exposing the substrate in the etching barrier layer and the pad oxide layer by taking the patterned photoresist layer as a mask; dry etching the substrate using the opening, and forming the trench in the substrate.
Optionally, the step of forming the shielding gate structure includes: forming a shielding grid dielectric layer which covers the inner wall of the groove and the surface of the etching barrier layer; forming a shielding grid conductive material layer, wherein the shielding grid conductive material layer covers the shielding grid dielectric layer and fills the groove; and etching to remove the shielding gate dielectric layer and the shielding gate conductive material layer with partial thickness, and taking the remaining shielding gate dielectric layer and the shielding gate conductive material layer in the groove as the shielding gate structure.
Optionally, the isolation material layer is made of silicon oxide, and is formed by using an HDP CVD process.
In summary, in the method for manufacturing the shielded gate trench power device according to the present invention, the pad oxide layer on the substrate and the etching stop layer on the pad oxide layer are used as a mask for forming the trench, and the etching rate of the etching stop layer during forming the opening and the trench is equal to or slightly greater than the etching rate of the pad oxide layer (the etching rate ratio may be, for example, 1.1:1 to 1: 1), so as to prevent the etching stop layer from protruding from the pad oxide layer on the sidewall of the trench, thereby reducing or avoiding the overhang problem of the sidewall of the trench. In addition, the surface of the substrate is used as a grinding stop layer, so that an extra grinding stop layer is not required to be formed, the process flow of the shielding grid groove power device is simplified, the filling thickness during forming of the isolation material layer and the thickness of corresponding grinding removal can be reduced, the material cost is saved, and the production efficiency is improved.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention.
Fig. 1a to fig. 1b are schematic diagrams illustrating a conventional trench type power device.
Fig. 2 is a flowchart of a method for forming a trench power device according to an embodiment of the present disclosure.
Fig. 3a to fig. 3h are schematic structural diagrams corresponding to respective steps of a method for forming a trench power device according to an embodiment of the present disclosure.
In fig. 1a to 1 b: a 10' -substrate; 11' -a trench; 12' -overhang; 21' -a silicon oxide layer; 22' -a silicon nitride layer; 23' -a silicon oxide layer.
In fig. 3a to 3 h: 10-a substrate; 10 a-an epitaxial layer; 10 b-a substrate; 11-an opening; 12-a trench;
21-pad oxide layer; 22-etch stop layer;
31-a shielded gate structure; 31 a-a shield gate dielectric layer; 31 b-a shield grid conductive material layer;
32-a layer of isolating material; 33-isolating layer.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are intended to be part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or at least two of the feature unless the content clearly dictates otherwise.
Fig. 2 is a flowchart of a method for manufacturing a shielded gate trench power device according to an embodiment of the present disclosure.
As shown in fig. 2, the method for manufacturing a shielded gate trench power device provided in this embodiment includes:
s01: providing a substrate, wherein a pad oxide layer covers the substrate;
s02: forming an etching barrier layer, wherein the etching barrier layer covers the pad oxide layer;
s03: forming an opening exposing the substrate in the etching barrier layer and the pad oxide layer, forming a groove in the substrate by using the opening, wherein the ratio of the etching rate of the etching barrier layer to the etching rate of the pad oxide layer is 1.1: 1-1: 1 when the opening and the groove are formed by etching;
s04: forming a shielding gate structure in the trench, wherein the shielding gate structure is positioned at the bottom of the trench;
s05: forming an isolation material layer, wherein the isolation material layer covers the shielding gate structure and the etching barrier layer and fills the groove;
s06: and performing a polishing process by taking the surface of the substrate as a polishing stop layer so as to expose the surface of the substrate, wherein when the polishing process is performed, the polishing selection ratio of the pad oxide layer to the substrate is more than 30: 1; and the number of the first and second groups,
s07: and removing part of the thickness of the isolation material layer in the groove, and taking the rest isolation material layer as an isolation layer which is used for isolating the shielding gate structure.
The shielded gate trench power device may be any suitable device such as a shielded gate trench power device with an upper and lower structure and other shielded gate trench power devices with an upper and lower structure. In this embodiment, a shielded gate trench power device with a top-bottom structure is described as an example.
Fig. 3a to 3h are schematic structural diagrams corresponding to respective steps of a method for manufacturing a shielded gate trench power device according to an embodiment of the present application, and next, the method for manufacturing the shielded gate trench power device will be described in detail with reference to fig. 3a to 3 h.
First, referring to fig. 3a, step S01 is performed to provide a substrate 10, wherein the substrate 10 is covered with a pad oxide layer 21.
The substrate 10 may be any suitable substrate 10 known to those skilled in the art, and the material of the substrate 10 may be at least one of the following materials: silicon, gallium nitride, silicon carbide, silicon carbonitride, and the like.
The substrate 10 includes a base 10b and an epitaxial layer 10a formed on the base 10 b. Taking an N-type shielded gate trench power device as an example, the doping types of the substrate 10b and the epitaxial layer 10a are both N-type, and the doping concentration of the substrate 10b is higher than that of the epitaxial layer 10 a.
Taking the substrate 10 as silicon as an example, the pad oxide layer 21 covering the surface of the substrate 10 may be silicon oxide, and a thermal oxidation process is used to form the pad oxide layer 21 with a denser film layer, so as to protect the substrate 10 in the subsequent process and facilitate forming a trench with better morphology. The thickness of the pad oxide layer 21 can be specifically set according to the depth and the aspect ratio of the trench to be formed, and the thickness can be, for example, 100 to 1000 angstroms. In the present embodiment, the depth of the trench to be formed is 3.5 microns and the opening width is 0.85 microns, and the thickness of the pad oxide layer 21 can be 500 angstroms.
Next, referring to fig. 3b, step S02 is performed to form an etch stop layer 22, wherein the etch stop layer 22 covers the pad oxide layer 21.
The etch stop layer 22 and the pad oxide layer 21 may be used as a hard mask for forming a trench later, and the material of the etch stop layer 22 may be any suitable etch stop material, such as silicon oxide or amorphous carbon. It should be noted that, by selecting a suitable material to form the etching stop layer 22, and under a corresponding etching process, the etching rate of the etching stop layer 22 is equal to or slightly greater than the etching rate of the pad oxide layer 21 (the etching rate ratio may be, for example, 1.1:1 to 1: 1), so as to reduce or avoid the overhang problem of the trench sidewall.
Preferably, the material of the etch stop layer 22 is the same as that of the pad oxide layer 21, so that the two layers have the same etch rate and the dimensional stability of the opening width of the trench is also considered. In the present embodiment, the material of the etch stop layer 22 and the pad oxide layer 21 are silicon oxide, and TEOS is used as a silicon source and formed by a CVD process, so as to form the etch stop layer 22 at a faster rate and at a lower cost. Moreover, the etching stop layer 22 can be removed by subsequent grinding easily, so that residues are not easy to generate, and the removal rate is high, thereby being beneficial to reducing the material cost of the grinding process and improving the grinding efficiency (reducing the time cost). Of course, the thickness of the etching stop layer 22 can be determined according to practical situations, and the thickness thereof can be, for example, 2000 to 7000 angstroms. In the present embodiment, the thickness of the etch stop layer 22 may be 5000 angstroms.
It should be appreciated that in the present embodiment, the absence of the silicon nitride layer between the etch stop layer 22 and the pad oxide layer 21 reduces the overall thickness of the hard mask on the substrate 10, which is beneficial for reducing the thickness of the material subsequently filling the trench and the corresponding removal (etch back or polishing) thickness, thereby reducing material consumption and improving efficiency.
Next, referring to fig. 3c and fig. 3d, step S03 is executed to form an opening 11 in the etch stop layer 22 and the pad oxide layer 21 to expose the substrate 10, and form a trench 12 in the substrate 10 by using the opening 11, wherein a ratio of an etching rate of the etch stop layer 22 to an etching rate of the pad oxide layer 21 is 1.1:1 to 1:1 when the opening 11 and the trench 12 are formed by etching.
Specifically, a patterned photoresist layer may be formed on the etching stop layer 22, the etching stop layer 22 and the pad oxide layer 21 are dry-etched by using the patterned photoresist layer to form the opening 11, the patterned first dielectric layer 22 and the pad oxide layer 21 are used as a hard mask, a dry etching process is performed on the substrate 10 in the opening 11, and the trench 12 is formed in the epitaxial layer 10 a.
Taking the pad oxide layer 21 and the etch stop layer 22 as silicon oxide as an example, in the process of forming the opening 11 by etching, the etch stop layer 22 and the pad oxide layer 21 have the same etching rate, so that the sidewall of the formed opening 11 has a better profile, i.e., the sidewall of the opening 11 does not generate overhang (overhang), and the same manner as above is performed when the opening 11 is used to form the trench 12, thereby reducing or avoiding the risk of overhang on the sidewall of the trench 12. In other embodiments, the material of the etching stop layer 22 is different from the material of the pad oxide layer 21, but when the opening 11 and the trench 12 are formed by etching, the etching rate of the etching stop layer 22 is slightly greater than the etching rate of the pad oxide layer 21 (for example, the ratio of the etching rates is 1.1:1 to 1: 1), so as to prevent the etching rate of the etching stop layer 22 from being smaller than the etching rate of the pad oxide layer 21, thereby causing the etching stop layer 22 to protrude (i.e., form an overhang) on the sidewall of the trench 12.
It should be understood that, in contrast to using a silicon nitride layer as a polishing stop layer, in the present embodiment, the surface of the substrate is used as a polishing stop layer, and an additional polishing stop layer is not required, which simplifies the process flow of the shielded gate trench power device and thus reduces the problems, such as overhang, caused by the polishing stop layer. On the other hand, even if the etching rate of the etching stopper layer 22 is slightly larger than that of the silicon nitride layer (i.e., the formed hard mask is slightly softer in etching than the silicon nitride layer), resulting in an increase in the opening width (top) of the opening 11, the opening width (near the substrate surface) of the trench 12 is not affected because the thickness of the etching stopper layer 22 is relatively thick.
Next, referring to fig. 3e, step S04 is performed to form a shield gate structure 31 in the trench 12, where the shield gate structure 31 is located at the bottom of the trench 12.
Specifically, a shielding gate dielectric layer 31a may be formed first, where the shielding gate dielectric layer 31a covers the inner wall of the trench 12 and extends to cover the surface of the etching stop layer 22; then, forming a shielding gate conductive material layer 31b in the trench 12, wherein the shielding gate conductive material layer 31b covers the shielding gate dielectric layer 31a and fills the trench 12; then, the shielding gate conductive material layer 31b and the shielding gate dielectric layer 31a with a certain thickness are etched back, and the shielding gate conductive material layer 31b and the shielding gate dielectric layer 31a remaining in the trench 12 are used as the shielding gate structure 31. The shield gate dielectric layer 31a may be, for example, a silicon oxide layer formed by a thermal oxidation process, and the shield gate conductive material layer 31b may be, for example, polysilicon formed by an LPCVD process.
In the process of forming the shielding gate structure 31, the sidewall of the trench 12 has a better shape, which is beneficial to avoiding void defects when filling the shielding gate conductive material layer, and the shielding gate conductive material layer with a better (more uniform) film quality can be formed in the trench 12, so that the shielding gate structure 31 with a flatter top surface can be formed by etching back, and an isolation layer with a more uniform thickness can be formed in the subsequent process.
Next, referring to fig. 3f, step S05 is performed to form an isolation material layer 32, wherein the isolation material layer 32 covers the shield gate structure 31 and the etch stop layer 22, and fills the trench 12 onto the substrate 10.
The isolation material layer 32 may be, for example, silicon oxide, and may be formed by, for example, an HDP CVD process to facilitate the isolation material layer 32 with better step coverage and filling. It will be appreciated that, due to the better profile (no overhang) of the sidewalls of the trench 12, void defects during the formation of the isolation material layer 32 are avoided, thereby forming the isolation material layer 32 with better (more uniform) film quality in the trench 12.
Next, referring to fig. 3g, step S06 is executed to perform a polishing process with the surface of the substrate 10 as a polishing stop layer to expose the surface of the substrate 10, wherein, when the polishing process is performed, a polishing selection ratio of the pad oxide layer 21 to the substrate 10 is greater than 30: 1.
specifically, taking the substrate 10 as a silicon material and the pad oxide layer 21 as a silicon oxide material as an example, the polishing process may be a chemical mechanical polishing process, and a polishing slurry (slurry) of the polishing process includes ceria suspended particles, silica suspended particles, and the like, so that the pad oxide layer 21 has a larger polishing selection ratio (the polishing selection ratio may be, for example, greater than 30: 1) relative to the substrate 10 when the isolation material layer 32 is polished, thereby removing the etch stop layer 22, the pad oxide layer 21, and the isolation material layer 32 on the surface of the substrate 10, and only retaining the isolation material layer 32 in the trench 12.
In the above process, since the silicon nitride layer (which is used as a polishing stop layer, for example) is not disposed between the pad oxide layer 21 and the etch stop layer 22, not only the efficiency of the polishing process can be improved, but also the consumption of the polishing slurry can be reduced, and the subsequent step of removing the silicon nitride layer can be omitted, thereby simplifying the process flow, improving the production efficiency, and reducing the material cost.
Next, referring to fig. 3h, step S07 is performed to remove a portion of the thickness of the isolation material layer 32 in the trench 12, and use the isolation shielding gate structure 31 and the gate structure (not shown) on the isolation shielding gate structure 31 with the remaining isolation material layer 32 as the isolation layer 33.
Finally, the method for manufacturing the shielded gate trench power device provided in this embodiment may further include other subsequent process steps, such as formation of the gate structure, the source region, the source metal pad layer, and the gate metal pad layer, and other corresponding process steps may also be included in other embodiments of the present application, but the formation of the above steps may be formed by methods commonly used in the art, and details are not described herein.
In summary, in the method for manufacturing the shielded gate trench power device according to the present invention, the pad oxide layer on the substrate and the etching stop layer on the pad oxide layer are used as a mask for forming the trench, and the etching rate of the etching stop layer during forming the opening and the trench is equal to or slightly greater than the etching rate of the pad oxide layer (the etching rate ratio may be, for example, 1.1:1 to 1: 1), so as to prevent the etching stop layer from protruding from the pad oxide layer on the sidewall of the trench, thereby reducing or avoiding the overhang problem of the sidewall of the trench. In addition, the surface of the substrate is used as a grinding stop layer, so that an extra grinding stop layer is not required to be formed, the process flow of the shielding grid groove power device is simplified, the filling thickness during forming of the isolation material layer and the thickness of corresponding grinding removal can be reduced, the material cost is saved, and the production efficiency is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A method for manufacturing a shielded gate trench power device, comprising:
providing a substrate, wherein a pad oxide layer covers the substrate;
forming an etching barrier layer, wherein the etching barrier layer covers the pad oxide layer;
forming an opening exposing the substrate in the etching barrier layer and the pad oxide layer, forming a groove in the substrate by using the opening, wherein the ratio of the etching rate of the etching barrier layer to the etching rate of the pad oxide layer is 1.1: 1-1: 1 when the opening and the groove are formed by etching;
forming a shielding gate structure in the trench, wherein the shielding gate structure is positioned at the bottom of the trench;
forming an isolation material layer, wherein the isolation material layer covers the shielding gate structure and the etching barrier layer and fills the groove;
and performing a polishing process by taking the surface of the substrate as a polishing stop layer to expose the surface of the substrate, wherein the polishing selection ratio of the pad oxide layer to the substrate is more than 30: 1; and the number of the first and second groups,
and removing part of the thickness of the isolation material layer in the groove, and taking the rest isolation material layer as an isolation layer which is used for isolating the shielding gate structure.
2. The method of claim 1, wherein the substrate comprises silicon, and the pad oxide layer comprises silicon oxide.
3. The method of claim 2, wherein said pad oxide layer is formed using a thermal oxidation process.
4. The method of claim 3, wherein the polishing process is a chemical mechanical polishing process, and the slurry of the polishing process comprises ceria suspended particles.
5. The method of claim 1, wherein the etch stop layer is made of the same material as the pad oxide layer.
6. The method of claim 5, wherein the material of the etch stop layer comprises silicon oxide, and the etch stop layer is formed by a CVD process.
7. The method of claim 6, wherein the pad oxide layer has a thickness of 100-1000 angstroms, and the etch stop layer has a thickness of 2000-7000 angstroms.
8. The method of manufacturing a shielded gate trench power device of claim 1 wherein the step of forming the trench comprises:
forming a patterned photoresist layer on the etch stop layer;
forming an opening exposing the substrate in the etching barrier layer and the pad oxide layer by taking the patterned photoresist layer as a mask;
dry etching the substrate using the opening, and forming the trench in the substrate.
9. The method of manufacturing a shielded gate trench power device of claim 8, wherein the step of forming the shielded gate structure comprises:
forming a shielding grid dielectric layer which covers the inner wall of the groove and the surface of the etching barrier layer;
forming a shielding grid conductive material layer, wherein the shielding grid conductive material layer covers the shielding grid dielectric layer and fills the groove;
and etching to remove the shielding gate dielectric layer and the shielding gate conductive material layer with partial thickness, and taking the remaining shielding gate dielectric layer and the shielding gate conductive material layer in the groove as the shielding gate structure.
10. The method of any of claims 1-9, wherein the material of the isolation material layer comprises silicon oxide, and the isolation material layer is formed by an HDP CVD process.
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US7173339B1 (en) * 1998-06-22 2007-02-06 Micron Technology, Inc. Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure
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CN103515215A (en) * 2012-06-28 2014-01-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing fin field effect tube

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US7173339B1 (en) * 1998-06-22 2007-02-06 Micron Technology, Inc. Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure
JP2012004360A (en) * 2010-06-17 2012-01-05 Fuji Electric Co Ltd Method of manufacturing semiconductor device
CN103515215A (en) * 2012-06-28 2014-01-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing fin field effect tube

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