CN114897771A - Neural network-based printed circuit board hole processing quality prediction method - Google Patents

Neural network-based printed circuit board hole processing quality prediction method Download PDF

Info

Publication number
CN114897771A
CN114897771A CN202210333253.5A CN202210333253A CN114897771A CN 114897771 A CN114897771 A CN 114897771A CN 202210333253 A CN202210333253 A CN 202210333253A CN 114897771 A CN114897771 A CN 114897771A
Authority
CN
China
Prior art keywords
neural network
training
network model
hole
parameters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210333253.5A
Other languages
Chinese (zh)
Inventor
郑李娟
严冰
王成勇
欧卓东
黄欣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong University of Technology
Original Assignee
Guangdong University of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong University of Technology filed Critical Guangdong University of Technology
Priority to CN202210333253.5A priority Critical patent/CN114897771A/en
Publication of CN114897771A publication Critical patent/CN114897771A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00Image analysis
    • G06T7/0002Inspection of images, e.g. flaw detection
    • G06T7/0004Industrial image inspection
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/045Combinations of networks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/048Activation functions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/08Learning methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00Indexing scheme for image analysis or image enhancement
    • G06T2207/20Special algorithmic details
    • G06T2207/20081Training; Learning
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00Indexing scheme for image analysis or image enhancement
    • G06T2207/20Special algorithmic details
    • G06T2207/20084Artificial neural networks [ANN]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00Indexing scheme for image analysis or image enhancement
    • G06T2207/30Subject of image; Context of image processing
    • G06T2207/30108Industrial image inspection
    • G06T2207/30141Printed circuit board [PCB]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/30Computing systems specially adapted for manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Health & Medical Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • Biophysics (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Artificial Intelligence (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Biomedical Technology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Health & Medical Sciences (AREA)
  • Quality & Reliability (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

The invention relates to the technical field of circuit board processing, in particular to a printed circuit board hole processing quality prediction method based on a neural network. According to the method, the neural network is utilized to construct a prediction model between factors influencing the hole quality and the hole machining quality requirement, the model is utilized to carry out process simulation to obtain the optimal machining parameters, so that the hole machining of the circuit board meets the quality requirement, the product quality is ensured, and compared with the traditional machining experiment, the method is lower in experiment cost, less in experiment frequency, shorter in period and more accurate in experiment result.

Description

Neural network-based printed circuit board hole processing quality prediction method
Technical Field
The invention relates to the technical field of circuit board processing, in particular to a neural network-based printed circuit board hole processing quality prediction method.
Background
Circuit boards, also known as Printed Circuit Boards (PCBs) or printed circuit boards, are one of the important components in the electronics industry. With the rapid development of information technology, information communication among various devices is developing towards the trend of rapidity, complexity and diversification, and in order to meet the requirements of different devices on the information transmission process, various printed circuit board materials are developed to meet different requirements. In the face of hole processing of printed circuit boards with different material characteristics and different thicknesses, how to select reasonable processing parameters to meet the requirements of high efficiency and high quality becomes a difficult point in processing. At present, a processing experiment is generally performed before batch processing, a proper processing parameter is selected according to a processing result to ensure that the processing of circuit board holes can finally meet the quality requirement, and then the production efficiency is improved on the basis of ensuring the quality requirement.
Disclosure of Invention
In order to solve the problems, the invention provides a printed circuit board hole processing quality prediction method based on a neural network.
The invention is realized by adopting the following scheme:
a printed circuit board hole processing quality prediction method based on a neural network comprises the steps of firstly determining the number of input layers and output layers in a neural network model, designing experiments according to the number of the input layers, carrying out a plurality of experiments to obtain experimental data for hole processing, preprocessing the obtained experimental data, constructing the neural network model, training and verifying the neural network model by using the processed experimental data, simulating processing parameters needing prediction by using the constructed neural network model, and obtaining optimal parameters; the input layer is a factor affecting the quality of the hole, and the output layer is a quality requirement of the processed hole.
Further, the method comprises the following steps:
s1, determining the number of input layers and the number of output layers extending into the neural network model;
s2, designing a full factor experiment according to the number of input layers, and repeatedly carrying out a plurality of experiments to obtain experimental data of the processing quality of the circuit board holes;
s3, preprocessing the acquired experimental data, normalizing the experimental data, and distributing the acquired experimental data into training data and verification data according to a proper proportion;
s4, constructing a neural network model, and determining the number of hidden layers and training parameters;
s5, training the neural network model by using the training data in the S3; completing the construction of a neural network model;
s6, completing the construction of the neural network model; training a neural network model using the training data in S3
S7, inputting the alternative processing parameters of the verification data set to be predicted into the trained and constructed neural network model, and performing verification process simulation on the neural network model to obtain a process simulation output result;
and S8, selecting alternative processing parameters to perform process simulation in the model, and acquiring the optimal processing parameters from the alternative processing parameters according to the output result.
Further, in step S2, after the specific input layer and the specific output layer are determined, the levels of the respective factors are selected according to the input factors, a full factor experiment is performed, the quality of the holes required under different factors and different levels of processing is detected, and the experiment data is obtained after repeating the experiment for several times.
Further, in the step S3, the acquired experimental data is randomly allocated as training data and verification data, where the training data is 70-90% of the experimental data.
Further, the training parameters in step S4 include a node number, a transfer function, a training method, a learning rate, a training number, and a training target.
Furthermore, the transfer function, the training method, the learning rate, the training times and the training target parameter in the training parameters are obtained through multiple simulation experiments, in the results of the multiple simulation experiments, the adjustment of all the training parameters in the results of the multiple simulation experiments needs to meet the requirement of ensuring that gradient explosion or gradient disappearance occurs in the gradient descending process of model training, the running time of the model is shortest in the range meeting the set error, and the optimal training parameters are selected according to the set error results.
Further, in step S5, after the neural network model is trained by using the training data, the neural network model is verified by using the verification data in step S3, and the parameters of the neural network model are adjusted to be within the preset target error range.
Further, in the step S7, after the result of verifying the neural network model is smaller than the acceptable error range, a new processing parameter design experiment needs to be selected to obtain a corresponding experiment result, the accuracy of the neural network model is tested by using the new experiment result, if the test result is smaller than the acceptable error range, the step S8 is continuously executed, and if the test result is not smaller than the acceptable error range, the step S4 is returned to.
Further, in step S5, if it is determined that the training target is not reached after the training and the verification, the process returns to step S4.
Further, the factors affecting the quality of the hole include physical properties of a machining material, a structure and a material of a machining tool, a diameter of the machining tool and machining parameters; the quality requirements of the holes comprise hole quality indexes such as hole wall roughness, hole site precision, burrs, roundness and the like.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the method, the neural network is utilized to construct a prediction model between factors influencing the hole quality and the hole machining quality requirement, the model is utilized to carry out process simulation to obtain the optimal machining parameters, so that the hole machining of the circuit board meets the quality requirement, the product quality is ensured, and compared with the traditional actual machining experiment, the method is lower in experiment cost, less in experiment times, shorter in period and more accurate in experiment result.
2. By utilizing the neural network model, not only can a certain hole quality index of a certain production condition be predicted, but also various hole quality indexes under the condition can be predicted, the hole quality under the certain production condition can be comprehensively evaluated, and the hole machining quality can be further improved.
3. The neural network model can be used for optimizing specific pore quality indexes, only different process simulations are needed, then the production conditions of the specific pore quality indexes are obtained, and repeated experiments are carried out, so that the specific pore quality indexes can be optimized in a targeted manner according to output results.
Drawings
Fig. 1 is a flowchart of a method for predicting the processing quality of a printed circuit board hole based on a neural network according to the present invention.
FIG. 2 is a diagram of a neural network model architecture of the present invention.
Detailed Description
To facilitate an understanding of the invention for those skilled in the art, the invention will be described in further detail below with reference to specific embodiments and the attached drawings.
Referring to fig. 1 to 2, the method for predicting the hole processing quality of the printed circuit board based on the neural network, provided by the invention, comprises the steps of firstly determining the number of input layers and output layers in a neural network model, designing an experiment according to the number of the input layers, carrying out a plurality of experiments to obtain experimental data of hole processing, preprocessing the obtained experimental data to construct the neural network model, training and verifying the neural network model by using the processed experimental data, and simulating processing parameters to be predicted by using the constructed neural network model to obtain optimal parameters.
The input layer is a factor affecting the quality of the hole, and the output layer is a quality requirement of the processed hole. The factors influencing the quality of the hole include physical properties of a machining material, the structure and material of a machining tool, the diameter of the machining tool and machining parameters (such as the rotating speed and the feeding speed of a machine tool), and the quality requirements of the hole include hole quality indexes such as hole wall roughness, hole position precision, burrs, roundness and the like.
The printed circuit board hole processing quality prediction method based on the neural network comprises the following steps:
s1, determining the number of input layers and the number of output layers in the network model, in this embodiment, the number of input layers is 3, and the number of output layers is 2, where the input layers include the drilling speed of the machine tool, the feeding speed, and the number of machining holes (the specific implementation may be set according to actual requirements), and the output layers include the hole wall roughness and the hole site precision (the specific implementation may be set according to actual requirements);
s2, designing an experiment (data for training and verifying a neural network model needs to be ensured to be obtained) according to the number of input layers, repeatedly performing the experiment for a plurality of times, and obtaining the experimental data (namely the data of an output layer) of the processing quality of the circuit board holes after detecting the experimental result;
s3, preprocessing the acquired experimental data, normalizing the experimental data, and distributing the acquired experimental data into training data and verification data, specifically, in this embodiment, a Min-Max Scaling method function is used to normalize a data set (i.e., the experimental data) to 0-1, and a retention method is used to segment each set of data into a training set (training data) and a test set (verification data);
s4, constructing a neural network model, and determining the number of hidden layers and training parameters;
s5, completing the construction of the neural network model;
s6, training the neural network model by using the training data in the S3;
s7, inputting the alternative processing parameters to be predicted into the constructed neural network model, and performing process simulation by using the neural network model to obtain a process simulation output result;
and S8, acquiring the optimal processing parameter from the alternative processing parameters according to the result of the process simulation output, and after the optimal processing parameter is acquired, performing hole processing on the circuit board by using the processing parameter, specifically, after the neural network model is constructed and before a certain hole is processed, only inputting the corresponding factors (the alternative processing parameters and the like) into the neural network model to simulate the processing results of the factors, so that a user can conveniently select the optimal processing parameter according to the simulation result.
In step S2, after the specific input layer and output layer are determined, the levels of the respective factors are selected according to the input factors, full factor experiments are performed, the quality of the holes required for processing under different factors and different levels is detected, and experimental data is obtained after repeating the experiments for several times. In this embodiment, 64 sets of experiments are designed, and the experiments are repeated 3 times, although the number of the specific experimental sets and the number of repeated experiments can be adaptively adjusted according to actual requirements.
In the step S3, the acquired experimental data are randomly distributed into training data and verification data, where the training data is 70-90% of the experimental data, and the verification data is 1-W if the experimental data is W.
The training parameters in step S4 include the number of nodes, transfer function, training method, learning rate, training times, and training target.
Transfer functions, training methods, learning rates, training times and training target parameters in the training parameters are obtained through multiple simulation experiments, and the optimal training parameters are selected according to set error results in the results of the multiple simulation experiments. In this embodiment, the hidden layer number is selected to be 1, and the node number is selected according to an empirical formula, for example
Figure BDA0003575793030000071
Wherein n and m are the number of neurons of the input layer and the output layer respectively, and a is an integer between 0 and 10. According to the known conditions that n is 3 and m is 2, a is 6, the number m of neurons in the hidden layer is determined to be 8, the transfer function is selected to be a sigmoid function, the training method is selected to be a tranlm method, the learning method is a LEARNGDM method, and the learning rate, the training times and the training target are respectively set to be 0.005, 100 and 0.1. Wherein the hidden layer is mainly used for inputtingThe characteristics of the data are abstracted to another dimension space to show more abstract characteristics, belong to a fixed structure of the model, and any function containing continuous mapping from one finite space to another finite space can be fitted when the hidden layer number is 1.
In step S5, after the neural network model is trained by using the training data, the neural network model is verified by using the verification data in step S3, and parameters (parameters include learning rate, learning method, training times, training model, etc.) of the neural network model are adjusted to be within a preset target error range. In this embodiment, the number of neurons in the hidden layer is set to 6 by adjusting the parameters and the method (the adjustment process is adjusted according to the experimental effect by setting different parameters), and the learning rate, the training frequency, and the training target are set to 0.05, 50, and 0.01, respectively.
In step S5, if it is determined that the training target is not reached after the training and the verification, the process returns to S4, where the process returns to S4 to be executed again, and the transfer function, the training method, the learning rate, the training frequency, and the training target parameter need to be reset.
In the step S7, the neural network model is verified, and after the result is smaller than the acceptable error range, a new processing parameter design experiment needs to be selected to obtain a corresponding experiment result, and the new experiment result is used to perform an accuracy test on the neural network model (i.e., whether the neural network model of the component to be tested is accurate and reliable and can be put into use or not), if the test result is smaller than the acceptable error range, the step S8 is continuously executed, and if the test result is not smaller than the acceptable error range, the step S4 is returned to.
According to the method, the neural network is utilized to construct a prediction model between factors influencing the hole quality and the hole machining quality requirement, the model is utilized to carry out process simulation to obtain the optimal machining parameters, so that the hole machining of the circuit board meets the quality requirement, the product quality is ensured, and compared with the traditional actual machining experiment, the method is lower in experiment cost, less in experiment times, shorter in period and more accurate in experiment result. By utilizing the neural network model, not only can a certain hole quality index of a certain production condition be predicted, but also various hole quality indexes under the condition can be predicted, the hole quality under the certain production condition can be comprehensively evaluated, and the hole machining quality can be further improved. The neural network model can be used for optimizing specific pore quality indexes, only different process simulations are needed, then the production conditions of the specific pore quality indexes are obtained, and repeated experiments are carried out, so that the specific pore quality indexes can be optimized in a targeted manner according to output results.
In the description of the present invention, it is to be understood that the indicated orientations or positional relationships are only for convenience in describing the present invention and for simplicity in description, and are not intended to indicate or imply that the indicated devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be construed as limiting the present invention.
Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly, e.g., as meaning permanently attached, removably attached, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
While the invention has been described in conjunction with the specific embodiments set forth above, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims.

Claims (10)

1. A printed circuit board hole processing quality prediction method based on a neural network is characterized by comprising the steps of firstly determining the number of input layers and output layers in a neural network model, designing an experiment according to the number of the input layers, carrying out a plurality of experiments to obtain experimental data of hole processing, preprocessing the obtained experimental data to construct the neural network model, training and verifying the neural network model by using the processed experimental data, simulating processing parameters needing to be predicted by using the constructed neural network model, and obtaining optimal parameters; the input layer is a factor affecting the quality of the hole, and the output layer is a quality requirement of the processed hole.
2. The neural network-based printed circuit board hole processing quality prediction method according to claim 1, comprising the steps of:
s1, determining the number of input layers and the number of output layers in the neural network model;
s2, designing an experiment according to the number of input layers, and repeatedly carrying out a plurality of experiments to obtain experimental data of the processing quality of the circuit board holes;
s3, preprocessing the acquired experimental data, normalizing the experimental data, and distributing the acquired experimental data into training data and verification data;
s4, constructing a neural network model, and determining the number of hidden layers and training parameters;
s5; completing the construction of a neural network model;
s6, training the neural network model by using the training data in S3
S7, inputting the verification data set into the trained neural network model, and verifying the neural network model;
and S8, selecting alternative processing parameters to perform process simulation in the model, and acquiring the optimal processing parameters from the alternative processing parameters according to the output result.
3. The method for predicting the hole processing quality of printed circuit board based on neural network as claimed in claim 2, wherein in step S2, after the specific input layer and output layer are determined, the level of each factor is selected according to the input factors, a full factor experiment is performed, the quality of the required hole processed under different factors and different levels is detected, and the experiment data is obtained after repeating the experiment for several times.
4. The neural network-based printed circuit board hole processing quality prediction method of claim 2, wherein in step S3, the acquired experimental data are randomly allocated as training data and verification data, wherein the training data is 70-90% of the experimental data.
5. The neural network-based printed circuit board hole processing quality prediction method of claim 2, wherein the training parameters in step S4 include node number, transfer function, training method, learning rate, training times, and training goal.
6. The printed circuit board hole processing quality prediction method based on neural network as claimed in claim 5, wherein the transfer function, training method, learning rate, training times and training target parameters in the training parameters are obtained by multiple simulation experiments, the adjustment of all training parameters in the results of multiple simulation experiments needs to meet the requirement of ensuring that gradient explosion or gradient disappearance occurs in the gradient descending process of model training, the running time of the model is shortest in the error range set, and the optimal training parameters are selected according to the error result set.
7. The method of claim 2, wherein in step S5, after the neural network model is trained by the training data, the neural network model is verified by the verification data in step S3, and parameters of the neural network model are adjusted to within a preset target error range.
8. The method as claimed in claim 2, wherein in step S7, the neural network model is verified, and after the result is smaller than the acceptable error range, a new processing parameter design experiment needs to be selected to obtain a corresponding experiment result, the new experiment result is used to perform an accuracy test on the neural network model, if the test result is smaller than the acceptable error range, the step S8 is executed, and if the test result is not smaller than the acceptable error range, the step S4 is executed.
9. The method of claim 1 wherein in step S5, if training and verification are followed by a decision that the training goal has not been reached, then returning to S4.
10. The neural network-based printed circuit board hole processing quality prediction method of claim 1, wherein the factors affecting the hole quality include physical properties of a processing material, structure and material of a processing tool, diameter of the processing tool, and processing parameters; the quality requirements of the holes comprise hole quality indexes such as hole wall roughness, hole site precision, burrs, roundness and the like.
CN202210333253.5A 2022-03-31 2022-03-31 Neural network-based printed circuit board hole processing quality prediction method Pending CN114897771A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210333253.5A CN114897771A (en) 2022-03-31 2022-03-31 Neural network-based printed circuit board hole processing quality prediction method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210333253.5A CN114897771A (en) 2022-03-31 2022-03-31 Neural network-based printed circuit board hole processing quality prediction method

Publications (1)

Publication Number Publication Date
CN114897771A true CN114897771A (en) 2022-08-12

Family

ID=82715835

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210333253.5A Pending CN114897771A (en) 2022-03-31 2022-03-31 Neural network-based printed circuit board hole processing quality prediction method

Country Status (1)

Country Link
CN (1) CN114897771A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116797053A (en) * 2023-08-25 2023-09-22 深圳普菲特信息科技股份有限公司 Chemical production data analysis method, system and medium based on neural network

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116797053A (en) * 2023-08-25 2023-09-22 深圳普菲特信息科技股份有限公司 Chemical production data analysis method, system and medium based on neural network
CN116797053B (en) * 2023-08-25 2023-11-10 深圳普菲特信息科技股份有限公司 Chemical production data analysis method, system and medium based on neural network

Similar Documents

Publication Publication Date Title
US20170061313A1 (en) System and Method for Estimating a Performance Metric
CN108304679A (en) A kind of adaptive reliability analysis method
US10936781B1 (en) Method for setting parameters in design of printed circuit board, device employing method, and non-transitory storage medium
CN109472318A (en) For the method and device of the machine learning model selected characteristic of building
CN114897771A (en) Neural network-based printed circuit board hole processing quality prediction method
CN106777402A (en) A kind of image retrieval text method based on sparse neural network
CN108563895A (en) A kind of interval model modification method considering correlation
Ambasana et al. S-parameter and frequency identification method for ANN-based eye-height/width prediction
CN109615080A (en) Unsupervised model evaluation method, apparatus, server and readable storage medium storing program for executing
CN113904915A (en) Intelligent power communication fault analysis method and system based on Internet of things
CN116306485A (en) Method, system and terminal for establishing digital twin body of circuit board
CN114071014B (en) Method and system for improving imaging precision of IC carrier board circuit pattern
EP4080789A1 (en) Enhanced uncertainty management for optical communication systems
CN113973061A (en) Circuit time delay prediction method and device, terminal equipment and readable storage medium
JPWO2019220481A1 (en) Judgment rule acquisition device, judgment rule acquisition method and judgment rule acquisition program
Liu et al. Self-adaptive lower confidence bound: A new general and effective prescreening method for gaussian process surrogate model assisted evolutionary algorithms
CN108960424A (en) Determination method, apparatus, equipment and the storage medium of triumph neuron
Zhang et al. A fast signal integrity design model of printed circuit board based on monte-carlo tree
Ranjan et al. An Approach to Build Process‐Oriented Basis for Causation‐Based Multivariate SPC and Process Capability Analysis
Krimpenis et al. Balancing multiple criteria in formulation of weighted, single-objective genetic algorithm optimization for CNC machining problems
EP4270236A1 (en) Method and device for providing a recommender system
Romanuke Evolution of expert competences in estimating a finite set of objects by a given comparison scale via pairwise comparison matrices within the space of positive inverse-symmetric matrices
CN113408221A (en) Probe service life prediction method, system, device and storage medium
Sobhgol et al. Processing of data for dependability analysis of wireless communication
CN117807929A (en) Model simulation prediction method and system based on deep learning

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination