CN114884594B - 一种适用于fpga的干扰检测方法 - Google Patents

一种适用于fpga的干扰检测方法 Download PDF

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CN114884594B
CN114884594B CN202210568144.1A CN202210568144A CN114884594B CN 114884594 B CN114884594 B CN 114884594B CN 202210568144 A CN202210568144 A CN 202210568144A CN 114884594 B CN114884594 B CN 114884594B
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李雪迎
王军
周圣堂
陈亚丁
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Abstract

本发明属于通信技术领域,具体的说是一种适用于FPGA的干扰检测方法。本发明结合FPGA流水线处理的优势,解决了基于迭代思想的干扰检测算法不利于FPGA实现的问题,本发明提供的方法不再需要进行迭代,只需遍历一次初始干扰数据集合即可确定干扰检测门限,避免了FPGA实现时每次迭代需遍历所有干扰数据集合的复杂控制逻辑,降低了处理延时和缓存消耗。

Description

一种适用于FPGA的干扰检测方法
技术领域
本发明属于通信技术领域,具体的说是一种适用于FPGA的干扰检测方法。
背景技术
近年来,在万物互联的应用需求推动下,无线通信技术迅猛发展,与之伴随的电磁环境也日益复杂,给信息传输的可靠性和有效性带来了前所未有的挑战。其中,人为恶意干扰信号往往功率较大,形成了对通信信号的功率压制,严重破坏系统传输性能。除“硬抗”干扰以外,通信系统的抗干扰手段都以干扰信号检测为基础,在检测得到时域干扰或频域干扰的位置后,可对通信波形进行重构,使之避开干扰,或采用干扰抑制技术提升通信系统的抗干扰性能。
干扰检测技术包括干扰信号存在性检测和干扰信号在时域或频域上的位置检测,前者是一种二元假设检验问题,用于判断被检信号中是否存在干扰;而后者主要依赖于能量检测(Energy Detection,ED)算法,该算法简单,不需要干扰信号的先验信息,并且对未知信道和衰落具有鲁棒性,但传统的ED算法需要准确获得噪声功率,对噪声较为敏感。为了克服此缺点,连续均值去除(Consecutive Mean Excision,CME)和前向连续均值去除(Forward Consecutive Mean Excision,FCME)算法被相继提出,两种算法均基于迭代的思想,对噪声不再敏感,前者将所有频点作为初始无干扰频点,经过反复迭代从无干扰频点集合中去除干扰频点(Henttu P,Aromaa S.Consecutive mean excision algorithm[C].IEEE International Symposium on Spread Spectrum Techniques and Application,Prague,Czech Republic,2002:450–454);后者将幅值最小的一部分频点作为初始无干扰频点,经过反复迭代从干扰频点集合中去除无干扰频点(Saarnisaari H,HenttuP.Impulse detection and rejection methods for radio systems[C].IEEE MilitaryCommunications Conference,Boston,USA,2003:1126-1131)。干扰检测门限是算法的关键输出,由迭代结束得到的无干扰频点集合决定,检测门限可将采样带宽内的频点划分为无干扰频点集合和干扰频点集合,进一步可估计出噪声功率、干扰功率等参数用于干扰抑制。
干扰检测需要满足高实时性和强稳定性,而现场可编程逻辑门阵列(FieldProgrammable Gate Array,FPGA)具有高性能、低延时、低功耗、可编程的特点,常被应用于通信领域中的数字信号处理,因而可用于干扰信号检测算法的落地(Rodriguez J J,MoureM J.Features,design tools,and application domains of FPGAs[J].IEEETransactions on Industrial Electronics,2007,54(4):1810-1823)。在FPGA中实现上述迭代算法时,需要利用随机存取存储器(Random Access Memory,RAM)不断地读写每次迭代得到的无干扰频点数据,并反复调用累加器、除法器、比较器计算迭代门限,进一步调整干扰频点与无干扰频点集合,迭代结束后得到算法输出的干扰检测门限。
因此,在FPGA中采用CME或FCME算法得到干扰检测门限的方法,面临着迭代运算带来的大量处理延时、复杂控制逻辑和额外缓存消耗等问题。
发明内容
针对上述问题,本发明提出了一种适用于FPGA的干扰检测方法,该方法不再需要进行迭代,能够利用FPGA的流水线处理优势快速确定干扰检测门限进行干扰检测。
本发明的技术方案是:
一种适用于FPGA的干扰检测方法,包括以下步骤:
S1、对接收信号进行采样获得长度为N的采样数据
Figure BDA0003659111970000021
r=[r(0),r(1),…,r(N-1)],计算检测统计量S,具体为:
若进行时域干扰检测,则计算采样数据r的模值或者模方值得到S;
若进行频域干扰检测,则先对采样数据r进行加窗,窗函数选择Hamming窗;将采样数据变换到频域,得到频域数据R=(r0+jq0,r1+jq1,…,rN-1+jqN-1),其中r为实部,q为虚部;最后,计算R的模值得到检测统计量S:
S(k)=|R(k)|,k=0,1,…,N-1
S2、计算干扰检测门限因子TCME为:
TCME=F-1(1-Pf)/E[S(k)]
其中,E[]表示取平均,Pf为干扰检测的虚警概率,C(x)为检测统计量S(k)的分布函数:
Figure BDA0003659111970000031
其中,X为随机变量,x为随机变量X的取值,σ2是高斯噪声的方差。
S3、对检测统计量S由小到大进行排序,得到
Figure BDA0003659111970000032
S4、在遍历初始干扰数据集合之前,根据下式计算排序后所有可能的门限值:
Figure BDA0003659111970000033
S5、确定干扰检测门限DT
将排序得到的序列G的前Qn个检测统计量组成初始无干扰数据集合In,集合中无干扰数据个数
Figure BDA0003659111970000034
η为初始无干扰数据的占比,
Figure BDA0003659111970000035
表示向下取整;
将索引p从初始干扰数据最小索引Qn取值至N-1,将排序后的检测统计量G(p+1)依次与最靠近的门限值GT(p)进行大小比较,若存在p使得G(p+1)≥GT(p),则输出干扰检测门限DT=GT(p);否则,没有干扰存在;
S6、在确定干扰检测门限DT后,按下式找出干扰数据索引集合:
J={k∈{1,2,…,N}|S(k)≥DT}
从而实现干扰检测。
本发明的有益效果为,本发明结合FPGA流水线处理的优势,解决了基于迭代思想的干扰检测算法不利于FPGA实现的问题,本发明提供的方法不再需要进行迭代,只需遍历一次初始干扰数据集合即可确定干扰检测门限,避免了FPGA实现时每次迭代需遍历所有干扰数据集合的复杂控制逻辑,降低了处理延时和缓存消耗。
附图说明
图1是本发明提供的干扰检测门限快速确定方法的FPGA实现结构。
图2是本发明实施例提供的采用本发明方法和FCME算法对PBNJ进行干扰检测的漏检概率仿真结果对比图。
图3是本发明实施例提供的采用本发明方法和FCME算法对PBNJ进行干扰检测的误检概率仿真结果对比图。
具体实施方式
下面结合附图和实施例,详细描述本发明的技术方法。
如图1所示,该发明结合FPGA流水线处理的优势,对检测统计量S进行排序后,利用累加器、除法器和乘法器计算所有可能的门限值,再将排序后的检测统计量G进行延时,与门限值一一对比,不需要进行迭代即可快速确定干扰检测门限,有效降低了时间复杂度和空间复杂度,适用于FPGA实现。
实施例
本例中进行干扰检测的接收信号为加性高斯白噪声(Additive White GaussianNoise,AWGN)信道下的部分频带噪声干扰(Partial Band Noise Jamming,PBNJ),采样点数N=512,信号带宽为5MHz,采用本发明提供的干扰检测门限快速确定方法对接收信号进行干扰检测,实施步骤如下:
S1、计算检测统计量
Figure BDA0003659111970000041
首先对采样数据r进行加窗,窗函数选择Hamming窗;然后,按式
Figure BDA0003659111970000042
k=0,1,…,N-1将采样数据变换到频域,得到频域数据R=(r0+jq0,r1+jq1,…,rN-1+jqN-1);最后,计算R的模值得到检测统计量S:
S(k)=|R(k)|
S2、设定干扰检测的虚警概率Pf=0.01,计算干扰检测门限因子TCME
首先确定检测统计量S(k)的分布情况:当接收信号只有高斯白噪声时,rk~N(0,σ2),qk~N(0,σ2),且rk与qk相互独立,因此
Figure BDA0003659111970000043
服从瑞利分布,于是,检测统计量S(k)的概率密度函数为:
Figure BDA0003659111970000044
S(k)的期望为:
Figure BDA0003659111970000051
分布函数为:
Figure BDA0003659111970000052
因此,由式(4)可得干扰检测门限因子为:
Figure BDA0003659111970000053
当虚警概率Pf=0.01,门限因子TCME=2.4215。
S3、对检测统计量S由小到大进行排序,得到
Figure BDA0003659111970000054
S4、在遍历初始干扰数据集合之前,根据下式计算排序后所有可能的门限值:
Figure BDA0003659111970000055
S5、确定干扰检测门限DT
S51、设置初始无干扰数据的占比η=0.1,于是将排序得到的序列G的前51个检测统计量组成初始无干扰数据集合In
S52、将索引p从初始干扰数据最小索引51取值至511,将排序后的检测统计量G(p+1)依次与最靠近的门限值GT(p)进行大小比较,若存在p使得G(p+1)≥GT(p),则输出干扰检测门限DT=GT(p);否则,没有干扰存在。
S6、在确定干扰检测门限后,按下式找出干扰数据索引集合:
J={k∈{1,2,…,512}|S(k)≥DT}
图2和图3分别为本发明方法与FCME干扰检测算法对PBNJ进行干扰检测时的漏检概率和误检概率仿真结果对比图,PBNJ的带宽因子α=0.2。表1对比了FCME干扰检测算法与本发明方法在FPGA实现时的资源消耗与处理延时,两种算法均在Xilinx Kintex-7系列FPGA的XC7K325T芯片上进行实现,系统时钟为120MHz,FCME干扰检测算法迭代了8次后得到干扰检测门限,由于两种算法均包含排序模块,因此表1没有考虑排序的资源消耗和延时,而是对比两种算法在排序之后确定干扰检测门限所需的资源消耗和延时:
Figure BDA0003659111970000061
可以看到,本发明方法相比FCME算法不再需要缓存资源,并且降低了8倍处理延时。仿真结果以及FPGA实现结果表明,本发明方法与FCME干扰检测算法具有相同的检测性能,但本发明更适宜于FPGA实现。

Claims (1)

1.一种适用于FPGA的干扰检测方法,其特征在于,包括以下步骤:
S1、对接收信号进行采样获得长度为N的采样数据
Figure FDA0003659111960000011
r=[r(0),r(1),…,r(N-1)],计算检测统计量S,具体为:
若进行时域干扰检测,则计算采样数据r的模值或者模方值得到S;
若进行频域干扰检测,则先对采样数据r进行加窗,窗函数选择Hamming窗;将采样数据变换到频域,得到频域数据R=(r0+jq0,r1+jq1,…,rN-1+jqN-1),其中r为实部,q为虚部;最后,计算R的模值得到检测统计量S:
S(k)=|R(k)|,k=0,1,…,N-1
S2、计算干扰检测门限因子TCME为:
TCME=F-1(1-Pf)/E[S(k)]
其中,E[]表示取平均,Pf为干扰检测的虚警概率,F(x)为检测统计量S(k)的分布函数:
Figure FDA0003659111960000012
其中,X为随机变量,x为随机变量X的取值,σ2是高斯噪声的方差;
S3、对检测统计量S由小到大进行排序,得到
Figure FDA0003659111960000013
S4、在遍历初始干扰数据集合之前,根据下式计算排序后所有可能的门限值:
Figure FDA0003659111960000014
S5、确定干扰检测门限DT
将排序得到的序列G的前Qn个检测统计量组成初始无干扰数据集合In,集合中无干扰数据个数
Figure FDA0003659111960000015
η为初始无干扰数据的占比,
Figure FDA0003659111960000016
表示向下取整;
将索引p从初始干扰数据最小索引Qn取值至N-1,将排序后的检测统计量G(p+1)依次与最靠近的门限值GT(p)进行大小比较,若存在p使得G(p+1)≥GT(p),则输出干扰检测门限DT=GT(p);否则,没有干扰存在;
S6、在确定干扰检测门限DT后,按下式找出干扰数据索引集合:
J={k∈{1,2,…,N}|S(k)≥DT}
从而实现干扰检测。
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