CN114884354A - Direct-current power supply conversion control framework capable of being used for boosting or reducing voltage - Google Patents
Direct-current power supply conversion control framework capable of being used for boosting or reducing voltage Download PDFInfo
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- CN114884354A CN114884354A CN202210807982.XA CN202210807982A CN114884354A CN 114884354 A CN114884354 A CN 114884354A CN 202210807982 A CN202210807982 A CN 202210807982A CN 114884354 A CN114884354 A CN 114884354A
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- circuit
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- external interface
- boosting
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1582—Buck-boost converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a direct current power supply conversion control framework for boosting or reducing voltage, which relates to the field of boosting and reducing voltage control, and comprises the following components: the signal feedback module is used for outputting square wave signals with different duty ratios according to the buck-boost voltage; the logic control circuit is used for judging whether voltage is increased or decreased according to the duty ratio of the square wave signal and the voltage increasing and decreasing confirmation circuit, and when the voltage increasing and decreasing are judged to be consistent, the logic control circuit controls the driving circuit to carry out voltage increasing driving or voltage decreasing driving; a step-up/step-down confirmation circuit for confirming whether to perform step-up or step-down; compared with the prior art, the invention has the beneficial effects that: according to the invention, the voltage boosting circuit and the voltage reducing circuit are integrated in the same circuit, the voltage boosting and reducing amplitude is adjustable, voltage boosting and reducing can be completed only by externally connecting a capacitor, an inductor and a power supply, and the wiring of the capacitor, the inductor and the power supply is only required to be changed for converting voltage boosting and reducing, so that the circuit is simple and convenient.
Description
Technical Field
The invention relates to the field of voltage boosting and reducing control, in particular to a direct-current power supply conversion control framework for boosting or reducing voltage.
Background
The voltage boosting circuit can make the output voltage higher than the input voltage, and the voltage reducing circuit can make the output power supply lower than the input voltage.
There are step-up equipment and step-down equipment in the existing market, but lack and carry out unified device with it, cause when needing step-up, step-down switching, often need to change the circuit by a wide margin, it is not convenient enough, need improve.
Disclosure of Invention
The present invention is directed to a dc power conversion control architecture for voltage boosting or voltage dropping, so as to solve the problems mentioned in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
a dc power conversion control architecture that can be used for either step-up or step-down, comprising:
the signal feedback module is used for outputting square wave signals with different duty ratios according to the buck-boost voltage;
the logic control circuit is used for judging whether voltage is increased or decreased according to the duty ratio of the square wave signal and the voltage increasing and decreasing confirmation circuit, and when the voltage increasing and decreasing are judged to be consistent, the logic control circuit controls the driving circuit to carry out voltage increasing driving or voltage decreasing driving;
a step-up/step-down confirmation circuit for confirming whether to perform step-up or step-down;
the time sequence circuit is used for controlling the working time of the logic control circuit so as to change the voltage rising and falling amplitude;
the driving circuit is used for driving voltage boosting or voltage reduction;
an output circuit for outputting a voltage;
the potential selection circuit is used for selecting the wiring condition of the PMOS tube of the output circuit;
the signal feedback module is connected with the logic control circuit, the buck-boost confirming circuit is connected with the logic control circuit, the sequential circuit is connected with the logic control circuit, the logic control circuit is connected with the driving circuit, and the driving circuit is connected with the output circuit.
As a still further scheme of the invention: the signal feedback module comprises:
a reference voltage circuit for acquiring a reference voltage;
a first amplifier U1 for outputting a comparison signal according to a reference voltage and an input signal;
the sawtooth wave signal circuit is used for generating a sawtooth wave signal;
the second amplifier U2 is used for generating a square wave signal according to the comparison signal and the sawtooth wave signal;
the reference voltage circuit is connected with the in-phase end of the first amplifier U1, the inverting end of the first amplifier U1 is connected with the external interface FB, the output end of the first amplifier U1 is connected with the in-phase end of the second amplifier U2, the inverting end of the second amplifier U2 is connected with the sawtooth wave signal circuit, and the output end of the second amplifier U2 is connected with the logic control circuit.
As a still further scheme of the invention: the reference voltage circuit includes:
the band-gap reference source is used for providing a fixed voltage or fixed current;
the reference voltage is used for obtaining a constant voltage according to the fixed voltage or the fixed current and ensuring that the voltage of the non-inverting terminal of the first amplifier U1 is constant;
the band-gap reference source is connected with an external interface VIN, the other end of the band-gap reference source is connected with reference voltage, and the other end of the reference voltage is connected with the in-phase end of the first amplifier U1.
As a still further scheme of the invention: the output circuit comprises a PMOS tube V1 and an NMOS tube V2, the G pole of the PMOS tube V1 is connected with the drive circuit, the G pole of the NMOS tube V2 is connected with the drive circuit, the D pole of the PMOS tube V1 is connected with the D pole of the NMOS tube V2 and the external interface SW, the S pole of the NMOS tube V2 is connected with the external interface GND, and the S pole of the PMOS tube V1 is connected with the external interface VS.
As a still further scheme of the invention: the external circuit comprises a power supply E1, an inductor LOUT and a capacitor COUT during voltage reduction, the negative electrode of the power supply E1 is connected with the negative electrode of the circuit, the positive electrode of the power supply E1 is connected with a reference voltage circuit and an external interface VS, one end of the inductor LOUT is connected with an external interface SW, the other end of the inductor LOUT is connected with the capacitor COUT and the external interface FB, and the other end of the capacitor COUT is connected with the negative electrode of the circuit.
As a still further scheme of the invention: the external circuit comprises a power supply E2, an inductor LOUT and a capacitor COUT during boosting, the negative electrode of the power supply E2 is connected with the negative electrode of the circuit, the positive electrode of the power supply E2 is connected with the inductor LOUT and a reference voltage circuit, the other end of the inductor LOUT is connected with an external interface SW, one end of the capacitor COUT is connected with the negative electrode of the circuit, and the other end of the capacitor COUT is connected with an external interface VS and an external interface FB.
As a still further scheme of the invention: the voltage boosting and reducing confirming circuit is connected with the external interface VS and the external interface SW.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the voltage boosting circuit and the voltage reducing circuit are integrated in the same circuit, the voltage boosting and reducing amplitude is adjustable, voltage boosting and reducing can be completed only by externally connecting a capacitor, an inductor and a power supply, and the wiring of the capacitor, the inductor and the power supply is only required to be changed for converting voltage boosting and reducing, so that the circuit is simple and convenient.
Drawings
Fig. 1 is a schematic diagram of a dc power conversion control architecture for boosting or stepping down.
Fig. 2 is a voltage-reducing schematic diagram of a dc power conversion control architecture that can be used for voltage-increasing or voltage-reducing.
Fig. 3 is a voltage boosting schematic diagram of a dc power conversion control architecture that can be used for voltage boosting or voltage reduction.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the protection scope of the present invention.
Referring to fig. 1, a dc power conversion control architecture for voltage boosting or voltage reducing includes:
the signal feedback module is used for outputting square wave signals with different duty ratios according to the buck-boost voltage;
the logic control circuit is used for judging whether voltage is increased or decreased according to the duty ratio of the square wave signal and the voltage increasing and decreasing confirmation circuit, and when the voltage increasing and decreasing are judged to be consistent, the logic control circuit controls the driving circuit to carry out voltage increasing driving or voltage decreasing driving;
a step-up/step-down confirmation circuit for confirming whether to perform step-up or step-down;
the time sequence circuit is used for controlling the working time of the logic control circuit so as to change the voltage rising and falling amplitude;
the driving circuit is used for driving voltage boosting or voltage reduction;
an output circuit for outputting a voltage;
the potential selection circuit is used for selecting the wiring condition of the PMOS tube of the output circuit;
the signal feedback module is connected with the logic control circuit, the buck-boost confirming circuit is connected with the logic control circuit, the sequential circuit is connected with the logic control circuit, the logic control circuit is connected with the driving circuit, and the driving circuit is connected with the output circuit.
In a specific embodiment: when the external application circuit is determined, the boost-buck confirming circuit judges whether the output circuit is in the boost mode or the buck mode before the output circuit is started, and the FB interface adjusts the duty ratio in the signal feedback module through the logic feedback circuit.
The logic control circuit can be composed of an exclusive nor gate and an MOS (metal oxide semiconductor) tube, wherein the exclusive nor gate is used for processing input signals of the signal feedback module and the buck-boost confirming circuit, and the MOS tube is used for controlling the buck-boost amplitude value according to the sequential circuit.
In this embodiment: referring to fig. 1, the signal feedback module includes:
a reference voltage circuit for acquiring a reference voltage;
a first amplifier U1 for outputting a comparison signal (high level or low level) according to a reference voltage and an input signal;
the sawtooth wave signal circuit is used for generating a sawtooth wave signal;
the second amplifier U2 is used for generating a square wave signal according to the comparison signal and the sawtooth wave signal;
the reference voltage circuit is connected with the in-phase end of the first amplifier U1, the inverting end of the first amplifier U1 is connected with the external interface FB, the output end of the first amplifier U1 is connected with the in-phase end of the second amplifier U2, the inverting end of the second amplifier U2 is connected with the sawtooth wave signal circuit, and the output end of the second amplifier U2 is connected with the logic control circuit.
In a specific embodiment: the voltage of the non-inverting terminal of the amplifier U1 is constant, so that the output terminal of the amplifier U1 can output a high level or a low level to adjust the duty ratio according to the voltage of the external pin FB under different buck-boost conditions, and further the square wave signals with different duty ratios are generated to the logic control circuit through the amplifier U2 and the sawtooth wave signal circuit.
In this embodiment: referring to fig. 1, the reference voltage circuit includes:
the band-gap reference source is used for providing a fixed voltage or fixed current;
the reference voltage is used for obtaining a constant voltage according to the fixed voltage or the fixed current and ensuring that the voltage of the non-inverting terminal of the first amplifier U1 is constant;
the band-gap reference source is connected with an external interface VIN, the other end of the band-gap reference source is connected with reference voltage, and the other end of the reference voltage is connected with the in-phase end of the first amplifier U1.
In a specific embodiment: obtaining constant voltage through resistance voltage division according to the fixed voltage; or a constant voltage is obtained by fixing current flowing through the resistor and acquiring the voltage on the resistor.
In this embodiment: referring to fig. 1, the output circuit includes a PMOS transistor V1 and an NMOS transistor V2, a G-pole of the PMOS transistor V1 is connected to the driving circuit, a G-pole of the NMOS transistor V2 is connected to the driving circuit, a D-pole of the PMOS transistor V1 is connected to a D-pole of the NMOS transistor V2 and the external interface SW, an S-pole of the NMOS transistor V2 is connected to the external interface GND, and an S-pole of the PMOS transistor V1 is connected to the external interface VS.
The MOS transistor V1 is a PMOS transistor, and G is conducted when the voltage is low; the MOS transistor V2 is an NMOS transistor, and G is turned on when the voltage is high.
In this embodiment: referring to fig. 2, the external circuit includes a power source E1, an inductor LOUT, a capacitor COUT during voltage reduction, a negative electrode of the power source E1 is connected to a negative electrode of the circuit, a positive electrode of the power source E1 is connected to the reference voltage circuit and the external interface VS, one end of the inductor LOUT is connected to the external interface SW, the other end of the inductor LOUT is connected to the capacitor COUT and the external interface FB, and the other end of the capacitor COUT is connected to the negative electrode of the circuit.
When the voltage is reduced, the PMOS transistor V1 and the NMOS transistor V2 are indirectly turned on and are in reverse directions with each other (the timing circuit controls the logic control circuit, and further controls the driving circuit, and affects the conduction of the MOS transistors V1 and V2): a potential selection circuit (Well Switch) selects the potential of the pole B of the PMOS to be connected to VS, when a PMOS tube V1 is conducted and an NMOS tube V2 is closed, a power supply E1 stores electric energy for an output inductor LOUT and a capacitor COUT, and the capacitor COUT is charged to enable FB to rise; when the PMOS transistor V1 is turned off and the NMOS transistor V2 is turned on, the output inductor LOUT capacitor COUT releases electric energy, and at this time, COUT is in a discharge state, so that FB falls. The FB interface adjusts the duty ratio through the signal feedback module and the control sequential circuit to complete the operation of the voltage reduction mode.
In this embodiment: referring to fig. 3, the external circuit during boosting includes a power source E2, an inductor LOUT, a capacitor COUT, a negative electrode of the power source E2 connected to the negative electrode of the circuit, a positive electrode of the power source E2 connected to the inductor LOUT and the reference voltage circuit, the other end of the inductor LOUT connected to the external interface SW, one end of the capacitor COUT connected to the negative electrode of the circuit, and the other end of the capacitor COUT connected to the external interface VS and the external interface FB.
When boosting, the PMOS transistor V1 and the NMOS transistor V2 are indirectly turned on and are in reverse directions (the sequential circuit controls the logic control circuit, and further controls the driving circuit, and the conduction of the MOS transistors V1 and V2 is affected): when the NMOS transistor V2 is turned on and the PMOS transistor V1 is turned off, the power supply E1 stores electric energy in the output inductor LOUT, and at this time, the COUT is in a discharge state, so that FB falls; when the NMOS transistor V2 is turned off and the PMOS transistor V1 is turned on, the output inductor LOUT releases electric energy to the capacitor COUT, and the capacitor COUT is charged to raise FB. The FB interface adjusts the duty ratio through the signal feedback module and the control sequential circuit to complete the boosting mode operation. In the process of output voltage rising, when VS potential is lower than VIN, a potential selection circuit (Well Switch) selects the potential of the B pole of the PMOS to be connected with VIN; a potential selection circuit (Well Switch) selects the potential of the B pole of the PMOS to be connected to VS when the potential of VS is higher than VIN.
In this embodiment: the voltage boosting and reducing confirming circuit is connected with the external interface VS and the external interface SW.
During boosting, the voltage at the position of the external interface SW approximate to the VIN is judged before the output circuit is started, and the boosting and reducing confirming circuit judges that boosting is carried out according to the voltage; when the voltage is reduced, the voltage of the external interface SW is lower than the voltage at VIN, and the voltage-reducing confirming circuit judges that the voltage is reduced according to the voltage.
The working principle of the invention is as follows: when the external application circuit is determined, the output circuit judges whether the output circuit is in boosting operation or in reducing operation through the boosting and reducing voltage confirmation circuit before starting, then the FB adjusts the duty ratio through the signal feedback module, the logic control circuit adjusts the output voltage according to the duty ratio of the square wave signal, and the selection circuit (Well Switch) selects the B pole potential of the PMOS to be VS or VIN to avoid the action error of the output circuit.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (7)
1. A DC power conversion control architecture for boosting or stepping down, comprising:
the DC power supply conversion control architecture for boosting or reducing voltage comprises:
the signal feedback module is used for outputting square wave signals with different duty ratios according to the buck-boost voltage;
the logic control circuit is used for judging whether voltage is increased or decreased according to the duty ratio of the square wave signal and the voltage increasing and decreasing confirmation circuit, and when the voltage increasing and decreasing are judged to be consistent, the logic control circuit controls the driving circuit to carry out voltage increasing driving or voltage decreasing driving;
a step-up/step-down confirmation circuit for confirming whether to perform step-up or step-down;
the time sequence circuit is used for controlling the working time of the logic control circuit so as to change the voltage rising and falling amplitude;
the driving circuit is used for driving voltage boosting or voltage reduction;
an output circuit for outputting a voltage;
the potential selection circuit is used for selecting the wiring condition of the PMOS tube of the output circuit;
the signal feedback module is connected with the logic control circuit, the buck-boost confirming circuit is connected with the logic control circuit, the sequential circuit is connected with the logic control circuit, the logic control circuit is connected with the driving circuit, and the driving circuit is connected with the output circuit.
2. The dc power conversion control architecture of claim 1, wherein the signal feedback module comprises:
a reference voltage circuit for acquiring a reference voltage;
a first amplifier U1 for outputting a comparison signal according to a reference voltage and an input signal;
the sawtooth wave signal circuit is used for generating a sawtooth wave signal;
the second amplifier U2 is used for generating a square wave signal according to the comparison signal and the sawtooth wave signal;
the reference voltage circuit is connected with the in-phase end of the first amplifier U1, the inverting end of the first amplifier U1 is connected with the external interface FB, the output end of the first amplifier U1 is connected with the in-phase end of the second amplifier U2, the inverting end of the second amplifier U2 is connected with the sawtooth wave signal circuit, and the output end of the second amplifier U2 is connected with the logic control circuit.
3. The dc power conversion control architecture of claim 2, wherein the reference voltage circuit comprises:
the band-gap reference source is used for providing a fixed voltage or fixed current;
the reference voltage is used for obtaining a constant voltage according to the fixed voltage or the fixed current and ensuring that the voltage of the non-inverting terminal of the first amplifier U1 is constant;
the band-gap reference source is connected with an external interface VIN, the other end of the band-gap reference source is connected with reference voltage, and the other end of the reference voltage is connected with the in-phase end of the first amplifier U1.
4. The architecture of claim 2, wherein the output circuit comprises a PMOS transistor V1 and an NMOS transistor V2, a G electrode of the PMOS transistor V1 is connected to the driving circuit, a G electrode of the NMOS transistor V2 is connected to the driving circuit, a D electrode of the PMOS transistor V1 is connected to a D electrode of the NMOS transistor V2 and the external interface SW, an S electrode of the NMOS transistor V2 is connected to the external interface GND, and an S electrode of the PMOS transistor V1 is connected to the external interface VS.
5. The architecture of claim 4, wherein the external circuit for voltage reduction comprises a power source E1, an inductor LOUT, and a capacitor COUT, a negative terminal of the power source E1 is connected to the negative terminal of the circuit, a positive terminal of the power source E1 is connected to the reference voltage circuit and the external interface VS, one terminal of the inductor LOUT is connected to the external interface SW, the other terminal of the inductor LOUT is connected to the capacitor COUT and the external interface FB, and the other terminal of the capacitor COUT is connected to the negative terminal of the circuit.
6. The DC power conversion control architecture of claim 4, wherein the external circuit comprises a power source E2, an inductor LOUT, a capacitor COUT, a negative electrode of the power source E2 is connected to the negative electrode of the circuit, a positive electrode of the power source E2 is connected to the inductor LOUT and the reference voltage circuit, the other end of the inductor LOUT is connected to the external interface SW, one end of the capacitor COUT is connected to the negative electrode of the circuit, and the other end of the capacitor COUT is connected to the external interface VS and the external interface FB.
7. The DC power conversion control architecture of claim 4, wherein the buck-boost validation circuit is connected to the external interface VS and the external interface SW.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210807982.XA CN114884354A (en) | 2022-07-11 | 2022-07-11 | Direct-current power supply conversion control framework capable of being used for boosting or reducing voltage |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210807982.XA CN114884354A (en) | 2022-07-11 | 2022-07-11 | Direct-current power supply conversion control framework capable of being used for boosting or reducing voltage |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040145360A1 (en) * | 2003-01-24 | 2004-07-29 | Intersil Americas Inc. | Electronic device including multiphase switching regulator and related methods |
| CN101218734A (en) * | 2005-07-15 | 2008-07-09 | 罗姆股份有限公司 | Step-up/down switching regulator, its control circuit, and electronic apparatus using same |
| CN106558986A (en) * | 2015-09-30 | 2017-04-05 | 光宝电子(广州)有限公司 | Combined type electric supply changeover device and its control method |
| CN106602878A (en) * | 2017-02-07 | 2017-04-26 | 北京集创北方科技股份有限公司 | Buck-boost conversion device |
| CN107612333A (en) * | 2017-10-25 | 2018-01-19 | 上海空间电源研究所 | A kind of control circuit and method based on two-tube buck-boost converter |
| CN110380614A (en) * | 2019-08-27 | 2019-10-25 | 禹创半导体(深圳)有限公司 | A kind of DC-DC converter |
| US20200266710A1 (en) * | 2019-02-19 | 2020-08-20 | Upi Semiconductor Corp. | Control circuit of buck-boost converting apparatus and mode switching method of the same |
| CN112865529A (en) * | 2021-01-11 | 2021-05-28 | 成都芯源系统有限公司 | Circuit and method for providing supply voltage for driving circuit in power supply system |
-
2022
- 2022-07-11 CN CN202210807982.XA patent/CN114884354A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040145360A1 (en) * | 2003-01-24 | 2004-07-29 | Intersil Americas Inc. | Electronic device including multiphase switching regulator and related methods |
| CN101218734A (en) * | 2005-07-15 | 2008-07-09 | 罗姆股份有限公司 | Step-up/down switching regulator, its control circuit, and electronic apparatus using same |
| CN106558986A (en) * | 2015-09-30 | 2017-04-05 | 光宝电子(广州)有限公司 | Combined type electric supply changeover device and its control method |
| CN106602878A (en) * | 2017-02-07 | 2017-04-26 | 北京集创北方科技股份有限公司 | Buck-boost conversion device |
| CN107612333A (en) * | 2017-10-25 | 2018-01-19 | 上海空间电源研究所 | A kind of control circuit and method based on two-tube buck-boost converter |
| US20200266710A1 (en) * | 2019-02-19 | 2020-08-20 | Upi Semiconductor Corp. | Control circuit of buck-boost converting apparatus and mode switching method of the same |
| CN110380614A (en) * | 2019-08-27 | 2019-10-25 | 禹创半导体(深圳)有限公司 | A kind of DC-DC converter |
| CN112865529A (en) * | 2021-01-11 | 2021-05-28 | 成都芯源系统有限公司 | Circuit and method for providing supply voltage for driving circuit in power supply system |
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