CN114883485A

CN114883485A - Phase change material layer structure, preparation method thereof and phase change memory

Info

Publication number: CN114883485A
Application number: CN202210355441.8A
Authority: CN
Inventors: 刘峻; 杨红心; 周凌珺
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2022-04-06
Filing date: 2022-04-06
Publication date: 2022-08-09

Abstract

The embodiment of the disclosure discloses a phase change material layer structure, a preparation method thereof and a phase change memory. The phase change material layer structure is applied to a phase change memory; the phase change material layer structure includes: the material of the first material layer is GeTe; a second material layer, the material of the second material layer at least including Ga element and Sb element; the first material layers are alternately stacked with the second material layers.

Description

Phase change material layer structure, preparation method thereof and phase change memory

Technical Field

The embodiment of the disclosure relates to the field of memories, and relates to but is not limited to a phase change material layer structure, a preparation method thereof and a phase change memory.

Background

Phase Change Memory (PCM) is a new type of Memory that uses the large resistance difference between crystalline and amorphous states of Phase Change material to store information. The phase-change material has higher resistance in an amorphous state, and the molecular structure of the phase-change material is in a disordered state; the phase-change material has lower resistance in a crystalline state, the internal molecular structure of the phase-change material is in an ordered state, and the resistance difference between the two states generally reaches 2 orders of magnitude.

Rapid transition of the phase change material between two resistance states (high and low) can be achieved by current-induced joule heating.

The PCM has the advantages of high stability, low power consumption, high storage density, compatibility with a conventional CMOS process, and the like, and thus receives more and more attention from researchers and enterprises. PCM is considered to be one of the most potential next-generation non-volatile memories with its great advantages.

Phase change materials are the core of PCMs, and their performance determines various key technical properties of the PCM. The research on high-performance phase-change materials is a problem which needs to be solved urgently.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a phase change material layer structure, a method for manufacturing the same, and a phase change memory.

In a first aspect, the disclosed embodiments provide a phase change material layer structure, which is applied to a phase change memory; the phase change material layer structure includes:

the material of the first material layer is GeTe;

a second material layer, the material of the second material layer at least including Ga element and Sb element;

the first material layers are alternately stacked with the second material layers.

In some embodiments, the GeTe satisfies the general formula Ge _m Te _n Wherein m and n are any integer.

In some embodiments, the material of the second material layer comprises:

GaSbGe or GaSb.

In some embodiments, the GaSbGe contains a doping element or the GaSb contains a doping element; wherein the doping element comprises at least one of: n element, C element, Si element or O element.

In some embodiments, the number of layers of the first material layer is greater than or equal to 1; the difference between the number of layers of the second material layer and the number of layers of the first material layer is 0 or 1.

In some embodiments, the phase change material layer structure is a superlattice-like structure.

In some embodiments, the superlattice-like structure has the general formula [ first material layer ] _(a) Second material layer _(b) ] _x Wherein a is the single-layer thickness of the first material layer; b is the monolayer thickness of the second material layer; x is the number of alternating periods of a single layer of the first material layer and a single layer of the second material layer.

In a second aspect, embodiments of the present disclosure provide a method for preparing a phase change material layer structure, where the method includes:

alternately forming a stack of first and second material layers;

the material of the first material layer is GeTe; the material of the second material layer at least comprises Ga and Sb elements.

In some embodiments, the second layer of material comprises at least GaSbGe, GaSb, doped GaSbGe, or doped GaSb; wherein the doping element comprises at least one of: n element, C element, Si element or O element.

In a third aspect, an embodiment of the present disclosure provides a phase change memory, including: phase change memory cells arranged in an array; wherein the phase change memory cell comprises:

a lower electrode, an ovonic threshold switch, an intermediate electrode, a phase change material layer structure as described in any of the above embodiments, and an upper electrode stacked in sequence.

In the embodiment of the disclosure, when the material in the GaSb family and the material in the GaSbGe family are not used as phase change materials alone, but are combined with GeTe to be used as composite phase change materials, compared with the case that the material in the GaSb family and the material in the GaSbGe family are used alone, the composite phase change material structure is not easily subjected to temperature change, has high thermal stability, and also has good data retention, and a phase change memory formed by using the composite phase change material can have longer service life and better performance.

Drawings

FIG. 1 is a perspective view of a 3D XPoint memory device;

FIG. 2A is a graph of the resistance of a GaSbGe family material and the resistivity of a GST-225 family material versus temperature;

FIG. 2B is a graph showing the resistance of the GaSbGe family material in the reset state and the set state as a function of the number of erase/write cycles;

FIG. 2C is a graph of ten year data retention and one hundred year data retention of materials within the GaSbGe family;

fig. 3 is a schematic view of a phase change material layer structure according to an embodiment of the disclosure;

fig. 4A is a schematic diagram of a phase change material layer structure according to an embodiment of the disclosure;

fig. 4B is a schematic diagram of another phase change material layer structure according to an embodiment of the disclosure;

fig. 4C is a schematic diagram of yet another phase change material layer structure provided by an embodiment of the disclosure;

fig. 5 is a schematic diagram of a phase change material layer structure of a superlattice-like structure according to an embodiment of the disclosure;

fig. 6 is a schematic diagram of a memory cell array in a phase change memory according to an embodiment of the disclosure.

Detailed Description

To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The basic storage principle of the phase change memory is that voltage or current pulse signals with different widths and heights are applied to a device unit, so that the phase change material is subjected to physical phase change, namely reversible phase change interconversion between a crystalline state (low resistance state) and an amorphous state (high resistance state), and writing ('1') and erasing ('0') of information are realized. The inter-conversion process includes two processes of amorphous transformation from a crystalline state to an amorphous state, which is called an amorphization process (RESET), and crystalline transformation from an amorphous state to a crystalline state, which is called a crystallization process (SET). The information is then read out by measuring and comparing the difference in resistance between the two physical phases, and this non-destructive reading process ensures accurate reading of the information stored in the device cell.

Phase change memories include two-dimensional phase change memories and three-dimensional phase change memories including three-dimensional cross-Point (3D X Point) memories that store data based on a change in resistance of a bulk material property (e.g., in a high resistance state or a low resistance state), which is combined with a stackable cross-Point data access array to enable bit addressing. For example, FIG. 1 shows a perspective view of an exemplary 3D XPoint memory 100. According to some embodiments, the 3D X Point memory 100 has a transistor-less cross-Point architecture that locates memory cells at the intersection of vertical conductors; the vertical conductor here includes Word lines (WL, Word Line) and Bit lines (BL, Bit Line) that perpendicularly intersect each other, and the WL and BL are generally constituted by a Line/space (L/S) of a 20nm/20nm constant width formed after a patterning process. A memory cell is formed at the intersection of the vertical WL and BL. The 3D X Point memory 100 includes a plurality of lower bit lines 111 parallel to each other in the same plane and a plurality of upper bit lines 121 parallel to each other in the same plane above the lower bit lines 111.

The 3D X Point memory 100 further includes a plurality of lower word lines 112 and upper word lines 122 parallel to each other in the same plane between the lower bit lines 111 and the upper bit lines 121 in a vertical direction. As shown in fig. 1, each of the lower bit lines 111 and each of the upper bit lines 121 extends laterally in a bit line direction in a top plan view (parallel to a wafer plane), and each of the lower word lines 112 and the upper word lines 122 extends laterally in a word line direction in a top plan view, each of the lower word lines 112 and the upper word lines 122 being perpendicular to each of the lower bit lines 111 and each of the upper bit lines 121.

As shown in fig. 1, the 3D X Point memory 100 includes a plurality of lower memory cells 110 and a plurality of upper memory cells 120, each lower memory cell 110 being disposed at an intersection of a lower bit line 111 and a corresponding lower word line 112, and each upper memory cell 120 being disposed at an intersection of an upper bit line 121 and a corresponding upper word line 122. Each memory cell 110/120 includes at least a vertically stacked PCM element and a selector. Each memory cell 110/120 stores a single bit of data and can be written to or read from each memory cell 110/120 by varying the voltage applied to a corresponding selector (which replaces the need for a transistor). Each memory cell can be individually accessed by applying a current through the top and bottom conductors (e.g., the respective lower 112 or upper 122 word line and lower 111 or upper 121 bit line) that are in contact with each memory cell. The memory cells in the 3D X Point memory 100 are arranged in a memory array. This design of stacking two sets of WL, BL and memory cells improves bit density.

The performance parameters of the phase change material include a crystal transition temperature (Tx), a Data Retention property (Data Retention), and a ratio of a RESET resistance to a SET resistance (a ratio of a resistance value in an amorphous state to a resistance value in a crystalline state). Generally, higher crystallization transition temperatures are beneficial for improved thermal stability and reduced power consumption. Data retention is used to evaluate the probability of phase change materials in the active region of memory cells in an array causing erroneous data and the desired loss of stored data due to undesired transitions under elevated temperature operation. The higher ratio of the RESET resistance to the SET resistance is favorable for distinguishing amorphous state and crystal of the phase-change material, which is favorable for increasing a Read-Write-Modify (RWM) window of the PCM.

In some embodiments, germanium (Ge), antimony (Sb) and tellurium (Te) -containing phase change memory is usedSynthetic materials (GST), e.g. Ge ₂ Sb ₂ Te ₅ The phase change material is used. However, this material has problems such as low crystal transition temperature and poor data retention.

In some embodiments, a gallium (Ga) and antimony (Sb) containing composite material (GaSb) is used as the phase change material in the phase change memory. This material, though, has a higher Tx and good data retention. But the ratio of its RESET resistance to the SET resistance is much lower than GST, which is detrimental to the PCM read and write erase window. This is mainly due to the phase segregation problem in the GaSb or GaSbGe system, which forms large Sb clusters and hinders the formation of the high RESET resistance state.

The above performance index is specifically analyzed by fig. 2A to 2C.

FIG. 2A is a graph showing a pre-deposited film of GST-225 (curve 121), Ga ₄₆ Sb ₅₄ (curve 122), Ga ₁ Sb ₁ Ge ₁ (curve 123) and the resistivity versus temperature of the doped (e.g., silicon oxide) GaSbGe composition (curve 124). As shown in curve 121, the resistivity of GST-225 begins to drop substantially at a temperature of about 150 ℃. This shows that the crystallization transition temperature of GST-225 is approximately 150 ℃. Ga as shown by curve 122 ₄₆ Sb ₅₄ The resistivity of (A) starts to drop greatly at a temperature of about 250 ℃ and represents Ga ₄₆ Sb ₅₄ The crystallization transition temperature of (a) is about 250 ℃. Ga as shown by curve 123 ₁ Sb ₁ Ge ₁ Begins to drop substantially at a temperature of about 360 ℃, indicating that Ga ₁ Sb ₁ Ge ₁ The crystallization transition temperature of (a) is about 360 ℃. Therefore Ga ₁ Sb ₁ Ge ₁ Is about 210 c higher than the crystalline transition temperature of GST-225, which achieves the desired performance characteristics and improves the data retention at high temperatures.

As shown by curve 124, the resistivity of the doped (e.g., silicon oxide) GaSbGe composition begins to drop significantly at a temperature of 441 ℃, indicating that the crystal transition temperature of the doped (e.g., silicon oxide) GaSbGe composition is about 360 ℃.

FIG. 2B is a schematic representation of a GaSbGe familyFatigue characteristic curves of materials in the family GaSbGe containing Ga _x Sb _y Ge _z (where x, y and z are added in combination to add up to 100%), the materials within the GaSbGe family also include doping elements. The concentrations of Ga, Sb and Ge may be normalized first at this point so that Ga, Sb and Ge increase to 100% in the combination, even when additional elements are added. The concentrations of the additionally added elements are not standardized, given their atomic concentrations, assuming that Ga, Sb and Ge are increased to 100%, the sum of the standardized concentration percentages is therefore greater than 100%. Thus, with added elements, the actual atomic percentages (added to 100%) can be determined by scaling the values of Ga, Sb and Ge by a factor ((100-sum of added elements)/100).

Curve 131 represents the amorphous reset state and curve 132 is used to represent the crystalline set state. As can be seen from FIG. 2B, the fatigue-free repeated erase-write frequency of the GaSbGe family material is as high as 10 ⁸ Next, at 10 ⁸ In the secondary period, the high resistance state and the low resistance state of the material in the GaSbGe family have stable resistance values, and the reliability required by the application of the device using the material in the GaSbGe family is ensured.

Fig. 2C is a graph showing ten-year data retention calculations for materials in the GaSbGe family, whose activation energy may be calculated to be 3.3 eV. At a data failure rate of 0.01%, the ten-year data retention of the material was 220 ℃ and at a data failure rate of 1%, the one-hundred-year data retention of the material was 205 ℃.

Such as Ge ₂ Sb ₂ Te ₅ The phase change material is used. However, this material has problems such as low crystal transition temperature and poor data retention.

The embodiment of the present disclosure provides a phase change material layer structure, as shown in fig. 3, the phase change material layer structure is applied to a phase change memory; the phase change material layer structure includes:

a first material layer 201, wherein the material of the first material layer 201 is GeTe;

a second material layer 202, a material of the second material layer 202 at least including Ga element and Sb element;

the first material layers 201 are alternately stacked with the second material layers 202.

The material of the second material layer 202 at least includes Ga element and Sb element, i.e. any material in GaSb family, and the material of the second material layer 202 may further include other elements, such as Ge element, so the second material layer may further include material in GaSbGe family.

In some embodiments, the positions of the first material layer 201 and the second material layer 202 may also be interchanged.

As can be seen from the above examples, the materials in the GaSb family and the materials in the GaSbGe family have higher crystal transition temperatures and good data retention. However, since such materials tend to have a phase segregation problem, large Sb clusters are formed, which hinders the formation of a high RESET resistance state.

By arranging the first material layer 201 on the upper layer and/or the lower layer of the second material layer 202, the problem of phase segregation of the materials can be solved, and meanwhile, the novel phase change material layer structure consisting of the second material layer 202 and the first material layer 201 simultaneously keeps the advantages of high crystallization transition temperature and good data retention of the materials in the GaSb family and the materials in the GaSbGe family.

The first material layer 201 includes GeTe, and when the material in the GaSb family and the material in the GaSbGe family are not used alone as phase change materials, but are used as composite phase change materials in combination with GeTe, the composite phase change material structure is not easily subjected to temperature change, has high thermal stability, and also has good data retention, a high ratio of RESET resistance to SET resistance, a low RESET current (the high RESET resistance determines that it has a low RESET current, so that it consumes less power), and a high endurance cycle (cycles of erase times).

The first layer material includes a material of GeTe family, which refers to a phase change material including Ge element and Te element, satisfying the general formula Ge _m Te _n (e.g., GeTe and GeTe) ₄ ). Materials of the GeTe family may also incorporate other elements, such as: at least one element of S, N, O, Cu, Si, Au, Al, W, Ga and other elements is used for optimizing the performance of the GeTe family material used for the phase change material.

In some embodiments, the material of the second material layer comprises:

GaSbGe or GaSb.

The GaSbGe family material refers to a phase change material including a Ga element, a Sb element, and a Ge element, in which the sum of the composition ratios of the Ga element, the Sb element, and the Ge element is 1. For example Ga _0.22 Sb _0.29 Ge _0.49 、Ga _0.3 Sb _0.36 Ge _0.34 And Ga _0.21 Sb _0.28 Ge _0.51 . The GaSb family material refers to a phase change material including a Ga element and a Sb element, wherein the sum of the composition ratios of the Ga element and the Sb element is 1. For example Ga _0.4 Sb _0.6 、Ga _0.3 Sb _0.7 And Ga _0.46 Sb _0.54 。

In other embodiments, the atomic weight of each element in the material may be used to represent the respective component, and is not limited herein and is only illustrative.

In the embodiment of the disclosure, the phase-change material layer structure of the embodiment is formed by compounding at least one layer of material of the GeTe family stacked alternately with the material of the GaSbGe family or the material of the GaSb family, so that the problem of phase segregation existing when the GaSb family or the GaSbGe family is used as the phase-change material can be effectively reduced, and the resistance value of the RESET state is improved.

Both the GaSbGe family of materials and the GaSb family of materials may be doped with other elements for optimizing the performance of the GaSbGe family of materials or the GaSb family of materials.

In some embodiments, the number of layers of the first material layer is greater than or equal to 1; the difference between the number of the second material layers and the number of the first material layers is 0 or 1.

When the number of the first material layer 201 in the phase change material layer structure is one, the second material layer may be located above the first material layer and/or below the first material layer, i.e. the first material layer at least needs to be in contact with the second material layer.

When the number of the first material layer in the phase change material layer structure is two or more, the top layer of the phase change material layer structure may be the first material layer or the second material layer, and the bottom layer of the phase change material layer structure may be the first material layer or the second material layer.

Because the first material layers and the second material layers are alternately stacked, the difference between the number of the second material layers and the number of the first material layers is 0 or 1.

Fig. 4A, 4B and 4C are partial schematic views of a phase change material layer structure, as shown in fig. 4A, a top layer is a first material layer 201, a bottom layer is a second material layer 202, and has an alternating period (each of the first material layer 201 and the second material layer 202 may constitute an alternating period)); as shown in fig. 4B, the top layer is a first material layer 201, the bottom layer is a second material layer 202, and has two alternating periods; as shown in fig. 4C, the top layer is the second material layer 202, and the bottom layer is the second material layer 202, i.e. one more second material layer 202 is stacked on two alternate periods. The phase change material layer structure may further include more alternating periods, which are not described in detail herein.

It is understood that the positions of the first material layer 201 and the second material layer 202 are interchangeable, and in fig. 4A, the top layer is the second material layer 202, and the bottom layer is the first material layer 201.

The layer thickness of each of the phase change material layers may be the same as or different from the layer thickness of the other layers.

When the layer thickness of each of the first material layer and the second material layer is on the nanometer scale, the structure of the phase change material layer is a superlattice-like structure.

As shown in fig. 5, a Super Lattice Like Structure (SLL) is composed of first material layers 201 and second material layers 202 alternately stacked. In some embodiments, the first material layer 201 may be a bottom layer. It is understood that the positions of the first material layer 201 and the second material layer 202 are interchangeable, and thus in some embodiments, the second material layer 202 may be a bottom layer.

In one embodiment, the top layer of the superlattice-like structure shown in fig. 5 may be further stacked with a material layer that is identical to the bottom material layer.

Each layer of the phase change material layer structure shown in fig. 5 is nano-scale.

In some embodiments, the structure of the phase change material layers is a superlattice-like structure, and the individual thickness of each first material layer is set to a nm (e.g., 5nm) and the individual thickness of each second material layer is set to b nm (e.g., 6 nm). A layer of the first material and a layer of the second material may be provided as a composite layer. The thickness of one composite layer is (a + b) nanometers (e.g., 5nm +6nm ═ 11 nm). X is the number of alternating periods of the first material layer of a monolayer and the second material layer of a monolayer, for example X may be 4. The expression for such a superlattice structure may be [ GeTe ] ₍₅₎ /GaSb ₍₆₎ ] ₍₄₎ Or [ GeTe ] ₍₅₎ /GaSbGe ₍₆₎ ] ₍₄₎ The thickness was 44 nm.

The individual thickness a of the first material layer and the individual thickness b of the second material layer as well as the number X of alternating periods can be set by the semiconductor device, which is shown in the above embodiments as an example, but not limited thereto.

The embodiment of the disclosure provides a preparation method of a phase change material layer structure, which comprises the following steps:

alternately forming a stack of first and second material layers;

The phase change material layer structure may be prepared by a deposition process or a growth process.

Deposition processes include, but are not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Sputtering (Sputtering), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), or the like.

In some embodiments, the first material layer or the second material layer may be formed by an epitaxial growth process, and the second material layer or the first material layer may be formed by a deposition process or a growth process. Repeating the steps until the phase change material layer structure is manufactured.

In some embodiments, the phase change material layer structure of the superlattice-like structure may be formed by a deposition process. For example by means of sputtering or atomic layer deposition in a deposition process.

In some embodiments, the phase change material layer structure described in the above embodiments may be manufactured by a sputtering system.

The sputtering system includes a chamber, a substrate mounted within the chamber. The first sputtering target includes a material of the GaSb family and a material of the GaSbGe family, and the second sputtering target includes a material of the GeTe family.

The substrate is coupled to a power supply controller that is used to apply the bias voltage during the sputtering process. The applied bias voltage can be direct current, pulsed direct current, radio frequency (radio frequency) and combinations thereof, and can be controlled on and off by a power process controller to coordinate the sputtering process.

Also included within the chamber is a vacuum pump or other device for evacuating the chamber and removing the exhaust gases. In addition, the chamber equipment further comprises a gas source. In one embodiment of the present disclosure, the gas source may be a source of inert gas, which may be argon. The system also includes the ability to dynamically control the flow of gas produced by the gas source, and the flow of different gases can have an effect on different layers formed during sputtering, such as film thickness. A power supply controller for controlling the composition of the deposited layers such that the first material layers and the second material layers are alternately stacked as required by the composition; the material of the first material layer is GeTe; the material of the second material layer comprises at least Ga and Sb elements.

In some embodiments, the second material layer comprises at least GaSbGe, GaSb, doped GaSbGe, or doped GaSb; wherein the doping element comprises at least one of the following: n element, C element, Si element or O element.

Both the GaSbGe family of materials and the GaSb family of materials may be doped with other elements, including at least one of: n element, C element, Si element or O element. For optimizing the properties of a material of the GaSbGe family or of a material of the GaSb family.

In some embodiments, the gas source may comprise a gas for reaction, such as oxygen or nitrogen for addition to the GaSbGe family or GaSb family.

In some embodiments, a GaSbGe-Si or GaSb-Si family of SiOx-doped materials may be formed using GaSbGe-Si or GaSb-Si as a sputtering target with reactive oxygen. Similarly, the sputtering target may be formed doped with SiN by introducing reactive nitrogen gas into the chamber _x Of the family of GaSbGe or of the family of GaSb.

In some embodiments, a Si-doped GaSbGe family material or a GaSb family material may be formed using GaSbGe-Si or GaSb-Si as a sputtering target.

In some embodiments, GaSbGe-Si or GaSb-Si may be used as a sputtering target with a reactive gas comprising oxygen or nitrogen to form a GaSbGe family material or a GaSb family material doped with silicon oxide or nitrogen oxide.

An embodiment of the present disclosure further provides a phase change memory, as shown in fig. 6, the phase change memory includes: a phase change memory cell 500 arranged in an array; wherein the phase change memory cell 500 comprises:

a lower electrode 508, an Ovonic Threshold Switch (OTS) 507, an intermediate electrode 506, a phase change material layer structure 504 as in any of the above embodiments, and an upper electrode 502, which are sequentially stacked.

The phase change material layer structure 504 according to the embodiment of the disclosure may be used in various phase change memories including a two-dimensional phase change memory and a three-dimensional phase change memory.

FIG. 6 is an example of an array of phase change memory cells, including a plurality of phase change memory cells 500, each having a first conductive line 501 above and a second conductive line 509 below. Wherein each phase change memory cell 500 comprises: an upper electrode 502, a phase change material layer structure 504, and a first conductive layer 503 and a second conductive layer 505 located on the upper and lower sides of the phase change material layer structure 504, a middle electrode 506, an ovonic threshold switch 507, and a lower electrode 508. The left and right sidewalls of the phase change material layer structure 504 further include a liner layer 510, a first dielectric layer 511, and a sidewall layer 512.

The material of the first conductive line 501 and the material of the second conductive line 509 may comprise conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

The first conductive line 501 may act as a bit line or a word line; the second conductive line 509 may also function as a word line or a bit line. For example, when the first conductive line 501 functions as a bit line, the second conductive line 509 may function as a word line. The phase change memory cell is used for storing data by performing phase change based on a voltage difference between the first conductive line and the second conductive line.

The materials of the upper electrode 502, the middle electrode 506, and the lower electrode 508 include carbon-containing materials including, but not limited to, amorphous carbon (a-c), carbon nanotubes, or graphene, among others.

The first conductive layer 503 and the second conductive layer 505 may be used to improve the contact sensitivity of the phase change material layer structure 504 with the upper electrode 502 and the middle electrode 506. In some embodiments, the first conductive layer 503 and the second conductive layer 505 may not be used.

The material of the ovonic threshold switch 507 may comprise a chalcogenide material, which may be, for example, Ge-Se, Si-Te, C-Te, B-Te, Ge-Te, Al-Te, Ge-Sb, Bi-Te, As-Te, Sn-Te, Ge-Te-Pb, or Ge-Se-Te, and the like.

The phase change material layer structure 504 may be made of a material including: the material of the first material layer is GeTe; a second material layer, the material of the second material layer at least including a Ga element and a Sb element; the first material layers are alternately stacked with the second material layers.

Each phase change memory cell 500 further includes a first Gap filling layer (Gap Fill)514 therebetween, and sidewalls of the phase change memory cell array further include a second Gap filling layer 513 and a second dielectric layer 515. Examples of the gap filling material used for the gap filling layer include, but are not limited to, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium tellurite (CdTe), zinc sulfide (ZnS), lead sulfide (PbS), and lead selenide (PbSe), and cobalt-based compounds, and any combination thereof.

The first gap filling layer 514 and the second gap filling layer 513 may be made of the same material or different materials.

The material of the second dielectric layer 515 may be an oxide. The material of the first dielectric layer 511 may be the same as or different from that of the second dielectric layer 515.

In some embodiments, the positions of the phase change material layer structure 504 and the ovonic threshold switch 507 may be interchanged.

The phase change memory cell array and the peripheral circuit may constitute a phase change memory.

The phase change memory formed by selecting the phase change material structure of the embodiment of the disclosure also has the advantages of the phase change material structure of the disclosure, namely, the phase change memory is not easy to be changed by temperature, has high thermal stability, and also has good data retention, high ratio of RESET resistance to SET resistance, low RESET current (the high RESET resistance determines the low RESET current at the same time, so that the power consumption of the phase change memory is smaller), and high endurance cycle (the cycle of erasing times).

It should be appreciated that reference throughout this specification to "some embodiments," "one embodiment," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above description is only an embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. The phase change material layer structure is characterized in that the phase change material layer structure is applied to a phase change memory; the phase change material layer structure includes:

the material of the first material layer is GeTe;

2. The phase change material layer structure of claim 1, wherein the GeTe satisfies the general formula Ge _m Te _n Wherein m and n are any integer.

3. The phase change material layer structure of claim 1, wherein the material of the second material layer comprises:

GaSbGe or GaSb.

4. The phase change material layer structure of claim 3, wherein the GaSbGe or the GaSb contains a doping element; wherein the doping element comprises at least one of: n element, C element, Si element or O element.

5. The phase change material layer structure of claim 3, wherein the number of layers of the first material layer is greater than or equal to 1; the difference between the number of the second material layers and the number of the first material layers is 0 or 1.

6. The phase change material layer structure of claim 3, wherein the phase change material layer structure is a superlattice-like structure.

7. The phase change material layer structure of claim 6, wherein the superlattice-like structure has a formula [ first material layer ] _(a) Second material layer _(b) ] _x Wherein a is the single-layer thickness of the first material layer; b is the monolayer thickness of the second material layer; x is a single layer of the first materialA number of alternating periods of layers with a single layer of the second material layer.

8. A method of making a phase change material layer structure, the method comprising:

alternately forming a stack of first and second material layers;

9. The method of claim 8, wherein the second material layer comprises at least GaSbGe, GaSb, doped GaSbGe, or doped GaSb; wherein the doping element comprises at least one of the following: n element, C element, Si element or O element.

10. A phase change memory, comprising: phase change memory cells arranged in an array; wherein the phase change memory cell comprises:

a lower electrode, an Ovonic Threshold Switch (OTS), an intermediate electrode, a phase change material layer structure according to any one of claims 1 to 7, and an upper electrode, which are sequentially stacked.