CN114882938A

CN114882938A - Peripheral circuit, memory, peripheral circuit system, electronic device, test device, and test method

Info

Publication number: CN114882938A
Application number: CN202210557718.5A
Authority: CN
Inventors: 赵祥明
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-05-19
Filing date: 2022-05-19
Publication date: 2022-08-09

Abstract

The embodiment of the disclosure provides a peripheral circuit, a memory, a system, an electronic device, a test device and a method. The peripheral circuit includes: a first counter configured to generate a first count value based on a read enable signal; a second counter configured to generate a second count value based on the data strobe signal; and a comparator having a first input coupled to the output of the first counter and a second input coupled to the output of the second counter, the comparator configured to compare the first count value and the second count value.

Description

Peripheral circuit, memory, peripheral circuit system, electronic device, test device, and test method

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a peripheral circuit, a memory and system, an electronic device, a test device, and a method.

Background

In a memory system including a memory controller and one or more memories, the memory controller may sample Data signals based on rising and/or falling edges of a Data Strobe Signal (DQS). The data strobe signal is used to synchronize data transmission between the memory and the memory controller, facilitating accurate data reading by the memory controller. If a problem occurs in the output of the data strobe signal, the memory controller may not read the data correctly.

Disclosure of Invention

The embodiment of the disclosure provides a peripheral circuit, a memory, a system, an electronic device, a test device and a method.

According to a first aspect of the present disclosure, there is provided a peripheral circuit comprising:

a first counter configured to generate a first count value based on a read enable signal; wherein a signal value of the read enable signal switches between a first signal value and a second signal value, the first count value indicating a number of times the read enable signal switches between the first signal value and the second signal value;

a second counter configured to generate a second count value based on the data strobe signal; wherein the signal value of the data strobe signal switches between a third signal value and a fourth signal value, the second count value indicating a number of times the data strobe signal switches between the third signal value and the fourth signal value; and the number of the first and second groups,

a comparator having a first input coupled to the output of the first counter and a second input coupled to the output of the second counter, the comparator configured to compare the first count value and the second count value.

According to a second aspect of the present disclosure, there is provided a memory comprising:

an array of memory cells;

the peripheral circuitry as described above, coupled to the memory cell array, configured to control the memory cell array.

According to a third aspect of the present disclosure, there is provided a memory system comprising:

a memory as described above configured to store data;

a memory controller, coupled to the memory, configured to control the memory.

According to a fourth aspect of the present disclosure, there is provided an electronic device comprising:

the memory system as described above, the memory system including a memory controller;

a host coupled to the memory controller configured to communicate.

According to a fifth aspect of the present disclosure, there is provided a test apparatus for testing a device including the peripheral circuit as described above, the test apparatus comprising:

a test unit configured to send a test command to the device and receive a test result generated by the device based on the test command; wherein the test result comprises a comparison result output by the comparator;

an analysis unit coupled to the test unit and configured to determine whether there is an abnormality in the peripheral circuit generating the data strobe signal according to the comparison result.

According to a sixth aspect of the present disclosure, there is provided a test method comprising:

generating a first count value based on a read enable signal within a time period for executing a preset command; wherein a signal value of the read enable signal switches between a first signal value and a second signal value, the first count value indicating a number of times the read enable signal switches between the first signal value and the second signal value;

generating a second count value based on the data strobe signal within a time period for executing the preset command; wherein the signal value of the data strobe signal switches between a third signal value and a fourth signal value, the second count value indicating a number of times the data strobe signal switches between the third signal value and the fourth signal value;

comparing the first count value and the second count value.

In the peripheral circuit provided by the embodiment of the disclosure, when the memory executes the preset command, the first counter can count the switching times of the read enable signal during the execution period of the whole preset command to generate a first count value, and the second counter can count the switching times of the data strobe signal during the execution period of the whole preset command to generate a second count value. After the memory executes the preset command, the comparator compares the first count value with the second count value to generate a comparison result. According to the comparison result indicating whether the first count value and the second count value are consistent, whether the data strobe signal is lost or the extra switching condition occurs in the memory can be judged.

In the present disclosure, it may be tested whether the peripheral circuit is able to stably output the data strobe signal in executing any read command or combination sequence including a read command, with greater coverage than testing sequences with a dedicated data strobe signal. Illustratively, a special data strobe signal test sequence can only test the output of the data strobe signal when a specified read command is executed (e.g., reading a specified block of data is executed), whereas in the present disclosure, the output of the data strobe signal can be tested simultaneously when any read command or combination sequence of read commands is executed.

Furthermore, when the peripheral circuit provided by the embodiment of the disclosure is tested, a test sequence specially aiming at data strobe signal output does not need to be written, the test mode is more flexible, and the test time can be shortened. In addition, during testing, the requirement on testing equipment is low, and a common Automatic Test Equipment (ATE), even a field-programmable logic array (FPGA) -based tester can finish testing the data strobe signal output of the memory, so that the compatibility with the existing testing equipment is good. And automatic test equipment supporting the DQS sync function is not necessarily used, so that test costs can be saved.

Drawings

Fig. 1 is a schematic diagram of an electronic device provided by an embodiment of the present disclosure;

fig. 2A and 2B are schematic diagrams of a memory system provided by an embodiment of the disclosure;

FIG. 3 is a schematic circuit diagram of a memory including peripheral circuitry provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a peripheral circuit provided in accordance with yet another embodiment of the present disclosure;

FIG. 6 is a timing diagram of a read operation provided by implementations of the present disclosure;

FIG. 7 is a schematic diagram of a peripheral circuit provided in accordance with yet another embodiment of the present disclosure;

FIG. 8 is a schematic flow chart of a testing method provided by an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a test apparatus provided in an embodiment of the present disclosure.

Detailed Description

The technical solution of the present application is further described in detail with reference to the drawings and specific embodiments of the specification.

In the description of the present application, it is to be understood that the terms "length," "width," "depth," "upper," "lower," "outer," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Fig. 1 is a block diagram of an electronic device provided by an embodiment of the present disclosure. The electronic device 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 1, electronic device 100 may include a host 108 and a memory system 102, memory system 102 having one or more memories 104 and a memory controller 106. Host 108 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. Host 108 is coupled to memory controller 106 and may be configured to send data to memory 104 or receive data from memory 104.

The memory 104 may be any memory in the present disclosure. Such as a non-volatile memory device, or a Dynamic Random Access Memory (DRAM). The non-volatile memory device may include NAND flash memory (e.g., three-dimensional (3D) NAND flash memory, two-dimensional NAND flash memory).

In some embodiments, memory controller 106 is coupled to memory 104 and host 108, and is configured to control memory 104. Memory controller 106 may manage data stored in memory 104 and communicate with host 108. In some embodiments, the memory controller 106 is configured to perform the testing methods provided by embodiments of the present disclosure to test the memory 104.

In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that serves as a data store and enterprise storage array for mobile devices such as smart phones, tablets, laptops, and the like. The memory controller 106 may be configured to control operations of the memory 104, such as read, erase, and program operations.

The memory controller 106 may also be configured to manage various functions with respect to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like.

In some embodiments, memory controller 106 is also configured to process Error Correction Codes (ECC) with respect to data read from memory 104 or written to memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The memory controller 106 and the one or more memories 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of end electronic products.

In one embodiment as shown in FIG. 2A, the memory controller 106 and the single memory 104 may be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. Memory card 202 may also include a memory card connector 204 that couples memory card 202 with a host (e.g., host 108 in FIG. 1).

In another embodiment as shown in fig. 2B, the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 206. SSD 206 can also include an SSD connector 208 that couples SSD 206 with a host (e.g., host 108 in fig. 1). In some embodiments, the storage capacity and/or operating speed of SSD 206 is greater than the storage capacity and/or operating speed of memory card 202.

Fig. 3 is a schematic circuit diagram of a memory 300 including peripheral circuits provided by an embodiment of the present disclosure. Memory 300 may be an example of memory 104 in fig. 1. The memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 can be a NAND memory cell array in which memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown).

In some embodiments, peripheral circuitry 302 is configured to perform the testing methods provided by embodiments of the present disclosure. It is understood that the peripheral circuitry 302 may be configured to perform the testing methods provided by embodiments of the present disclosure in accordance with instructions received from the memory controller 106.

In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within the area of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

In some embodiments, each memory cell 306 is a single level memory cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. As shown in fig. 3, each NAND memory string 308 may include a Source Select Gate (SSG)310 at its source end and a Drain Select Gate (DSG)312 at its drain end. The SSGs 310 and DSGs 312 may be configured to activate selected NAND memory strings 308 (columns of the array) during read and program operations.

In some embodiments, the sources of NAND memory strings 308 in the same block 304 are coupled by the same Source Line (SL)314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same block 304 have an Array Common Source (ACS). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a respective bit line 316, and data can be read from or written to the bit line 316 via an output bus (not shown).

In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor having the DSG 312) or a deselect voltage (e.g., 0V) to the respective DSG 312 via one or more DSG lines 313 and/or by applying a select voltage (e.g., above the threshold voltage of the transistor having the SSG 310) or a deselect voltage (e.g., 0V) to the respective SSG 310 via one or more SSG lines 315.

As shown in fig. 3, the NAND memory strings 308 may be organized into a plurality of blocks 304, each of the plurality of blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is the basic unit of data for an erase operation, i.e., all memory cells 306 on the same block 304 are erased at the same time. To erase the memory cells 306 in a selected block, the source lines 314 coupled to the selected block and unselected blocks in the same plane as the selected block may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, the erase operation may be performed at a half block level, at a quarter block level, or at any suitable fraction of a number of blocks or blocks.

The memory cells 306 of adjacent NAND memory strings 308 may be coupled by word lines 318, the word lines 318 selecting which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, the page 320 being the basic unit of data for a programming operation. The size of a page 320 in bits may be related to the number of NAND memory strings 308 coupled by a word line 318 in one block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a respective page 320 and a gate line coupling the control gates.

Peripheral circuitry 302 may be coupled to memory cell array 301 through bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying voltage and/or current signals to and sensing voltage and/or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

For example, fig. 4 is a schematic diagram of peripheral circuitry provided by an embodiment of the disclosure, where peripheral circuitry 302 includes control logic 512, I/O circuitry (input-output circuitry) 516, page buffer/sense amplifiers 504, column decoder/Bit Line (BL) drivers 506, row decoder/Word Line (WL) drivers 508, voltage generator 510, and data bus 518. It should be understood that in some embodiments, additional peripheral circuitry not shown in fig. 4 may also be included, such as ready/busy control circuitry.

The page buffer/sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, during a read operation, the page buffer/sense amplifier 504 may sense data on bit lines of the memory cell array 301 and buffer the sensed data for output. In some embodiments, the page buffer/sense amplifier 504 may store a page of program data (write data) to be programmed into one or more pages 320 of the memory cell array 301. In some embodiments, the page buffer/sense amplifier 504 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 306 coupled to the selected word line 318. In some embodiments, page buffer/sense amplifier 504 may also sense low power signals from bit line 316 representing data bits stored in memory cells 306 and amplify small voltage swings to recognizable logic levels in a read operation.

The column decoder/bit line driver 504 may be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from a voltage generator 510.

The row decoder/word line drivers 508 may be configured to be controlled by the control logic 512 and to select/deselect the blocks 304 of the memory cell array 301 and to select/deselect the word lines 318 of the blocks 304. The row decoder/word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, row decoder/word line drivers 508 may also select/deselect and drive SSG lines 315 and DSG lines 313.

The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, a source line voltage, an SSG line voltage, a DSG line voltage, and the like to be supplied to the memory cell array 301.

Registers 514 may be coupled to control logic 512 and I/O circuitry 516 and include status, command, and address registers to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit module.

The I/O circuitry 516 may be coupled to the control logic 512 and the register 514, and the I/O circuitry 516 may act as a control buffer, e.g., may buffer control commands received from the memory controller 106 and relay the control commands to the register 514. In one example, I/O circuitry 516 receives status information received from control logic 512 via registers 514 and relays the status information to memory controller 106. The I/O circuitry 516 may also be coupled to the page buffer/sense amplifier 504 via a data bus 518 to write data to the memory cell array 301 via the page buffer/sense amplifier 504 in a write operation or to read data from the memory cell array 301 via the page buffer/sense amplifier 504 in a read operation.

Control logic 512 may be coupled to each of the peripheral circuit modules described above and configured to control the operation of each of the peripheral circuit modules. The control logic 512 receives various control signals, such as a Chip Enable (CE) signal, a Command Latch Enable (CLE) signal, an Address Latch Enable (ALE) signal, a Write Enable (WE) signal, a Read Enable (RE) signal, and the like. In one example, control logic 512 controls I/O circuitry 516 via various control signals to receive control commands from memory controller 106 and relay the control commands to the command and address registers, respectively. In one example, in a read operation, the control logic 512 can control the corresponding peripheral circuit module to operate according to the control command.

In a memory system including a NAND memory, a memory controller samples data signals on DQ [7:0] pins (DQ0 pin, DQ1 pin, … DQ7 pin) based on rising and/or falling edges of a data strobe signal DQS. The switching of the level of the digital strobe signal DQS from a low level to a high level is referred to as a rising edge, and the switching from a high level to a low level is referred to as a falling edge. For example, the memory controller may sample the data on the rising or falling edge of the data strobe signal, i.e., one sample within one signal period. By way of further example, the memory controller may sample data on both the rising and falling edges of the data strobe signal, i.e., two samples in a signal period, with a higher read efficiency than one sample in one signal period.

When the memory controller reads data from the memory, the memory controller sends a Read Enable (RE) signal to the memory, which, upon receiving the Read Enable (RE) signal, prepares the data signals on the DQ [7:0] pins and synchronizes the generation of the toggling data strobe signal on the DQS pin. The memory controller samples the data signals on the DQ [7:0] pins based on the rising and/or falling edges of the data strobe signal. The data strobe signal is used to synchronize data transmission between the memory and the memory controller, facilitating accurate data reading by the memory controller.

If the memory fails to output the data strobe signal due to some faults, or the data strobe signal is not switched between high and low levels (toggle), or the data strobe signal is switched in a delayed manner (toggle), the memory controller will wait for the data strobe signal to switch, which is prone to cause the memory controller to be stuck. Therefore, in the development stage of the memory, sufficient tests are required to ensure that the memory can stably output the data strobe signal during the period of reading data.

Due to the high integration of memory, testing of memory is typically performed by Automatic Test Equipment (ATE). And judging whether the memory has faults or not by comparing whether the data written into the memory is the same as the data read out from the memory or not in the test process.

Some automatic test equipment that supports the data strobe signal synchronization function (DQS sync) can detect whether the memory is outputting the data strobe signal stably. In particular, automatic test equipment supporting the DQS sync function can count the number of times of switching of data strobe signals in the whole test sequence during the test process and compare with the expected number of times of switching of data strobe signals. If the two are not the same, a case is illustrated where the memory experiences a loss of data strobe signal (DQS missing) or extra toggling (DQS extra toggle) during execution of the test sequence. Meaning that the memory cannot stably output the data strobe signal. The higher price of automatic test equipment that supports the DQS sync function results in increased test costs. Also, even if automatic test equipment supporting the DQS sync function is used, a test sequence specially for data strobe signal output needs to be written and cannot be shared with other test sequences. That is, the automatic test equipment cannot test the data strobe signal output synchronously while testing other functions of the memory, which results in limited coverage of test sequences for the data strobe signal output and does not cover all cases where data strobe signals are used.

In view of this, the disclosed embodiment provides a peripheral circuit, as shown in fig. 5, including:

a first counter 601 configured to generate a first count value based on a received read enable signal; the first count value is used for indicating the number of times that the read enable signal is switched between the first signal value and the second signal value;

a second counter 602 configured to generate a second count value based on the received data strobe signal; wherein the signal value of the data strobe signal switches between a third signal value and a fourth signal value, the second count value being used to indicate the number of times the data strobe signal switches between the third signal value and the fourth signal value; and the number of the first and second groups,

a comparator 603, a first input of the comparator 603 being coupled to the output of the first counter 601, a second input of the comparator 603 being coupled to the output of the second counter 602, the comparator 603 being configured to compare said first count value with said second count value.

Illustratively, one of the first signal value and the second signal value is high, and the other is low. The read enable signal switches between a high level and a low level. The first counter 601 counts the number of times the read enable signal switches between a high level and a low level. Specifically, when the read enable signal switches from a high level to a low level, the first count value of the first counter 601 is incremented by one. When the read enable signal switches from low level to high level, the first count value of the first counter 601 is incremented by one.

Illustratively, one of the third signal value and the fourth signal value is high, and the other is low. The data strobe signal is also switched between a high level and a low level. The second counter 602 counts the number of times the data strobe signal switches between a high level and a low level. Specifically, when the data strobe signal is switched from a high level to a low level, the second count value of the second counter 602 is incremented by one, and when the data strobe signal is switched from a low level to a high level, the second count value of the second counter 602 is incremented by one.

Illustratively, the first counter 601 and the second counter 602 are binary counters. Taking the first counter 601 as an example, incrementing the first count value of the first counter 601 by one means incrementing according to a binary system, for example, a bit of the first counter 601 is switched from 0 to 1, or is switched from 1 to 0 and carries. In other embodiments, the first counter 601 and the second counter 602 may also be decimal counters or arbitrary counters.

In some embodiments, the number of bits of the first counter 601 and the second counter 602 may be set to be relatively small. The first counter 601 is automatically zeroed when the first count value reaches the maximum value that the number of bits of the first counter 601 can count up, and starts to count again from zero. Similarly, the second counter 602 is automatically zeroed when the second count value reaches the maximum value that the number of bits of the second counter 602 can count, and starts to count again from zero. Therefore, the occupied space of the counter in the memory is reduced, and the cost is saved.

For example, the first counter 601 and the second counter 602 may adopt a four-bit binary counter.

Here, the comparator 603 compares the received first count value with the second count value, and outputs a comparison result; and the comparison result is used for indicating whether the first count value and the second count value are consistent or not.

In some embodiments, the comparator 603 is specifically configured to: when the second count value does not coincide with the first count value, the comparator 603 outputs a fail signal as a comparison result.

In some embodiments, the comparator 603 can output a pass (pass) signal or a fail (fail) signal as the comparison result. Specifically, the method comprises the following steps:

when the second count value coincides with the first count value, the comparator 603 outputs a pass signal as a comparison result;

when the second count value does not coincide with the first count value, the comparator 603 outputs a fail signal as a comparison result.

From the comparison result output from the comparator 603, it can be determined whether the data strobe signal is lost or extra switching occurs in the memory. If the comparator 603 outputs a pass signal, it indicates that the switching times of the data strobe signal and the read enable signal are the same, and it can be considered that the memory can stably output the data strobe signal. If the comparator 603 outputs a fail signal, it indicates that the switching times of the data strobe signal and the read enable signal are different, indicating that the memory cannot stably output the data strobe signal.

Here, the pass signal and the fail signal may be binary signals 0 or 1. For example, the pass signal may be 0 and the fail signal may be 1, or the pass signal may be 1 and the fail signal may be 0.

FIG. 6 is a timing diagram of a read operation according to an embodiment of the present disclosure. FIG. 6 is a simplified illustration of the memory during a read operation

A pin,

Pin, DQ [7:0]Pin and DQS pin. As shown in FIG. 6, DQ [7:0] through the memory when the memory controller reads data to the memory]The pin sends a read command to the memory. Illustratively, the read command includes: 00h + Address (ADDR) +30 h. After receiving the read command, the memory reads data of the memory cell at the corresponding address and latches the data into the page buffer/sense amplifier.

Here, when the memory reads data of a memory cell at a corresponding address, ready/busy ((C))

) A low signal indicates a busy state. When data is latched to the page buffer/sense amplifier, the ready/busy signal is high indicating a ready state.

The memory controller generates a switched read enable signal (RE) after the ready/busy signal switches from a low level to a high level. As shown in fig. 6, the read enable signal is 1010 … 1010 periodic signal, where 1 is high level and 0 is low level, and the read enable signal switches between high and low levels.

Memory pass through

The pin receives the switched read enable signal and then transmits the data latched on the page buffer/sense amplifier to the I/O circuit through the data bus. For example, the data latched in the page buffer/sense amplifier may be transferred to the I/O circuit when the read enable signal is low-level, and the data latched in the page buffer/sense amplifier may be transferred to the transfer I/O circuit when the read enable signal is high-level, so that the secondary data read operation may be completed within one signal period.

Meanwhile, the memory generates a data strobe signal for toggling after receiving the toggle read enable signal, and transmits the data strobe signal to the DQS output buffer. As shown in FIG. 6, the data strobe signal is 1010 … 1010 periodic 1010 signals, where 1 is high and 0 is low, and the data strobe signal toggles between high and low.

After the memory controller acquires the toggled data strobe signal through the DQS pin, the data signal on the DQ [7:0] pin is read on the rising and falling edges of the data strobe signal.

It can be understood that, in the process of reading data from the memory by the memory controller, if the data strobe signal generated by the memory is not switched for a certain period of time, the data signal will not be read by the memory controller, but the memory controller waits for the data strobe signal to be switched all the time, which is liable to cause the memory controller to be stuck. If the data strobe signal generated by the memory switches more than the read enable signal within a certain period of time, it will cause an error in the data read by the memory controller.

Here, it should be noted that when the test equipment directly tests the memory, the test equipment can act as a memory controller, send a read command or a combined sequence including a read command to the memory, and a read enable signal. The test equipment may also acquire the data strobe signal and read the data signal based on rising and/or falling edges of the data strobe signal.

The peripheral circuit provided by the present disclosure can test whether the memory can stably output the data strobe signal in executing any read command or a combined sequence including the read command. When the memory finishes executing the read command, the first counter 601 can count the switching times of the read enable signal during the whole read command execution period to generate a first count value, and the second counter 602 can count the switching times of the data strobe signal during the whole read command execution period to generate a second count value. When the memory has executed the read command, the comparator 603 may compare the first count value with the second count value. According to the comparison result indicating whether the first count value and the second count value are consistent, whether the data strobe signal is lost or the extra switching condition occurs in the memory can be judged.

The peripheral circuit provided by the embodiment of the disclosure can test whether the memory has the condition of less switching or more switching of the data strobe signal by comparing the switching times of the read enable signal and the data strobe signal. In the present disclosure, it may be tested whether the memory is able to stably output the data strobe signal in executing any read command or a combined sequence including read commands, with greater coverage than a dedicated data strobe signal test sequence. Illustratively, a special data strobe signal test sequence can only test the output of the data strobe signal when a specified read function command is executed (e.g., reading data of a specified block is executed), whereas in the present disclosure, the output of the data strobe signal can be tested simultaneously when any read command or combination sequence of read commands is executed. For example, the output of the test data strobe signal under a read command of reading a specified block, a specified region, or a specified page may be performed. In other words, the present disclosure can test whether the data strobe signal can be stably output under more read commands, and thus, the test result for the data strobe signal output is more reliable.

It will be appreciated that in some embodiments, the test device tests the memory primarily by writing data to the memory, then reading the data and verifying the data. The peripheral circuit provided by the disclosure can test whether the memory can stably output the data strobe signal when executing any read command. In other words, in the disclosure, the peripheral circuit can perform the test of the data strobe signal output while performing other functional tests, and on one hand, the coverage of the data strobe signal test is greatly improved. On the other hand, a test sequence specially aiming at the data strobe signal output does not need to be written, so that the test time can be shortened.

Further, in the present disclosure, the switching times of the read enable signal and the data strobe signal are compared in the memory, and the comparison result is directly output. The test equipment only needs to obtain the comparison result, does not need to obtain the data strobe signal, and does not need to compare the switching times of the data strobe signal and the read enable signal, so that the automatic test equipment which does not support the DQS sync function can also test the data strobe signal output condition of the memory disclosed by the invention. That is, the testing method provided by the present disclosure has a low requirement for testing equipment, a common Automatic Test Equipment (ATE), even a field-programmable logic array (FPGA) -based tester can complete testing of data strobe signal output of a memory, and has good compatibility with existing testing equipment, and testing cost can be saved.

In some embodiments, the peripheral circuit further comprises a result register 604, an input of the result register 604 being coupled to an output of the comparator 603, the result register 604 being configured to store a fail signal when the second count value does not correspond to the first count value.

In some embodiments, the result register 604 is configured to store the comparison result. Specifically, when the second count value is not consistent with the first count value, a fail signal is stored; when the second count value coincides with the first count value, a pass signal is stored.

Illustratively, the result register 604 can store a binary signal 0 or 1 sent by the comparator 603.

After the memory has executed the read command sequence, the test equipment can read the comparison result (0 or 1) stored in the result register 604 to determine whether the memory has lost the data strobe signal or switched the data strobe signal additionally during the execution of the whole read command.

In some embodiments, the first counter 601 comprises a signal input for receiving an enable signal. It should be noted that, the disclosure does not limit to which specific peripheral circuit module the signal input terminal of the first counter 601 is coupled, as long as the signal input terminal of the first counter 601 can obtain the read enable signal.

In some embodiments, the peripheral circuit further includes a first buffer 605, the first buffer 605 configured to buffer the received read enable signal. An output of the first buffer 605 is coupled to a signal input of the first counter 601 for transmitting a read enable signal to the first counter 601.

Here, a first buffer 605 may be coupled to

And (7) a pin.

Memory pass through

The pin receives a read enable signal from a memory controller or test equipment and buffers the read enable signal in a first buffer. Illustratively, first buffer 605 is an RE input buffer (RE input buffer).

A signal input of the first counter 601 is coupled to an output of the first buffer 605 to receive the read enable signal buffered by the first buffer 605.

It will be appreciated that in some embodiments, the signal input of the first counter 601 may also be coupled to

A pin to directly receive a read enable signal from a memory controller or test equipment.

In some embodiments, the control logic 512 is configured to generate a data strobe signal. The control logic 512 may generate a data strobe signal based on the read enable signal.

In some embodiments, an input of the control logic 512 is coupled to an output of the first buffer 605, and the control logic 512 receives a read enable signal from the first buffer 605 and generates a data strobe signal. For example, the data strobe signal starts to switch after a preset delay based on a switching start time point of the read enable signal, which is very short, it can be considered that the data strobe signal starts to switch at the switching start time point of the read enable signal.

It will also be appreciated that the data strobe signal is generated based on the read enable signal. Theoretically, the memory receives the same number of times of switching the read enable signal and the data strobe signal generated by the memory during the period of time for executing the read command, and thus, the present disclosure can determine whether the control logic 512 can stably generate the data strobe signal by comparing the number of times of switching the read enable signal and the data strobe signal.

In some embodiments, the peripheral circuit further comprises a second buffer 607, an input of the second buffer 607 coupled to an output of the control logic 512, the second buffer 607 configured to buffer the data strobe signal.

Here, a second buffer 607 may be coupled to the DQS pin to transmit the data strobe signal to a memory controller or test equipment. Illustratively, the second buffer 607 is a DQS output buffer (DQS output buffer).

It will be appreciated that the second counter 602 is used to count the number of times the data strobe signal is switched, and therefore, a signal input of the second counter 602 may be coupled to an output of the control logic 512 to receive the data strobe signal generated by the control logic 512. The signal input of the second counter 602 may also be coupled to the output of the second buffer 607 to receive the data strobe signal buffered by the second buffer 607.

In some embodiments, the peripheral circuit further comprises a clock source 608, outputs of the clock source 608 are coupled to a clock input of the first counter 601, a clock input of the second counter 602, and a clock input of the comparator 603, respectively, the clock source 608 being configured to generate a clock signal. The first counter is configured to generate a first count value based on the received clock signal and the read enable signal; the second counter is configured to generate a second count value based on the received clock signal and the data strobe signal; the comparator is configured to compare the first count value and the second count value based on the received clock signal, the first count value, and the second count value.

Here, fig. 6 shows

A read enable signal at the pin and a data strobe signal at the DQS pin instead of the read enable signal received by the control logic and the data strobe signal generated by the control logic. It will be appreciated that after the control logic generates the data strobe signal, the data strobe signal will also be transmitted to the DQS pin through at least the second buffer. Therefore, the data strobe signal shown in fig. 6 has a longer delay time with respect to the read enable signal.

In this embodiment, the signal input terminal of the second counter may be coupled to the output terminal of the control logic, and the signal input terminal of the first counter may be coupled to the output terminal of the first buffer, so that the data strobe signal received by the second counter and the read enable signal received by the first counter are switched almost synchronously. Therefore, the second counter 602 and the first counter 601 can synchronously count the switching times of the data strobe signal and the read enable signal to generate a first count value and a second count value, and the comparator 603 can synchronously compare the second count value and the first count value once to monitor whether the control logic can stably output the data strobe signal in real time.

Specifically, as shown in fig. 5, the first counter 601 counts the number of switching times of the read enable signal according to the clock signal, the second counter 602 counts the number of switching times of the data strobe signal according to the same clock signal, and the comparator 603 samples a first count value of the first counter 601 and a second count value of the second counter 602 according to the same clock signal. Therefore, the comparator 603 can compare the number of times of switching of the read enable signal and the strobe signal every time the read enable signal is switched. During the execution of the read command, the comparator 603 outputs a fail signal as a comparison result upon finding that the first count value and the second count value are not identical.

It will be appreciated that during execution of a read command sequence by the memory, the data strobe signal may switch more than the read enable signal once during a first time period and less than the read enable signal once during a second time period different from the first time period. The first count value and the second count value may be the same after the memory has executed the read command sequence, but in practice, the control logic may have the data strobe signal toggle less or more.

In this embodiment, the first counter 601, the second counter 602, and the comparator 603 are synchronized by a clock signal from the same clock source 608. The comparator 603 can compare the switching times of the data strobe signal and the read enable signal every time the read enable signal is switched, and the situation that the data strobe signal is lost or is switched additionally and is not found can not occur. If the comparator 603 outputs a pass signal, it indicates that the data strobe signal is switched correspondingly when the read enable signal is switched, indicating that the memory can stably output the data strobe signal.

It should be noted that, during the execution of the read command sequence, the comparator 603 outputs a fail signal when the first count value and the second count value are inconsistent. When the comparator 603 samples the first count value and the second count value next time, the comparator 603 outputs a fail signal even if both the first count value and the second count value are incremented by one.

Also, the comparator 603 can only switch from a pass signal to a fail signal, and cannot switch from a fail signal to a pass signal. Illustratively, it is only possible to switch from 0 to 1, not from 1 to 0. That is, if the switching times of the data strobe signal is less than the switching times of the read enable signal, the comparator 603 cannot switch from the fail signal to the pass signal even if the switching times of the data strobe signal and the switching times of the read enable signal are the same due to the additional switching of the data strobe signal occurring thereafter after the comparator 603 outputs the fail signal. In other words, the comparator 603 outputs a fail signal in response to the first occurrence of a mismatch between the data strobe signal and the read enable signal. In this way, situations in which the data strobe signal is lost or switched additionally without being discovered can be avoided.

In some embodiments, an input of clock source 608 is coupled to an output of first buffer 605, and clock source 608 is configured to generate a clock signal based on a received read enable signal.

Illustratively, the frequency of the clock signal and the frequency of the read enable signal are the same. That is, the signal period of the clock signal is the same as the signal period of the read enable signal.

As described above, the first counter 601 and the second counter 602 sample the read enable signal and the data strobe signal according to the clock signal. Therefore, the first counter 601 and the second counter 602 may receive the clock signal before or at the same time as the read enable signal and the data strobe signal are received, respectively, so as to prevent counting down the switching times of the read enable signal and the data strobe signal.

In this embodiment, the clock source 608 generates a clock signal based on the read enable signal, and can achieve basic synchronization between the clock signal and the read enable signal, so that the clock signal and the read enable signal almost synchronously reach the first counter 601, and the clock signal reaches the second counter 602 before the data strobe signal, thereby ensuring that the first counter 601 and the second counter 602 can accurately count the switching times of the read enable signal and the data strobe signal, respectively.

Further, it is understood that in some embodiments, the first counter 601 and the second counter 602 are constituted by latches, and the first counter 601 can temporarily store the first count value. Therefore, in the case where the time point at which the data strobe signal is transmitted to the first counter is slightly delayed from the time point at which the read enable signal is transmitted to the second counter (for example, the delay time is less than half a signal period of the read enable signal), the comparator can compare the number of times of switching after the data strobe signal is switched based on the switching of the read enable signal with the number of times of switching of the read enable signal after any switching of the read enable signal.

In some embodiments, the delay time is longer (e.g., greater than half a signal period of the read enable signal) when the data strobe signal is transmitted to the first counter relative to the time the read enable signal is transmitted to the second counter. Here, the reason why the delay time is long may be that a time point at which the data strobe signal starts to switch is long relative to a time point at which the read enable signal starts to switch, or the second counter is connected to the second buffer, resulting in a long delay time of the received data strobe signal. In this case, even when the control logic 512 normally outputs the data strobe signal, the second count value and the first count value cannot be kept consistent. In view of this, this problem can be overcome by providing a delay circuit in the peripheral circuit.

For example, a delay circuit may be added between the first counter 601 and the comparator 603 to delay a time point when the first count value reaches the comparator 603, so that the first count value and the second count value reach the comparator 603 synchronously.

The following detailed description in conjunction with fig. 7 provides a peripheral circuit provided by one implementation of the present disclosure. As shown in fig. 7, the peripheral circuit includes an RE input buffer 705, a control logic 512, a DQS output buffer 707, a page buffer/sense amplifier 504, an I/O circuit 516, a clock source 608, a first counter 601, a second counter 602, a comparator 603, and a P/F register 704.

The input of RE input buffer 705 is coupled to

The pins, the outputs are coupled to control logic 512, first counter 601 and clock source 608. The RE input buffer 705 buffers a read enable signal from a memory controller or a test device and transmits the read enable signal to the control logic 512, the first counter 601, and the clock source 608.

Page buffer/sense amplifier 504 has an input coupled to RE input buffer 705 and an output coupled to I/O circuit 516. The page buffer/sense amplifier 504 transmits a data signal to the I/O circuit 516 according to the received read enable signal.

I/O circuit 516 has inputs coupled to page buffer/sense amplifier 504 and outputs coupled to DQ [7:0] pins. I/O circuitry 516 transmits data signals to a memory controller or test equipment via DQ [7:0] pins.

Control logic 512 has an input coupled to RE input buffer 705 and an output coupled to second counter 602 and DQS output buffer 707. Control logic 512 generates a data strobe signal based on the received read enable signal.

DQS output buffer 707 is coupled to control logic 512 at an input and to the DQS pin at an output. DQS output buffer 707 can buffer and transmit data strobe signals to a memory controller or test equipment through the DQS pin.

Clock source 608 has an input coupled to RE input buffer 705 and an output coupled to first counter 601, second counter 602, and comparator 603. Clock source 608 generates a clock signal based on the received read enable signal.

The first counter 601 has an input coupled to the RE input buffer 705 and the clock source 608 and an output coupled to the comparator 603. The first counter 601 counts the number of times of switching of the read enable signal according to the received clock signal, generates a first count value, and transmits the first count value to the comparator 603.

The second counter 602 has inputs coupled to the control logic 512 and the clock source 608 and an output coupled to the comparator 603. The second counter 602 counts the number of times of switching of the data strobe signal according to the received clock signal, generates a second count value, and transmits the second count value to the comparator 603.

The comparator 603 has an input coupled to the first counter 601, the second counter 602 and the clock source 608 and an output coupled to the P/F register 704. The comparator 603 samples and compares the first count value and the second count value according to the received clock signal, and then transmits the comparison result to the P/F register 704. Specifically, a pass signal is transmitted to the P/F register when the first count value and the second count value coincide, and a fail signal is transmitted to the P/F register when the first count value and the second count value do not coincide. Illustratively, the pass signal is 0 (i.e., low), the fail signal is 1 (i.e., high)

As shown in fig. 7, the RE input buffer 705 receives a read enable signal from a memory controller or a test device and buffers the read enable signal, which is illustratively a high-low level that 101010 … periodically switches. The page buffer/sense amplifier 504 receives the read enable signal, loads data onto the read enable signal to generate a data signal, and transmits the data signal to the I/O circuit 516.

In the process of transmitting the data signal to the I/O circuit 516, the clock source 608 receives the read enable signal to generate a clock signal, and transmits the clock signal to the first counter 601, the second counter 602, and the comparator 603. The first counter 601 receives the read enable signal and the clock signal almost simultaneously, starts counting the number of times of switching of the read enable signal, and transmits a first count value to the comparator 603.

During the transmission of the data signals to I/O circuit 516, control logic 512 receives the read enable signal, generates 101010 … a periodically toggled data strobe signal, and transmits the data strobe signal to DQS output buffer 707 and second counter 602. The memory controller or the test device samples the data signal according to the data strobe signal. The second counter 602 receives the clock signal and the data strobe signal in sequence, starts counting the data strobe signal, and transmits a second count value to the comparator 603. The comparator 603 receives the clock signal, the first count value, and the second count value, compares the first count value and the second count value, and transmits the comparison result to the P/F register 704.

After the read command is executed, the test equipment can read the value (0 or 1) in the P/F register 704 through the memory controller to determine whether the data strobe signal generated by the memory is lost or switched additionally. In some embodiments, the test equipment may also act as a memory controller, sending read commands and read enable signals directly into the memory and directly retrieving the comparison results stored in the P/F register 704. Illustratively, the comparison result may be represented by a low level for a pass signal and a high level for a fail signal.

The present disclosure also provides a test method for testing whether a memory including the above peripheral circuit can stably output a data strobe signal. Fig. 8 is a schematic flowchart of a testing method according to an embodiment of the present disclosure, and as shown in fig. 8, the testing method includes:

s100: generating a first count value based on a read enable signal within a time period for executing a preset command; wherein the signal value of the read enable signal switches between a first signal value and a second signal value, the first count value indicating a number of times the read enable signal switches between the first signal value and the second signal value;

s200: generating a second count value based on the data strobe signal within a time period for executing the preset command; wherein the signal value of the data strobe signal switches between a third signal value and a fourth signal value, the second count value being used to indicate the number of times the data strobe signal switches between the third signal value and the fourth signal value;

s300: the first count value and the second count value are compared.

In some embodiments, the preset command comprises a read command. The preset command may be a sequence of read commands or a combined sequence including read commands.

In some embodiments, step S300 specifically includes:

comparing the first count value with the second count value, and generating a pass signal as a comparison result when the second count value is consistent with the first count value; alternatively, the first and second electrodes may be,

and comparing the first count value with the second count value, and generating a failure signal as a comparison result when the second count value is inconsistent with the first count value.

The test method provided by the present disclosure can test whether the memory can stably output the data strobe signal in the memory executing any read command or a combined sequence including the read command. When the memory finishes executing the read command sequence, the first counter in the memory can count the switching times of the read enable signal in the whole read command execution period to generate a first count value, and the second counter in the memory can count the switching times of the data strobe signal in the whole read command execution period to generate a second count value. When the read command is executed, a comparator in the memory may compare the first count value with the second count value. According to whether the first count value is consistent with the second count value, whether the data strobe signal of the memory is lost or additionally switched can be judged.

It will be appreciated that in some embodiments the way in which the test equipment tests the memory is primarily to write data to the memory and then read that data. The test method provided by the disclosure can test whether the memory can stably output the data strobe signal at any time of reading data. In other words, the test method provided by the disclosure can give consideration to the test of data strobe signal output during other function tests, and on one hand, the coverage rate of the data strobe signal test is greatly improved. On the other hand, a test sequence specially aiming at the data strobe signal output does not need to be written, so that the test time can be shortened.

In the present disclosure, the switching times of the read enable signal and the data strobe signal are compared in the memory, and the comparison result is directly output. The test equipment only needs to obtain the comparison result, does not need to obtain the data strobe signal, and does not need to compare the switching times of the data strobe signal and the read enable signal, so that automatic test equipment supporting the DQS sync function is not required to be used. That is, the testing method provided by the present disclosure has a low requirement for testing equipment, a common Automatic Test Equipment (ATE), even a field-programmable logic array (FPGA) -based tester can complete testing of data strobe signal output of a memory, and is compatible with existing testing equipment, and testing cost can be saved.

In some embodiments, the testing method further comprises:

storing the failure signal;

alternatively, the comparison result is stored, the comparison result comprising a pass signal or a pass signal.

Illustratively, the memory executes the preset command device, and the register in the memory stores the comparison result, so that after the test is finished, the test equipment reads the comparison result in the register.

In some embodiments, the testing method further comprises:

the data strobe signal is generated based on the read enable signal.

In some embodiments, the peripheral circuitry comprises: and the output end of the clock source is respectively coupled to the clock input end of the first counter, the clock input end of the second counter and the clock input end of the comparator, and the clock source is configured to generate a clock signal. Correspondingly, the test method comprises the following steps:

generating a first count value based on a clock signal and a read enable signal within a time period for executing a preset command; wherein the signal value of the read enable signal switches between a first signal value and a second signal value, the first count value indicating a number of times the read enable signal switches between the first signal value and the second signal value;

generating a second count value based on the clock signal and the data strobe signal within a time period for executing the preset command; wherein the signal value of the data strobe signal switches between a third signal value and a fourth signal value, the second count value being used to indicate the number of times the data strobe signal switches between the third signal value and the fourth signal value;

comparing the first count value and the second count value based on the clock signal, the first count value and the second count value; generating a comparison result; wherein the comparison result is used for indicating whether the first count value and the second count value are consistent.

In this embodiment, the first counter, the second counter, and the comparator are synchronized by a clock signal sent by the same clock source. The comparator can sample a first count value of the first counter and a second count value of the second counter according to the clock signal during the execution of the read command, and output a fail signal once the first count value and the second count value are inconsistent. That is, the comparator can compare the switching times of the data strobe signal and the read enable signal every time the read enable signal is switched, and the situation that the data strobe signal is lost or is not found due to extra switching can not occur. If the comparator outputs a pass signal, the data strobe signal is correspondingly switched when the read enable signal is switched, which indicates that the memory can stably output the data strobe signal.

In some embodiments, the testing method further comprises:

based on the read enable signal, a clock signal is generated. Therefore, the frequency of the clock signal is the same as that of the read enable signal, the clock signal and the read enable signal almost synchronously reach the first counter, the clock signal reaches the second counter before the data strobe signal, and the first counter and the second counter can accurately count the switching times of the read enable signal and the data strobe signal respectively.

The present disclosure also provides a test apparatus for testing a device including the above peripheral circuit. As shown in fig. 9, the test apparatus 901 includes: a test unit 902 configured to send a test command to the device and receive a test result generated by the device based on the test command; wherein the test result comprises a comparison result output by the comparator.

In some embodiments, the test device 901 may test a memory system including a memory and a memory controller, and the test device may send a test command to the memory controller and read a comparison result from the memory controller.

In some embodiments, as shown in FIG. 9, the test equipment 901 may also test memory 904 (e.g., a non-volatile memory device). The test device 901 may send test commands directly to the memory 904. Illustratively, the test signals may be applied directly to the pins of the memory 904. In some embodiments, the test unit 902 of the test device 901 may transfer DQ [7:0] to the memory 904]The pins apply a pulse containing address information and command information or a signal wave formed of a plurality of pulses. The test unit 902 may also be directed to the memory 904

The pin applies a read enable signal that switches high and low. The test unit 902 may accept high and low level toggled DQS signals from the DQS pin output of the memory 904 and sample DQ [7:0] based on the data strobe signal]A data signal on a pin.

In some embodiments, the test equipment 901 may also directly retrieve the comparison results stored on the registers in the memory 904. For example, the test apparatus 901 may directly obtain the level of the register output, for example, a low level indicates a pass signal and a high level indicates a fail signal.

In some embodiments, a tester may determine whether there is an abnormality in the control logic that generates the data strobe signal based on the comparison. In further embodiments, the test apparatus 901 further comprises an analyzing unit 903, and the analyzing unit 903 is coupled to the test unit 902 and configured to determine whether an exception exists in the control logic generating the data strobe signal according to the comparison result. Illustratively, the analyzing unit 903 is specifically configured to:

when the comparison result indicates that the first count value and the second count value are consistent, determining that the control logic is not abnormal;

and when the comparison result indicates that the first count value and the second count value are not consistent, determining that the control logic is abnormal.

In this embodiment, the test equipment can give consideration to the test of data strobe signal output during other function tests, so that the coverage rate of the data strobe signal test is greatly improved on the one hand. On the other hand, a test sequence specially aiming at the data strobe signal output does not need to be written, so that the test time can be shortened. In the present disclosure, the switching times of the read enable signal and the data strobe signal are compared in the memory, and the comparison result is directly output. The test equipment only needs to obtain the comparison result, does not need to obtain the data strobe signal, and does not need to compare the switching times of the data strobe signal and the read enable signal, so that automatic test equipment supporting the DQS sync function is not required to be used. That is, the testing method provided by the present disclosure has no high requirement for testing equipment, and a common Automatic Test Equipment (ATE), even a field-programmable logic array (FPGA) -based tester, can complete testing of data strobe signal output of a memory, thereby saving testing cost.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A peripheral circuit, comprising:

2. The peripheral circuit of claim 1, wherein the comparison appliance is configured to:

when the second count value is consistent with the first count value, outputting a pass signal;

and outputting a failure signal when the second count value is inconsistent with the first count value.

3. The peripheral circuit of claim 2, further comprising:

a result register having an input coupled to an output of the comparator, the result register configured to: storing the failure signal when the second count value is not consistent with the first count value.

4. The peripheral circuit of claim 1, further comprising:

a first buffer, an output of the first buffer coupled to a signal input of the first counter, the first buffer configured to buffer the read enable signal;

a control logic having an input coupled to an output of the first buffer, the control logic configured to generate the data strobe signal according to the read enable signal.

5. The peripheral circuit of claim 4, further comprising:

a second buffer having an input coupled to the control logic, the second buffer configured to buffer the data strobe signal;

wherein an output of the second buffer is coupled to a signal input of the second counter; alternatively, the output of the control logic is coupled to a signal input of the second counter.

6. The peripheral circuit of claim 4, further comprising:

a clock source having an output coupled to the clock input of the first counter, the clock input of the second counter, and the clock input of the comparator, respectively, the clock source configured to generate a clock signal;

the first counter is configured to generate the first count value based on the clock signal and the read enable signal; a second counter configured to generate the second count value based on the clock signal and the data strobe signal; the comparator is configured to compare the first count value and the second count value based on the clock signal, the first count value, and the second count value.

7. The peripheral circuit of claim 6,

an input of the clock source is coupled to an output of the first buffer, the clock source configured to generate the clock signal based on the read enable signal.

8. A memory, comprising:

an array of memory cells;

the peripheral circuitry of any of claims 1 to 7, coupled to the memory cell array, the peripheral circuitry configured to control the memory cell array.

9. A memory system, comprising:

the memory of claim 8;

a memory controller coupled to the memory configured to control the memory.

10. An electronic device, comprising:

the memory system of claim 9, the memory system comprising a memory controller;

a host coupled to the memory controller configured to communicate.

11. A test apparatus for testing a device including a peripheral circuit as claimed in any one of claims 1 to 7, the test apparatus comprising:

12. The test apparatus of claim 11, wherein the analysis unit is specifically configured to:

determining that there is no abnormality in the peripheral circuit when the comparison result indicates that the first count value and the second count value are consistent;

when the comparison result indicates that the first count value and the second count value are inconsistent, determining that the peripheral circuit has an abnormality.

13. A method of testing, comprising:

comparing the first count value and the second count value.

14. The method of claim 13, wherein comparing the first count value to the second count value comprises:

generating a pass signal when the second count value is consistent with the first count value;

generating a fail signal when the second count value is not consistent with the first count value.

15. The testing method of claim 14, further comprising:

storing the failure signal.

16. The testing method of claim 13, further comprising:

the data strobe signal is generated based on the read enable signal.

17. The test method of claim 13, wherein the peripheral circuit comprises: a clock source having an output coupled to the clock input of the first counter, the clock input of the second counter, and the clock input of the comparator, respectively, the clock source configured to generate a clock signal;

the generating a first count value based on a read enable signal includes: generating a first count value based on the clock signal and a read enable signal;

generating a second count value based on the data strobe signal, comprising: generating a second count value based on the clock signal and the data strobe signal;

the comparing the first count value and the second count value based on the first count value and the second count value includes: comparing the first count value and the second count value based on the clock signal, the first count value, and the second count value.

18. The testing method of claim 17, further comprising:

the clock signal is generated based on the read enable signal.

19. The method of claim 13, wherein the preset command comprises a read command.