CN114879832A - Power consumption control method, device, chip, device and medium for computing device - Google Patents

Abstract

The present disclosure provides a power consumption control method, device, chip, device and medium for a computing device, and relates to the field of computer technology, in particular to the field of chip technology and artificial intelligence. The implementation scheme is: obtaining a first number of data request signals in a power consumption evaluation period, wherein the power consumption evaluation period includes a first preset number of consecutive multiple operation cycles, and the data request signal is used to request input data of the operation device ; based on the first number, obtain the average power consumption characteristic value of the computing device in the power consumption evaluation period; based on the average power consumption characteristic value and the preset power consumption threshold, obtain the power consumption evaluation result in the power consumption evaluation period; and based on the power consumption evaluation period Adjust the operating frequency of the computing device according to the power consumption evaluation result.

Description

Power consumption control method, device, chip, device and medium for computing device

technical field

The present disclosure relates to the field of computer technology, in particular to the field of chip technology and artificial intelligence, and in particular to a power consumption control method, device, electronic device, computer-readable storage medium and computer program product for a computing device.

Background technique

With the development of artificial intelligence technology, more and more applications based on artificial intelligence technology have achieved results far exceeding traditional algorithms; deep learning is the core technology of artificial intelligence technology at present. Deep learning is a data-intensive algorithm and a computationally-intensive algorithm, and it is also an algorithm with rapid iterative development.

Traditional general-purpose processing devices such as CPU, GPU, and DSP are designed for general-purpose computing tasks. When dealing with deep learning applications, there are disadvantages such as low computing performance and low efficiency, which cannot effectively support the large-scale deployment of deep learning algorithms in data centers and other scenarios. The ASIC/FPGA-based deep learning acceleration device can deeply customize the hardware structure according to the computing characteristics of deep learning. Compared with traditional CPU, GPU, DSP and other devices, it can achieve higher computing performance and computing efficiency.

The approaches described in this section are not necessarily approaches that have been previously conceived or employed. Unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section. Similarly, unless otherwise indicated, the issues raised in this section should not be considered to be recognized in any prior art.

SUMMARY OF THE INVENTION

The present disclosure provides a power consumption control method, an apparatus, an electronic device, a computer-readable storage medium, and a computer program product for a computing device.

According to an aspect of the present disclosure, there is provided a power consumption control method for a computing device, comprising: acquiring a first number of data request signals in a power consumption evaluation period, wherein the power consumption evaluation period includes a first preset number The data request signal is used to request the input data of the computing device; based on the first number, the average power consumption characteristic value of the computing device in the power consumption evaluation period is obtained; based on the average power consumption characteristic value and the preset value The power consumption threshold value is obtained, and the power consumption evaluation result in the power consumption evaluation period is obtained; and the operating frequency of the computing device is adjusted based on the power consumption evaluation result.

According to another aspect of the present disclosure, there is provided a power consumption control device for an arithmetic device, comprising: a first acquisition unit configured to acquire a first number of data request signals within a power consumption evaluation period, wherein the power consumption The power consumption evaluation cycle includes a first preset number of consecutive multiple operation cycles, and the data request signal is used to request input data of the computing device; the second obtaining unit is configured to obtain, based on the first number, the computing device during the power consumption evaluation cycle the average power consumption characteristic value in Adjust the operating frequency of the computing device according to the power consumption evaluation result.

According to another aspect of the present disclosure, there is provided a chip including the above-mentioned power consumption control device for an arithmetic device.

According to another aspect of the present disclosure, there is provided an electronic device including the above-mentioned chip.

According to another aspect of the present disclosure, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by at least one processor One processor executes to enable at least one processor to execute the above-described power consumption control method for an arithmetic device.

According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the above-described power consumption control method for an arithmetic device.

According to another aspect of the present disclosure, there is provided a computer program product including a computer program, wherein the computer program, when executed by a processor, implements the above-described power consumption control method for an arithmetic device.

According to one or more embodiments of the present disclosure, by obtaining the number of data request signals in a certain period to evaluate the power consumption level of the computing device, and adjusting the power consumption of the device by adjusting the operating frequency of the computing device, simple logic Determine and efficiently evaluate the power consumption of the device and improve the efficiency of power consumption adjustment.

It should be understood that what is described in this section is not intended to identify key or critical features of embodiments of the disclosure, nor is it intended to limit the scope of the disclosure. Other features of the present disclosure will become readily understood from the following description.

Description of drawings

The accompanying drawings illustrate the embodiments by way of example and constitute a part of the specification, and together with the written description of the specification serve to explain exemplary implementations of the embodiments. The shown embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numbers refer to similar but not necessarily identical elements.

FIG. 1 shows a flowchart of a power consumption control method for a computing device according to an embodiment of the present disclosure;

FIG. 2 shows a schematic structural diagram of a chip for setting a power consumption control device according to an embodiment of the present disclosure;

FIG. 3 shows a structural block diagram of a vector computing apparatus according to an exemplary embodiment of the present disclosure;

4 shows a structural block diagram of a matrix multiplication apparatus according to an exemplary embodiment of the present disclosure;

FIG. 5 shows a structural block diagram of a power consumption control apparatus according to an embodiment of the present disclosure;

6 shows a structural block diagram of a power consumption control device for an arithmetic device according to an embodiment of the present disclosure;

7 illustrates a block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding and should be considered as exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted from the following description for clarity and conciseness.

In the present disclosure, unless otherwise specified, the use of the terms "first", "second", etc. to describe various elements is not intended to limit the positional relationship, timing relationship or importance relationship of these elements, and such terms are only used for Distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of the element, while in some cases they may refer to different instances based on the context of the description.

The terminology used in the description of the various described examples in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context clearly dictates otherwise, if the number of an element is not expressly limited, the element may be one or more. Furthermore, as used in this disclosure, the term "and/or" covers any and all possible combinations of the listed items.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In the deep learning algorithm, mainstream language models (such as BERT, ERNIE, etc.) include a large number of operations such as matrix multiplication and vector calculation, and mainstream machine vision models (such as RESNET, MASK-RCNN, YOLO, SSD and other networks) are also Contains a large number of convolution operations, and convolution operations are usually converted to matrix operations. Therefore, deep learning chips usually provide dedicated computing devices such as matrix multiplication devices and vector computing devices to accelerate deep learning algorithms.

While providing extremely high computing power for matrix multiplication and vector computing, these computing devices also consume a lot of power consumption. Under different scenarios and chip heat dissipation conditions, relevant technicians often need to adjust the power consumption levels of different computing devices according to actual conditions and computing needs, so as to avoid device performance degradation due to excessive power consumption of the computing devices.

In the related art, for power consumption monitoring and adjustment of the computing device in the chip, the power management chip of the board card is usually used to detect the current change of the entire chip, and adjust the frequency of the entire chip accordingly. This method usually requires the host to actively control the frequency switching of the chip, or perform frequency switching through the MCU inside the chip, which has a high delay; frequency switching will affect all devices of the entire deep learning chip, limiting the power consumption of computing devices such as matrix multiplication and transposition. At the same time, it also limits the performance of other modules such as memory access and control.

Embodiments of the present disclosure provide a power consumption control method for a computing device. Based on the relationship between a data request signal of input data of the computing device and the power consumption of the device, the computing device is evaluated by acquiring the number of data request signals in a certain period. The power consumption level of the device can be adjusted by adjusting the operating frequency of the computing device, so that the power consumption of the device can be efficiently evaluated through simple logic judgment, and the efficiency of power consumption adjustment can be improved.

According to an embodiment of the present disclosure, as shown in FIG. 1 , a power consumption control method for a computing device is provided, which may include: step S101 , acquiring a first number of data request signals in a power consumption evaluation period, wherein: The power consumption evaluation cycle includes a first preset number of consecutive multiple operation cycles, and the data request signal is used to request input data of the computing device; step S102, based on the first number, obtain the average power consumption of the computing device in the power consumption evaluation cycle. In step S103, based on the average power consumption characteristic value and the preset power consumption threshold, the power consumption evaluation result in the power consumption evaluation period is obtained; and in step S104, based on the power consumption evaluation result, the operating frequency of the computing device is adjusted.

Therefore, by obtaining the number of data request signals in a certain period to evaluate the power consumption level of the computing device, and adjusting the power consumption of the device by adjusting the operating frequency of the computing device, it is possible to efficiently evaluate the power consumption of the device through simple logical judgment, and improve the Efficiency of power regulation.

FIG. 2 shows a schematic structural diagram of a chip for setting a power consumption control device according to an embodiment of the present disclosure.

In some embodiments, as shown in FIG. 2 , the instruction generation device 210 provided in the chip sends the operation instruction to the instruction parsing device 220 , and the instruction parsing device 220 parses the operation instruction to generate at least one operation cycle corresponding The calculation enable signal and the data request signal used to request the calculation of each operation cycle. In each operation cycle, the instruction parsing device 220 sends a calculation enable signal and a data request signal to the operation device 230 and the storage device 250 respectively, and the storage device 250 sends the input data to the operation device 230 based on the data request signal to complete the calculation, The output data output by the arithmetic device 230 is stored.

In some embodiments, the power consumption control apparatus 240 of the embodiments of the present disclosure may be connected with the instruction parsing apparatus 220 to implement power consumption control of the computing apparatus 230 corresponding to the instruction parsing apparatus 220 . Specifically, in each computing cycle, the instruction parsing device 220 will simultaneously send a data request signal to the power consumption control device 240, and the power consumption control device 240 obtains the power consumption level of the computing device 230 based on the number of the signals. .

In some embodiments, the power consumption control apparatus 240 may perform statistics on the data request signals of each operation cycle in a first preset number of consecutive multiple operation cycles (ie, power consumption evaluation cycles).

The length of the power consumption evaluation cycle can be adjusted by setting a first preset number, for example, the first preset number can be set to 8 operation cycles. It is understandable that relevant technical personnel can set the first preset number by themselves according to actual requirements and conditions such as calculation requirements and hardware heat dissipation conditions, which is not limited here.

In some embodiments, the computing device may include a plurality of computing sub-modules. Based on the first number, acquiring the average power consumption characteristic value of the computing device in the power consumption evaluation period may include: based on the first number, acquiring the power consumption evaluation period in the power consumption evaluation period. a second number of operation sub-modules in the operation device in a working state; and based on the second number, obtain an average power consumption characteristic value of the operation device in the power consumption evaluation period.

Thus, based on the number of data request signals, the number of computing sub-modules operating in the computing device in the cycle can be obtained, and the power consumption level of the computing device in the cycle can be characterized by the number of operating computing sub-modules. Therefore, the power consumption level of the computing device can be efficiently obtained through simple logical operations, the real-time performance is higher, and the computing resources are less occupied.

A computing device usually includes multiple computing sub-modules, and in one computing cycle, if one computing sub-module performs calculations, it must acquire one or more pieces of input data, and each input data is requested through different data. signal obtained (that is, the amount of incoming data is the same as the amount of the data request signal). Therefore, in one power consumption evaluation period, there is a certain corresponding relationship between the first number of data request signals and the second number of operation sub-modules in the working state. The average number of operating sub-modules (ie, the average power consumption characterization value) in the working state during the power consumption evaluation period can represent the average power consumption level of the computing device during the power consumption evaluation period.

FIG. 3 shows a structural block diagram of a vector computing apparatus according to an exemplary embodiment of the present disclosure.

In an exemplary embodiment, the computing device may be, for example, the vector computing device 300 shown in FIG. 3 . Vector computing devices are typically used to handle operations between vectors or between vectors and scalars. As shown in FIG. 3 , the vector calculation apparatus 300 includes K vector calculation submodules, and in one operation cycle, each vector calculation submodule handles a pair of vectors or an operation between a vector and a scalar, that is, when a vector When the vector calculation sub-module is working, it is necessary to input two input data to the sub-module at the same time, and each input data corresponds to a data request signal.

It can be seen that there is a corresponding relationship between the number of data request signals and the number of vector calculation submodules in working state, that is, the number of data request signals is twice the number of vector calculation submodules in working state.

Therefore, by counting the first number of data request signals in the power consumption evaluation period, the second number of the vector computing submodules in the working state in the power consumption evaluation period can be obtained through the corresponding relationship. Furthermore, the power consumption level of the vector computing device in the power consumption evaluation period can be reflected by obtaining the number of the vector computing sub-modules in the working state on average per computing cycle (ie, the average power consumption characteristic value).

FIG. 4 shows a structural block diagram of a matrix multiplication apparatus according to an exemplary embodiment of the present disclosure.

In an exemplary embodiment, the operation device may be, for example, the matrix multiplication device 300 shown in FIG. 4 . The matrix multiplication device shown in FIG. 4 includes M×N matrix multiplication sub-modules, which can support a maximum of a matrix with M row vectors and a matrix with N column vectors to perform matrix inner product within one operation cycle. operation, where M and N are positive integers greater than 1.

When applying the matrix multiplication device to calculate a matrix A with m row vectors and a matrix B with n column vectors (where 1≤m≤M, 1≤n≤N), m×n The matrix multiplication submodules perform operations simultaneously.

Each matrix multiplication sub-module needs to obtain input data A(i) and input data B(j) (i∈[0, m], j∈[0, n]) respectively when performing operations. Each input data Corresponding to a data request signal, when m×n matrix multiplication sub-modules are required to perform operations at the same time, the number of data request signals is (m+n).

From this, it can be seen that by counting the first number of data request signals (the number of data request signals requesting A(i) and requesting B(j) data request signals) in the power consumption evaluation period, and through the above corresponding relationship, we can Obtain a second number of matrix multiplication submodules that are in a working state during the power consumption evaluation period. Furthermore, the power consumption level of the matrix multiplication device in the power consumption evaluation period can be reflected by obtaining the average number of matrix multiplication sub-modules in the working state per operation cycle (ie, the average power consumption characteristic value).

FIG. 5 shows a structural block diagram of a power consumption control apparatus according to an embodiment of the present disclosure.

In some embodiments, the power consumption control apparatus 500 may first count the number of data request signals in each operation cycle through the statistics module 510, so as to obtain the number of operation sub-modules in the working state in the operation cycle based on a predetermined corresponding relationship ( Record it as busy_cnt) and send it to the register for storage.

In some embodiments, each busy_cnt for a first preset number of cycles may be stored in a register, then input into an adder for summation, and then input into a divider to obtain the corresponding average power consumption characterization value .

In some embodiments, preferably, the first preset number can be set to 2 ⁿ (n is a positive integer), so that the shift register 520 shown in FIG. 5 can first perform an arithmetic right operation on each busy_cnt Shifting by n bits (equivalent to dividing by the first preset amount), and then transmitting each shifted busy_cnt to the adder 530 to calculate a sum, thereby obtaining an average power consumption characteristic value (denoted as busy_cnt_avg). Therefore, the division calculation operation can be conveniently performed through the shift register, the calculation efficiency is improved, and the calculation resources are saved.

In some embodiments, adjusting the operating frequency of the computing device based on the power consumption evaluation result may include: adjusting the binary-represented power consumption control signal value based on the power consumption evaluation result, wherein the power consumption evaluation result indicates whether the power consumption of the computing device exceeds The power consumption threshold is preset, and the power consumption control signal value includes a second preset number of multiple numerical bits; and based on the multiple numerical bits in the adjusted power consumption control signal value, controlling the power consumption control signal value after adjusting the power consumption control signal value. The operating frequency of the computing device in a plurality of computing cycles of the next second preset number, wherein the second preset number is less than or equal to the first preset number, and the plurality of numerical bits include a first numerical value whose value is the first value bit, the number of the first value bits is used to indicate the number of operation cycles in which the operation device stops working in the next second preset number of multiple operation cycles.

Therefore, a binary power consumption control signal value is adjusted according to the power consumption evaluation result, and the operating frequency of the computing device is adjusted correspondingly based on the signal value. The above operations can be realized by existing components (such as registers, comparators, etc.). , the structure is simple, and the cost is saved; at the same time, the above-mentioned power consumption control logic is simple, which can further improve the efficiency and real-time performance of power consumption adjustment.

In some embodiments, as shown in FIG. 5 , the preset power consumption threshold may be stored in the first register 550 and support the relevant technical personnel to maintain it based on the actual situation, so its value is not limited here.

The power consumption evaluation result can be obtained by comparing the average power consumption characteristic value (busy_cnt_avg) obtained from the adder 550 with the preset power consumption threshold value obtained from the first register 550 through the comparator 540 . After obtaining the power consumption evaluation result, the comparator 540 sends the power consumption evaluation result to the second register 560, and the second register 560 correspondingly adjusts the power consumption control signal stored in the second register 560 according to the power consumption evaluation result value.

In some embodiments, the plurality of numerical bits further include a second numerical value whose value is a second value. Based on the average power consumption characteristic value and the preset power consumption threshold, obtaining the power consumption evaluation result in the power consumption evaluation period may include: In response to the average power consumption characteristic value being greater than or equal to the preset power consumption threshold, it is determined that the power consumption evaluation result is that the power consumption of the computing device is too high; The method includes: in response to determining that the power consumption evaluation result is that the power consumption of the computing device is too high, adjusting a second value bit in the power consumption control signal value to a first value bit.

In some embodiments, as shown in FIG. 5 , a power consumption control signal value having a second preset number of bits may be stored in the second register 560 of the power consumption control apparatus 500 . The power consumption control signal value has a first value bit having a first value and a second value bit having a second value. The number of the first value bits indicates the number of cycles during which the computing device stops working within the power consumption adjustment cycle (ie, the next second preset number of multiple computing cycles) after the power consumption control signal value is adjusted. .

The second preset number needs to be less than or equal to the first preset number, so that it is possible to avoid evaluating and adjusting the power consumption again before the adjustment effect occurs. It is understandable that the second preset number can be set by the relevant technical personnel according to actual needs, which is not limited herein.

Exemplarily, the first value may be "1" and the second value may be "0"; or, the first value may be "0" and the second value may be "1"

In some embodiments, the power consumption control signal value stored in the second register 560 may be an 8-bit binary data (denoted as stall_mask[7:0]), and its initial value is “0000 0000” (that is, every One bit is the second value), the second register 560 may be an 8-bit register.

When the comparator 540 determines that the average power consumption characteristic value (busy_cnt_avg) is greater than or equal to the preset power consumption threshold through comparison, the result is correspondingly transmitted to the second register 560 . Based on the result, the second register 560 adjusts a bit of the original value of "0" in the power consumption control signal value (stall_mask[7:0]) maintained by it to "1", for example, stall_mask[7:0] Adjusted from the initial value "0000 0000" to "0000 0001", the power consumption control signal value can indicate that in 1 operation cycle in the adjusted 8 operation cycles, the operation device stops working; another example, stall_mask[7: 0] is adjusted from "00000011" to "0000 0111", the power consumption control signal value can indicate that there are 3 operation cycles in the adjusted 8 operation cycles, and the operation device stops working.

In some embodiments, the plurality of numerical bits further include a second numerical value whose value is a second value. Based on the average power consumption characteristic value and the preset power consumption threshold, obtaining the power consumption evaluation result in the power consumption evaluation period may include: In response to the average power consumption characteristic value being less than the preset power consumption threshold, determining that the power consumption evaluation result is that the power consumption of the computing device is normal; and wherein, based on the power consumption evaluation result, determining the power consumption control signal value represented in binary may include: responding to After determining that the power consumption evaluation result is that the power consumption of the computing device is normal and the power consumption control signal value includes a first value bit, a first value bit in the power consumption control signal value is adjusted to a second value bit.

In some embodiments, when the comparator 540 determines that the average power consumption characteristic value (busy_cnt_avg) is smaller than the preset power consumption threshold through comparison, the result is correspondingly transmitted to the second register 560 . Based on the result, the second register 560 can adjust the power consumption control signal value (stall_mask[7:0]) to be maintained accordingly.

When the original value in stall_mask[7:0] contains "1", one bit of the original value of "1" in stall_mask[7:0] can be adjusted to "0". For example, if stall_mask[7:0] is adjusted from the initial value "0000 0111" to "00000011", the power consumption control signal value can indicate that there are 2 operation cycles in the adjusted 8 operation cycles, and the operation device stops working (Before the adjustment was 3 cycles out of every 8 cycles).

In some embodiments, determining the power consumption control signal value represented in binary based on the power consumption evaluation result may further include: in response to determining that the power consumption evaluation result is that the power consumption of the computing device is normal and each numerical bit in the power consumption control signal value are the second value bits, it is determined that each value bit in the power consumption control signal value is still the second value bit.

In some embodiments, when the power consumption evaluation result obtained from the comparator 540 is that the average power consumption characteristic value (busy_cnt_avg) is less than the preset power consumption threshold, and the original value of the power consumption control signal value stall_mask[7:0] is the initial value When the value is "00000000", the value of the power consumption control signal stall_mask[7:0] can be left unchanged, and it still remains "0000 0000" (that is, the operation device is normal in each of the following 8 operation cycles). Work).

In some embodiments, based on a plurality of numerical bits in the adjusted power consumption control signal value, the operation of the computing device in the next second preset number of multiple operation cycles after the adjusted power consumption control signal value is controlled. The frequency may include: generating an instruction issuance blocking signal based on a third number of second numerical bits in the adjusted power consumption control signal value; and sending the instruction issuance blocking signal to an instruction for sending an arithmetic instruction to the computing device The parsing device is configured to prevent the instruction parsing device from stopping issuing operation instructions in a third number of operation cycles in the next second preset number of multiple operation cycles.

Thus, based on the adjusted value of the power consumption control signal, an instruction issuance prevention signal is generated, so as to stop the number of cycles in which instructions are issued in the next power consumption adjustment period, so as to control the operation frequency of the computing device by adjusting the operating frequency. The power consumption level of the computing device can effectively control the power consumption level of the computing device without affecting the normal operation of other components in the chip (such as a storage device, a control device, etc.).

In some embodiments, as shown in FIG. 5 , after the power consumption control signal value in the second register 560 is adjusted, the second register 560 will generate an instruction issuance blocking signal based on the adjusted power consumption control signal value , and send it to the instruction parsing device (not shown in the figure).

In some embodiments, after the instruction parsing device receives the instruction issuance blocking signal, it can know that the instruction issuance needs to be stopped within the next second preset number of multiple operation cycles (that is, the above-mentioned calculation enable signal and data request signal), thereby controlling the operation device to stop working within the period.

In some embodiments, after acquiring the above-mentioned information, the instruction parsing apparatus may randomly select a period for stopping issuing instructions (the number is the same as the number of the first value in the power consumption control signal value).

In some embodiments, as shown in FIG. 5 , the second register 560 may also generate an instruction issuance blocking signal 502 based on the power consumption control signal value 501 stored therein. For example, the power consumption control signal value 501 is “0000 1111” , then the correspondingly generated instruction delivery prevention signal 502 is a corresponding window signal. After receiving the instruction issuing blocking signal 502, the instruction parsing apparatus can stop issuing the instruction based on the four operation cycles indicated by the window of the signal.

In some embodiments, the power consumption control method for a computing device according to an embodiment of the present disclosure may further include: after the value of the power consumption control signal is adjusted, in response to the elapse of a third preset number of operation cycles, obtaining the most recent an average power consumption characteristic value of the computing device in the power consumption evaluation period to determine the power consumption evaluation result of the computing device in the most recent power consumption evaluation period, wherein the third preset number is greater than or equal to the first preset number; and Based on the power consumption evaluation result of the computing device in the most recent power consumption evaluation period, the power consumption control signal value is re-determined.

Therefore, by setting the interval period (that is, the third preset number of operation cycles), after the power consumption adjustment is performed once, the power consumption data comparison and the power consumption control signal value in the register are performed after the interval period. Therefore, the frequency of power consumption adjustment can be controlled based on the interval period, and the power consumption adjustment of the computing device can be made smoother.

In some embodiments, when a third preset number of operation cycles (ie, interval periods) is set, no averaging is performed within the third preset number of operation cycles after one power consumption control signal value adjustment has been performed. Comparison of power consumption characteristic value and preset power consumption threshold value, and adjustment of power consumption control signal value. In the interval period, the computing device operates according to the adjusted operating frequency.

In some embodiments, the third preset period may be greater than or equal to the first preset period, which can avoid that when the next comparison is triggered, the acquired average power consumption characteristic value is still the result of the previous statistics, which affects The power consumption evaluation results and power consumption adjustment effects of this comparison. It is understandable that the third preset number can be set by the relevant technical personnel according to actual needs, for example, it can be an integer multiple of the first preset period, which is not limited herein.

In some embodiments, as shown in FIG. 6 , a power consumption control device 600 for a computing device is also provided, which may include: a first obtaining unit 610 configured to obtain a data request signal within a power consumption evaluation period The first number of , wherein the power consumption evaluation cycle includes a first preset number of consecutive multiple operation cycles, and the data request signal is used to request the input data of the computing device; the second acquisition unit 620 is configured to be based on the first number of , to obtain the average power consumption characteristic value of the computing device in the power consumption evaluation period; the third obtaining unit 630 is configured to obtain the power consumption evaluation result in the power consumption evaluation period based on the average power consumption characteristic value and the preset power consumption threshold ; and an adjustment unit 640, configured to adjust the operating frequency of the computing device based on the power consumption evaluation result.

The operations of the unit 610 to the unit 640 in the power consumption control apparatus 600 are similar to the operations of the steps S101 to S104 in the above-mentioned power consumption control method for an arithmetic device, and are not repeated here.

In some embodiments, the computing device may include a plurality of computing sub-modules, and the second obtaining unit may include: a first obtaining sub-unit configured to obtain, based on the first number, the computing devices that are in the working state during the power consumption evaluation period and a second obtaining subunit configured to obtain the average power consumption characteristic value of the computing device in the power consumption evaluation period based on the second quantity.

In some embodiments, the adjustment unit may include: an adjustment subunit configured to adjust the binary-represented power consumption control signal value based on a power consumption evaluation result, wherein the power consumption evaluation result indicates whether the power consumption of the computing device exceeds a preset power consumption a power consumption threshold, the power consumption control signal value includes a second preset number of multiple numerical bits; and a control subunit configured to control the power consumption control adjustment based on the multiple numerical bits in the adjusted power consumption control signal value The operating frequency of the computing device in the next second preset number of multiple operation cycles after the signal value, wherein the second preset number is less than or equal to the first preset number, and the number of numerical bits includes the first value. The number of the first value bits is used to indicate the number of operation cycles in which the operation device stops working in the next second preset number of multiple operation cycles.

In some embodiments, the plurality of numerical bits further include a second numerical value whose value is a second value, and the third obtaining unit may include: a first determining subunit, configured to respond to the average power consumption characteristic value being greater than or equal to a predetermined value Setting a power consumption threshold, it is determined that the power consumption evaluation result is that the power consumption of the computing device is too high; and wherein, the adjustment subunit may be configured to: in response to determining that the power consumption evaluation result is that the power consumption of the computing device is too high, the power consumption control signal value A second value bit in is adjusted to the first value bit.

In some embodiments, the plurality of numerical bits further include a second numerical value having a second value, and the third obtaining unit may include: a second determining subunit, configured to respond that the average power consumption characteristic value is less than the preset power consumption the power consumption threshold, and determine that the power consumption evaluation result is that the power consumption of the computing device is normal; and wherein, the adjustment subunit may be configured to: in response to determining that the power consumption evaluation result is that the power consumption of the computing device is normal and that the power consumption control signal value includes the first power consumption A value bit that adjusts a first value bit in the power consumption control signal value to a second value bit.

In some embodiments, the adjusting subunit may be further configured to: in response to determining that the power consumption evaluation result is that the power consumption of the computing device is normal and that each value bit in the power consumption control signal value is a second value bit, determine Each value bit in the power consumption control signal value remains a second value bit.

In some embodiments, the control sub-unit may include: a generating module configured to generate an instruction issuance blocking signal based on a third number of second numerical bits in the adjusted power consumption control signal value; and a sending module, configured by is configured to send an instruction issuing blocking signal to the instruction parsing device for sending an arithmetic instruction to the computing device, so as to prevent the instruction parsing device from stopping in a third number of operation cycles among the next second preset number of multiple operation cycles Issue operation instructions.

In some embodiments, the power consumption control apparatus for a computing device according to an embodiment of the present disclosure may further include: a fourth acquisition unit, configured to, after the value of the power consumption control signal is adjusted, respond to a third preset number of After the computing cycle, the average power consumption characteristic value of the computing device in the most recent power consumption evaluation cycle is obtained to determine the power consumption evaluation result of the computing device in the most recent power consumption evaluation cycle, wherein the third preset number is greater than or is equal to the first preset number; and the determining unit is configured to re-determine the power consumption control signal value based on the power consumption evaluation result of the computing device in the most recent power consumption evaluation period.

In some embodiments, a chip is provided, including the above-described power consumption control device for a computing device.

In some embodiments, there is provided an electronic device including the above-mentioned chip.

In some embodiments, an electronic device is provided, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being processed by the at least one processor The processor executes, so that at least one processor can execute the above-mentioned power consumption control method for an arithmetic device.

In some embodiments, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to perform the above-described power consumption control method for a computing device.

In some embodiments, a computer program product is provided, comprising a computer program, wherein the computer program, when executed by a processor, implements the above-described power consumption control method for a computing device.

According to embodiments of the present disclosure, an electronic device, a readable storage medium, and a computer program product are also provided.

Referring to FIG. 7 , a structural block diagram of an electronic device 700 that can function as a server or client of the present disclosure will now be described, which is an example of a hardware device that can be applied to various aspects of the present disclosure. Electronic devices are intended to represent various forms of digital electronic computer devices, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are by way of example only, and are not intended to limit implementations of the disclosure described and/or claimed herein.

As shown in FIG. 7 , the electronic device 700 includes a computing unit 701 that can be programmed according to a computer program stored in a read only memory (ROM) 702 or loaded into a random access memory (RAM) 703 from a storage unit 708 . Various appropriate actions and processes are performed. In the RAM 703, various programs and data required for the operation of the electronic device 700 can also be stored. The computing unit 701 , the ROM 702 , and the RAM 703 are connected to each other through a bus 704 . An input/output (I/O) interface 705 is also connected to bus 704 .

Various components in the electronic device 700 are connected to the I/O interface 705 , including: an input unit 706 , an output unit 707 , a storage unit 708 , and a communication unit 709 . The input unit 706 may be any type of device capable of inputting information to the electronic device 700, the input unit 706 may receive input numerical or character information, and generate key signal input related to user settings and/or function control of the electronic device, and This may include, but is not limited to, a mouse, keyboard, touch screen, trackpad, trackball, joystick, microphone and/or remote control. Output unit 707 may be any type of device capable of presenting information, and may include, but is not limited to, a display, speakers, video/audio output terminals, vibrators, and/or printers. The storage unit 708 may include, but is not limited to, magnetic disks and optical disks. The communication unit 709 allows the electronic device 700 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers and/or chips Groups such as Bluetooth™ devices, 802.11 devices, WiFi devices, WiMax devices, cellular communication devices and/or the like.

Computing unit 701 may be various general-purpose and/or special-purpose processing components with processing and computing capabilities. Some examples of computing units 701 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various specialized artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 executes the various methods and processes described above, such as the above-described power consumption control method for an arithmetic device. For example, in some embodiments, the power consumption control method for a computing device described above may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 708 . In some embodiments, part or all of the computer program may be loaded and/or installed on electronic device 700 via ROM 702 and/or communication unit 709 . When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the above-described power consumption control method for an arithmetic device described above may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured in any other suitable manner (eg, by means of firmware) to perform the above-described power consumption control method for a computing device.

Various implementations of the systems and techniques described herein above may be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips system (SOC), complex programmable logic device (CPLD), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include being implemented in one or more computer programs executable and/or interpretable on a programmable system including at least one programmable processor that The processor, which may be a special purpose or general-purpose programmable processor, may receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device an output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer or other programmable data processing apparatus, such that the program code, when executed by the processor or controller, performs the functions/functions specified in the flowcharts and/or block diagrams. Action is implemented. The program code may execute entirely on the machine, partly on the machine, partly on the machine and partly on a remote machine as a stand-alone software package or entirely on the remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in connection with the instruction execution system, apparatus or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), fiber optics, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.

To provide interaction with a user, the systems and techniques described herein may be implemented on a computer having a display device (eg, a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user ); and a keyboard and pointing device (eg, a mouse or trackball) through which a user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (eg, visual feedback, auditory feedback, or tactile feedback); and can be in any form (including acoustic input, voice input, or tactile input) to receive input from the user.

The systems and techniques described herein may be implemented on a computing system that includes back-end components (eg, as a data server), or a computing system that includes middleware components (eg, an application server), or a computing system that includes front-end components (eg, a user's computer having a graphical user interface or web browser through which a user may interact with implementations of the systems and techniques described herein), or including such backend components, middleware components, Or any combination of front-end components in a computing system. The components of the system may be interconnected by any form or medium of digital data communication (eg, a communication network). Examples of communication networks include: Local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

A computer system can include clients and servers. Clients and servers are generally remote from each other and usually interact through a communication network. The relationship of client and server arises by computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a distributed system server, or a server combined with blockchain.

It should be understood that steps may be reordered, added or deleted using the various forms of flow shown above. For example, the steps described in the present disclosure can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved, which are not limited herein.

Although the embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it should be understood that the above-described methods, systems and devices are merely exemplary embodiments or examples, and the scope of the present invention is not limited by these embodiments or examples, but is limited only by the appended claims and their equivalents. Various elements of the embodiments or examples may be omitted or replaced by equivalents thereof. Furthermore, the steps may be performed in an order different from that described in this disclosure. Further, various elements of the embodiments or examples may be combined in various ways. Importantly, as technology evolves, many of the elements described herein may be replaced by equivalent elements that appear later in this disclosure.

Claims (21)

1. A power consumption control method for an arithmetic device, the method comprising:

acquiring a first number of data request signals in a power consumption evaluation period, wherein the power consumption evaluation period comprises a first preset number of continuous operation periods, and the data request signals are used for requesting input data of the operation device;

acquiring an average power consumption characterization value of the operation device in the power consumption evaluation period based on the first quantity;

acquiring a power consumption evaluation result in the power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value; and

and adjusting the working frequency of the arithmetic device based on the power consumption evaluation result.

2. The method of claim 1, wherein the computing device includes a plurality of computing sub-modules, and wherein obtaining an average power consumption characterization value for the computing device over the power consumption evaluation period based on the first number comprises:

acquiring a second number of operation sub-modules in the operation device in the working state in the power consumption evaluation period based on the first number; and

and acquiring an average power consumption characterization value of the operation device in the power consumption evaluation period based on the second quantity.

3. The method of claim 1, wherein the adjusting the operating frequency of the computing device based on the power consumption assessment result comprises:

adjusting a binary-expressed power consumption control signal value based on the power consumption evaluation result, wherein the power consumption evaluation result indicates whether the power consumption of the computing device exceeds the preset power consumption threshold value, and the power consumption control signal value comprises a second preset number of a plurality of numerical value bits; and

controlling the working frequency of the operation device in a plurality of operation cycles of a next second preset number after the power consumption control signal value is adjusted based on a plurality of numerical bits in the adjusted power consumption control signal value, wherein the second preset number is less than or equal to the first preset number, the plurality of numerical bits comprise a first numerical bit of which the numerical value is a first value, and the number of the first numerical bit is used for indicating the number of operation cycles of stopping the operation of the operation device in the plurality of operation cycles of the next second preset number.

4. The method of claim 3, wherein the plurality of numerical bits further includes a second numerical bit having a second value, and the obtaining the power consumption evaluation result in the power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value comprises:

in response to that the average power consumption characterization value is larger than or equal to the preset power consumption threshold value, determining that the power consumption evaluation result is that the power consumption of the operation device is too high; and wherein the one or more of the one or more,

determining a binary-represented power consumption control signal value based on the power consumption assessment result comprises:

adjusting a second numerical bit of the power consumption control signal value to a first numerical bit in response to determining that the power consumption evaluation result is that the computing device consumes too much power.

5. The method of claim 3, wherein the plurality of numerical bits further includes a second numerical bit having a second value, and the obtaining the power consumption evaluation result in the power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value comprises:

responding to the fact that the average power consumption characterization value is smaller than the preset power consumption threshold value, and determining that the power consumption evaluation result is that the power consumption of the operation device is normal; and wherein the (a) and (b) are,

determining a binary-represented power consumption control signal value based on the power consumption assessment result comprises:

adjusting one first numerical bit of the power consumption control signal values to a second numerical bit in response to determining that the power consumption evaluation result is that the computing device consumes normal power and the power consumption control signal values include the first numerical bit.

6. The method of claim 5, wherein determining a binary-represented power consumption control signal value based on the power consumption assessment result further comprises:

and in response to determining that the power consumption evaluation result is that the computing device consumes normal power and each numerical bit in the power consumption control signal value is a second numerical bit, determining that each numerical bit in the power consumption control signal value is still the second numerical bit.

7. The method of any of claims 3 to 6, wherein the controlling the operating frequency of the computing device in a next second preset number of computing cycles after adjusting the power consumption control signal value based on the number of numerical bits in the adjusted power consumption control signal value comprises:

generating an instruction issue blocking signal based on a third number of second numerical bits in the adjusted power consumption control signal value; and

and sending the instruction issuing prevention signal to an instruction analysis device used for sending the operation instruction to the operation device so as to prevent the instruction analysis device from stopping issuing the operation instruction in a third number of operation cycles in the next second preset number of operation cycles.

8. The method of any of claims 3 to 7, further comprising:

after the power consumption control signal value is adjusted, responding to a third preset number of operation cycles, and then obtaining an average power consumption representation value of the operation device in the latest power consumption evaluation cycle to determine a power consumption evaluation result of the operation device in the latest power consumption evaluation cycle, wherein the third preset number is greater than or equal to the first preset number; and

re-determining the power consumption control signal value based on a power consumption evaluation result of the arithmetic device in a latest power consumption evaluation period.

9. A power consumption control apparatus for an arithmetic apparatus, the power consumption control apparatus comprising:

a first acquisition unit configured to acquire a first number of data request signals within a power consumption evaluation period, wherein the power consumption evaluation period includes a first preset number of consecutive operation periods, and the data request signals are used for requesting input data of the operation device;

a second obtaining unit configured to obtain an average power consumption characterization value of the arithmetic device in the power consumption evaluation period based on the first number;

a third obtaining unit, configured to obtain a power consumption evaluation result in the power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value; and

an adjusting unit configured to adjust an operating frequency of the arithmetic device based on the power consumption evaluation result.

10. The power consumption control apparatus according to claim 9, wherein the arithmetic means includes a plurality of arithmetic sub-modules, the second acquisition unit includes:

a first obtaining subunit configured to obtain, based on the first number, a second number of operation sub-modules in the operation device that is in an operating state in the power consumption evaluation period; and

a second obtaining subunit configured to obtain, based on the second number, an average power consumption characterizing value of the arithmetic device in the power consumption evaluation period.

11. The power consumption control apparatus according to claim 9, wherein the adjusting unit includes:

an adjusting subunit configured to adjust a binary-represented power consumption control signal value based on the power consumption evaluation result, wherein the power consumption evaluation result indicates whether the power consumption of the computing device exceeds the preset power consumption threshold, and the power consumption control signal value includes a second preset number of a plurality of numerical bits; and

a control subunit configured to control an operating frequency of the arithmetic device in a next second preset number of multiple operation cycles after the power consumption control signal value is adjusted based on a plurality of numerical bits in the adjusted power consumption control signal value, where the second preset number is less than or equal to the first preset number, the plurality of numerical bits include a first numerical bit whose numerical value is a first value, and the number of the first numerical bit is used to indicate a number of operation cycles in which the arithmetic device stops operating in the next second preset number of multiple operation cycles.

12. The power consumption control apparatus according to claim 11, wherein the plurality of numerical bits further includes a second numerical bit whose numerical value is a second value, the third obtaining unit includes:

a first determining subunit, configured to determine that the power consumption evaluation result is that the power consumption of the computing device is too high in response to that the average power consumption characterization value is greater than or equal to the preset power consumption threshold; and wherein the one or more of the one or more,

the adjustment subunit is configured to:

adjusting a second numerical bit of the power consumption control signal value to a first numerical bit in response to determining that the power consumption evaluation result is that the computing device consumes too much power.

13. The power consumption control apparatus according to claim 11, wherein the plurality of numerical bits further includes a second numerical bit whose numerical value is a second value, the third obtaining unit includes:

a second determining subunit, configured to determine, in response to the average power consumption characterization value being smaller than the preset power consumption threshold value, that the power consumption evaluation result is that the power consumption of the computing device is normal; and wherein the one or more of the one or more,

the adjustment subunit is configured to:

adjusting one first numerical bit of the power consumption control signal values to a second numerical bit in response to determining that the power consumption evaluation result is that the computing device consumes normal power and the power consumption control signal values include the first numerical bit.

14. The power consumption control apparatus of claim 13, wherein the adjustment subunit is further configured to:

and in response to determining that the power consumption evaluation result is that the computing device consumes normal power and each numerical bit in the power consumption control signal value is a second numerical bit, determining that each numerical bit in the power consumption control signal value is still the second numerical bit.

15. The power consumption control apparatus according to any one of claims 11 to 14, wherein the control subunit includes:

a generation module configured to generate an instruction issue blocking signal based on a third number of second numerical bits in the adjusted power consumption control signal value; and

a sending module configured to send the instruction issue blocking signal to an instruction analysis device for sending an operation instruction to the operation device, so as to prevent the instruction analysis device from stopping issuing the operation instruction in a third number of operation cycles in the next second preset number of operation cycles.

16. The power consumption control apparatus according to any one of claims 11 to 15, further comprising:

a fourth obtaining unit, configured to obtain an average power consumption characterization value of the computing device in a latest power consumption evaluation period in response to a third preset number of computing periods after the power consumption control signal value is adjusted, so as to determine a power consumption evaluation result of the computing device in the latest power consumption evaluation period, where the third preset number is greater than or equal to the first preset number; and

a determination unit configured to re-determine the power consumption control signal value based on a power consumption evaluation result of the arithmetic device in a latest power consumption evaluation period.

17. A chip comprising the apparatus of any one of claims 9-16.

18. An electronic device comprising the chip of claim 17.

19. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

20. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-8.

21. A computer program product comprising a computer program, wherein the computer program realizes the method of any one of claims 1-8 when executed by a processor.

Images