CN114879832A - Power consumption control method, device, chip, apparatus, and medium for arithmetic device - Google Patents
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Abstract
The present disclosure provides a power consumption control method, device, chip, device and medium for an arithmetic device, and relates to the field of computer technologies, in particular to the fields of chip technologies and artificial intelligence. The implementation scheme is as follows: acquiring a first number of data request signals in a power consumption evaluation period, wherein the power consumption evaluation period comprises a first preset number of continuous multiple operation periods, and the data request signals are used for requesting input data of an operation device; acquiring an average power consumption characterization value of the operation device in a power consumption evaluation period based on the first quantity; acquiring a power consumption evaluation result in a power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value; and adjusting the operating frequency of the computing device based on the power consumption evaluation result.
Description
Technical Field
The present disclosure relates to the field of computer technologies, particularly to the field of chip technologies and artificial intelligence, and in particular, to a power consumption control method and apparatus for an arithmetic apparatus, an electronic device, a computer-readable storage medium, and a computer program product.
Background
With the development of artificial intelligence technology, more and more applications obtain the effect far exceeding the traditional algorithm based on the artificial intelligence technology; deep learning is the core technology of the current artificial intelligence technology. Deep learning is a data intensive algorithm and a calculation intensive algorithm, and is also an algorithm for rapid iterative development.
The traditional general processing equipment such as a CPU, a GPU and a DSP is designed aiming at general computing tasks, when the deep learning application is processed, the defects of low computing performance, low efficiency and the like exist, and the large-scale deployment of a deep learning algorithm in scenes such as a data center and the like cannot be effectively supported. The special accelerating equipment for deep learning based on the ASIC/FPGA deeply customizes a hardware structure aiming at the calculation characteristics of deep learning, and can realize higher calculation performance and calculation efficiency compared with the traditional equipment such as a CPU, a GPU, a DSP and the like.
The approaches described in this section are not necessarily approaches that have been previously conceived or pursued. Unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section. Similarly, unless otherwise indicated, the problems mentioned in this section should not be considered as having been acknowledged in any prior art.
Disclosure of Invention
The present disclosure provides a power consumption control method for an arithmetic device, an apparatus, an electronic device, a computer-readable storage medium, and a computer program product.
According to an aspect of the present disclosure, there is provided a power consumption control method for an arithmetic device, including: acquiring a first number of data request signals in a power consumption evaluation period, wherein the power consumption evaluation period comprises a first preset number of continuous operation periods, and the data request signals are used for requesting input data of an operation device; acquiring an average power consumption characterization value of the operation device in a power consumption evaluation period based on the first quantity; acquiring a power consumption evaluation result in a power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value; and adjusting the operating frequency of the computing device based on the power consumption evaluation result.
According to another aspect of the present disclosure, there is provided a power consumption control apparatus for an arithmetic apparatus, including: a first acquisition unit configured to acquire a first number of data request signals within a power consumption evaluation period, wherein the power consumption evaluation period includes a first preset number of consecutive operation periods, and the data request signals are used for requesting input data of the operation device; a second acquisition unit configured to acquire an average power consumption representative value of the arithmetic device in a power consumption evaluation period based on the first number; the third obtaining unit is configured to obtain a power consumption evaluation result in a power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value; and an adjusting unit configured to adjust an operating frequency of the arithmetic device based on the power consumption evaluation result.
According to another aspect of the present disclosure, there is provided a chip including the above power consumption control apparatus for an arithmetic apparatus.
According to another aspect of the present disclosure, there is provided an electronic device including the chip described above.
According to another aspect of the present disclosure, there is provided an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the power consumption control method for the arithmetic device.
According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the above-described power consumption control method for an arithmetic device.
According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the above-described power consumption control method for an arithmetic device.
According to one or more embodiments of the present disclosure, by acquiring the number of data request signals in a certain period to evaluate the power consumption level of an arithmetic device and adjusting the power consumption of the arithmetic device in a manner of adjusting the operating frequency of the arithmetic device, it is possible to efficiently evaluate the power consumption of the arithmetic device through simple logic determination, and improve the efficiency of power consumption adjustment.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the embodiments and, together with the description, serve to explain the exemplary implementations of the embodiments. The illustrated embodiments are for purposes of illustration only and do not limit the scope of the claims. Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.
Fig. 1 shows a flowchart of a power consumption control method for an arithmetic device according to an embodiment of the present disclosure;
fig. 2 shows a schematic structural diagram of a chip that sets a power consumption control device according to an embodiment of the present disclosure;
fig. 3 shows a block diagram of a vector calculation apparatus according to an exemplary embodiment of the present disclosure;
fig. 4 shows a block diagram of a matrix multiplication apparatus according to an exemplary embodiment of the present disclosure;
fig. 5 shows a block diagram of a power consumption control apparatus according to an embodiment of the present disclosure;
fig. 6 shows a block diagram of a power consumption control apparatus for an arithmetic apparatus according to an embodiment of the present disclosure;
FIG. 7 illustrates a block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
In the present disclosure, unless otherwise specified, the use of the terms "first", "second", and the like to describe various elements is not intended to limit the positional relationship, the temporal relationship, or the importance relationship of the elements, and such terms are used only to distinguish one element from another. In some examples, a first element and a second element may refer to the same instance of the element, and in some cases, based on the context, they may also refer to different instances.
The terminology used in the description of the various described examples in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the elements may be one or more. Furthermore, the term "and/or" as used in this disclosure is intended to encompass any and all possible combinations of the listed items.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
In the deep learning algorithm, a mainstream language model (such as BERT, ERNIE and the like) includes a large amount of matrix multiplication, vector calculation and other operations, a mainstream machine vision model (such as RESNET, MASK-RCNN, YOLO, SSD and the like) also includes a large amount of convolution operations, and the convolution operations are usually realized by converting into matrix operations. Therefore, the deep learning chip generally provides a dedicated arithmetic device such as a matrix multiplication device and a vector calculation device for accelerating the deep learning algorithm.
While providing extremely high computational power for matrix multiplication and vector calculation, these arithmetic devices also consume a large amount of power. Under different scenes and chip heat dissipation conditions, related technicians often need to adjust the power consumption levels of different computing devices according to actual conditions and computing needs, so that the performance reduction of the computing device caused by overhigh power consumption is avoided.
In the related art, for monitoring and adjusting the power consumption of the computing device in the chip, the current change of the whole chip is usually detected through the power management chip of the board card, and the frequency of the whole chip is adjusted accordingly. The method usually needs a host to actively control the frequency switching of the chip, or the frequency switching is carried out through an MCU in the chip, so that the delay is higher; the frequency switching can affect all devices of the whole deep learning chip, and the performance of other modules such as access and control is limited while the power consumption of the arithmetic device such as matrix multiplication and transposition is limited.
The embodiment of the disclosure provides a power consumption control method for an arithmetic device, which evaluates the power consumption level of the arithmetic device by acquiring the number of data request signals in a certain period based on the relationship between the data request signals of input data of the arithmetic device and the power consumption of the device, adjusts the power consumption of the device in a mode of adjusting the working frequency of the arithmetic device, can judge the power consumption of the device efficiently through simple logic, and improve the efficiency of power consumption adjustment.
According to an embodiment of the present disclosure, as shown in fig. 1, there is provided a power consumption control method for an arithmetic device, which may include: step S101, acquiring a first number of data request signals in a power consumption evaluation period, wherein the power consumption evaluation period comprises a plurality of continuous operation periods with a first preset number, and the data request signals are used for requesting input data of an operation device; step S102, acquiring an average power consumption representation value of the operation device in a power consumption evaluation period based on the first quantity; step S103, acquiring a power consumption evaluation result in a power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value; and step S104, adjusting the working frequency of the arithmetic device based on the power consumption evaluation result.
Therefore, the power consumption level of the arithmetic device is evaluated by acquiring the number of the data request signals in a certain period, and the power consumption of the arithmetic device is adjusted in a mode of adjusting the working frequency of the arithmetic device, so that the power consumption of the efficient evaluation device can be judged through simple logic, and the efficiency of power consumption adjustment is improved.
Fig. 2 shows a schematic structural diagram of a chip provided with a power consumption control device according to an embodiment of the present disclosure.
In some embodiments, as shown in fig. 2, the instruction generating device 210 disposed in the chip issues the operation instruction to the instruction parsing device 220, and the instruction parsing device 220 parses the operation instruction to generate a computation enable signal corresponding to at least one operation cycle and a data request signal for requesting computation of each operation cycle. In each operation cycle, the instruction parsing device 220 sends a calculation enable signal and a data request signal to the operation device 230 and the storage device 250, respectively, and the storage device 250 sends input data to the operation device 230 to complete calculation based on the data request signal and stores output data output by the operation device 230.
In some embodiments, the power consumption control device 240 of the embodiments of the present disclosure may be connected to the instruction parsing device 220, so as to implement power consumption control on the computing device 230 corresponding to the instruction parsing device 220. Specifically, in each operation cycle, the instruction parsing device 220 simultaneously sends a data request signal to the power consumption control device 240, and the power consumption control device 240 obtains the power consumption level of the operation device 230 based on the number statistics of the signals.
In some embodiments, the power consumption control device 240 may count the data request signals of each operation cycle within a first preset number of consecutive operation cycles (i.e., power consumption evaluation cycles).
The length of the power consumption evaluation period may be adjusted by setting a first preset number, for example, the first preset number may be set to 8 operation periods. It can be understood that the related art can set the first preset number by itself according to actual requirements and conditions, such as the calculated requirements and the hardware heat dissipation conditions, and the like, without limitation.
In some embodiments, the arithmetic device may include a plurality of arithmetic sub-modules, and obtaining the average power consumption characterizing value of the arithmetic device during the power consumption evaluation period based on the first number may include: acquiring a second number of operation submodules in the operation device in the working state in the power consumption evaluation period based on the first number; and acquiring an average power consumption characterization value of the operation device in the power consumption evaluation period based on the second quantity.
Therefore, the number of the working calculation sub-modules in the calculation device in the period can be obtained based on the number of the data request signals, and the power consumption level of the calculation device in the period is represented by the number of the working calculation sub-modules. Therefore, the power consumption level of the arithmetic device can be efficiently obtained through simple logic operation, the real-time performance is higher, and the occupation of computing resources is less.
An arithmetic device usually includes a plurality of arithmetic sub-modules, and in an arithmetic cycle, if one arithmetic sub-module performs calculation, one or more pieces of input data, each of which is obtained by a different data request signal (that is, the number of input data is the same as the number of data request signals), must be acquired. Therefore, in one power consumption evaluation period, a certain corresponding relation exists between the first number of the data request signals and the second number of the operation sub-modules in the working state. And the average number (namely, the average power consumption characterization value) of the operation sub-modules in the working state in the power consumption evaluation period can characterize the average power consumption level of the operation device in the power consumption evaluation period.
Fig. 3 shows a block diagram of a vector calculation apparatus according to an exemplary embodiment of the present disclosure.
In an exemplary embodiment, the computing device may be, for example, a vector computing device 300 as shown in fig. 3. Vector computing devices are typically used to process operations between vectors or between vectors and scalars. As shown in fig. 3, the vector computing apparatus 300 includes K vector computing sub-modules, and each vector computing sub-module processes an operation between a pair of vectors or a vector and a scalar respectively in one operation cycle, that is, when one vector computing sub-module works, two input data are required to be input to the sub-module at the same time, and each input data corresponds to one data request signal.
Therefore, the corresponding relation exists between the number of the data request signals and the number of the vector calculation sub-modules in the working state, namely the number of the data request signals is 2 times of the number of the vector calculation sub-modules in the working state.
Therefore, by counting the first number of the data request signals in the power consumption evaluation period, the second number of the vector calculation sub-modules in the working state in the power consumption evaluation period can be obtained through the corresponding relation. Furthermore, the power consumption level of the vector computing device in the power consumption evaluation period can be reflected by acquiring the number of vector computing submodules (namely, average power consumption characterization values) which are in the working state in each computing period on average.
Fig. 4 shows a block diagram of a matrix multiplication apparatus according to an exemplary embodiment of the present disclosure.
In an exemplary embodiment, the arithmetic device may be, for example, a matrix multiplication device 300 as shown in fig. 4. The matrix multiplication device shown in fig. 4 includes M × N matrix multiplication submodules, which can support at most one matrix with M row vectors and one matrix with N column vectors to perform matrix inner product operation in one operation cycle, where M and N are positive integers greater than 1.
When the matrix multiplication device is applied to calculate a matrix A with M row vectors and a matrix B with N column vectors (wherein M is more than or equal to 1 and less than or equal to M, and N is more than or equal to 1 and less than or equal to N), M multiplied by N matrix multiplication sub-modules are required to carry out operation simultaneously.
When each matrix multiplication submodule performs operation, input data A (i) and input data B (j) (i belongs to [0, m ], j belongs to [0, n ]) are respectively obtained, each input data corresponds to one data request signal, and when m multiplied by n matrix multiplication submodules are required to perform operation simultaneously, the number of the data request signals is (m + n).
Therefore, it can be seen that, by counting the first number of data request signals (the number of data request signals requesting a (i) and the number of data request signals requesting b (j)) in the power consumption evaluation period, and according to the above correspondence, the second number of matrix multiplication sub-modules in the power consumption evaluation period in the working state can be obtained. Furthermore, by obtaining the number of the matrix multiplication sub-modules (i.e. the average power consumption characterization value) which are in the working state in each operation cycle on average, the power consumption level of the matrix multiplication device in the power consumption evaluation cycle can be reflected.
Fig. 5 shows a block diagram of a power consumption control apparatus according to an embodiment of the present disclosure.
In some embodiments, the power consumption control apparatus 500 may first count the number of data request signals in each operation cycle through the counting module 510, so as to obtain the number of operation sub-modules (denoted as busy _ cnt) in an operating state in the operation cycle based on a predetermined corresponding relationship and send the number to the register for storage.
In some embodiments, each busy _ cnt for a first preset number of cycles may be stored in a register, then input to an adder for summation, then input to a divider for obtaining a corresponding average power consumption characterization value.
In some embodiments, it may be preferable to set the first preset number to 2 n (n is a positive integer), so that the average power consumption characteristic value (denoted as busy _ cnt _ avg) can be obtained by first performing an arithmetic right shift on each busy _ cnt by n bits (which is equivalent to dividing by a first preset number) by using the shift register 520 shown in fig. 5, and then transmitting each shifted busy _ cnt to the adder 530 for summing. Therefore, division calculation operation can be conveniently carried out through the shift register, the calculation efficiency is improved, and the calculation resources are saved.
In some embodiments, adjusting the operating frequency of the computing device based on the power consumption assessment result may include: adjusting a power consumption control signal value represented by a binary system based on a power consumption evaluation result, wherein the power consumption evaluation result indicates whether the power consumption of the computing device exceeds a preset power consumption threshold value, and the power consumption control signal value comprises a plurality of numerical values of a second preset number; and controlling the working frequency of the operation device in a next second preset number of operation cycles after the power consumption control signal value is adjusted based on a plurality of numerical bits in the adjusted power consumption control signal value, wherein the second preset number is less than or equal to the first preset number, the plurality of numerical bits comprise a first numerical bit of which the numerical value is the first value, and the number of the first numerical bit is used for indicating the number of operation cycles in which the operation device stops working in the next second preset number of operation cycles.
Therefore, a binary power consumption control signal value is adjusted through the power consumption evaluation result, the working frequency of the operation device is correspondingly adjusted based on the signal value, the operation can be realized through the existing components (such as a register, a comparator and the like), the structure is simple, and the cost is saved; meanwhile, the power consumption control logic is simple, and the efficiency and the real-time performance of power consumption adjustment can be further improved.
In some embodiments, as shown in fig. 5, the preset power consumption threshold may be stored in the first register 550 and support the related technical personnel to maintain the same based on actual situations, so that the value thereof is not limited herein.
The power consumption evaluation result may be obtained by comparing the average power consumption characterizing value (busy _ cnt _ avg) obtained from the adder 550 and the preset power consumption threshold value obtained from the first register 550 by the comparator 540. After obtaining the power consumption evaluation result, the comparator 540 sends the power consumption evaluation result to the second register 560, and the second register 560 adjusts the power consumption control signal value stored in the second register 560 according to the power consumption evaluation result.
In some embodiments, the plurality of numerical bits further includes a second numerical bit having a second value, and obtaining the power consumption evaluation result in the power consumption evaluation period based on the average power consumption characterizing value and the preset power consumption threshold value may include: responding to the fact that the average power consumption characteristic value is larger than or equal to a preset power consumption threshold value, and determining that the power consumption evaluation result is that the power consumption of the operation device is too high; and wherein the determining the binary-represented power consumption control signal value based on the power consumption assessment result may comprise: and adjusting a second numerical bit in the power consumption control signal value to the first numerical bit in response to determining that the power consumption evaluation result is that the power consumption of the arithmetic device is too high.
In some embodiments, as shown in fig. 5, the second register 560 in the power consumption control apparatus 500 may store a power consumption control signal value having a second preset number of bits. The power consumption control signal value has a first value bit having a first value and a second value bit having a second value. The number of the first numerical bits indicates the number of cycles for the computing device to stop working in the power consumption adjustment period (i.e. the next second preset number of computing periods) after the power consumption control signal value is adjusted.
The second predetermined number needs to be less than or equal to the first predetermined number, thereby avoiding the need to evaluate and adjust the power consumption again when the adjustment effect has not yet occurred. It is understood that the second preset number can be set by a person skilled in the relevant art according to actual requirements, and is not limited herein.
For example, the first value may be "1", and the second value may be "0"; alternatively, the first value may be "0" and the second value may be "1"
In some embodiments, the power consumption control signal value stored in the second register 560 may be an 8-bit binary data (denoted as stall _ mask [7:0]), and its initial value is "00000000" (i.e., each bit is a second value), and the second register 560 may be an 8-bit register.
When the comparator 540 determines that the average power consumption characterization value (busy _ cnt _ avg) is greater than or equal to the preset power consumption threshold value through comparison, the result is correspondingly transmitted to the second register 560. The second register 560 adjusts, based on the result, one bit having an original value of "0" among the power consumption control signal values (stall _ mask [7:0]) maintained therein to "1", for example, the stall _ mask [7:0] is adjusted from an initial value of "00000000" to "00000001", and the power consumption control signal value indicates that the operation device stops operating in 1 operation cycle out of 8 operation cycles after the adjustment; for another example, the value of the power consumption control signal may indicate that the arithmetic device stops operating when 3 arithmetic cycles out of the adjusted 8 arithmetic cycles are set to "00000111" by "00000011" in the stall _ mask [7:0 ].
In some embodiments, the plurality of numerical bits further includes a second numerical bit having a second value, and obtaining the power consumption evaluation result in the power consumption evaluation period based on the average power consumption characterizing value and the preset power consumption threshold value may include: responding to the fact that the average power consumption characteristic value is smaller than a preset power consumption threshold value, and determining that the power consumption evaluation result is that the power consumption of the operation device is normal; and wherein the determining the binary-represented power consumption control signal value based on the power consumption assessment result may comprise: and adjusting one first numerical bit in the power consumption control signal value to be a second numerical bit in response to the power consumption evaluation result being that the power consumption of the arithmetic device is normal and the power consumption control signal value comprises the first numerical bit.
In some embodiments, when the comparator 540 determines that the average power consumption characterizing value (busy _ cnt _ avg) is smaller than the preset power consumption threshold value through comparison, the result is correspondingly transmitted to the second register 560. Based on the result, the second register 560 can adjust the power consumption control signal value (stall _ mask [7:0]) to maintain it accordingly.
When the original value in the stall _ mask [7:0] includes "1", a bit whose original value in the stall _ mask [7:0] is "1" may be adjusted to "0". For example, if stall _ mask [7:0] is adjusted from the initial value "00000111" to "00000011", the power consumption control signal value may indicate that the arithmetic device stops operating in 2 arithmetic cycles out of the adjusted 8 arithmetic cycles (3 cycles stop operating every 8 cycles before the adjustment).
In some embodiments, determining the binary-represented power consumption control signal value based on the power consumption evaluation result may further include: and in response to determining that the power consumption evaluation result is that the power consumption of the arithmetic device is normal and each numerical bit in the power consumption control signal value is the second numerical bit, determining that each numerical bit in the power consumption control signal value is still the second numerical bit.
In some embodiments, when the power consumption evaluation result obtained from the comparator 540 is that the average power consumption characterizing value (busy _ cnt _ avg) is smaller than the preset power consumption threshold value, and the original value of the power consumption control signal value stall _ mask [7:0] is the initial value of "000000000000", no adjustment may be made to the power consumption control signal value stall _ mask [7:0], and "000000000000" may still be maintained (i.e. the computing device operates normally in each of the following 8 computing cycles).
In some embodiments, controlling the operating frequency of the arithmetic device in a next second preset number of arithmetic cycles after the adjusting of the power consumption control signal value based on the plurality of numerical bits in the adjusted power consumption control signal value may include: generating an instruction issue blocking signal based on a third number of second numerical bits in the adjusted power consumption control signal value; and sending the instruction issuing blocking signal to an instruction analysis device used for sending the operation instruction to the operation device so as to prevent the instruction analysis device from stopping issuing the operation instruction in a third number of operation cycles in a next second preset number of operation cycles.
Therefore, based on the adjusted power consumption control signal value, an instruction issuing blocking signal is generated, so that the number of the periods for stopping issuing the instruction in the next power consumption adjusting period is reduced, the power consumption level of the operation device is controlled by adjusting the working frequency of the operation device, and the normal operation of other components (such as a storage device, a control device and the like) in the chip is not influenced while the power consumption level of the operation device is effectively controlled.
In some embodiments, as shown in fig. 5, after the power consumption control signal value in the second register 560 is adjusted, the second register 560 generates an instruction issue blocking signal based on the adjusted power consumption control signal value, and sends the instruction issue blocking signal to an instruction parsing apparatus (not shown).
In some embodiments, after receiving the instruction issue blocking signal, the instruction analysis device may know that the instruction (i.e., the calculation enable signal and the data request signal) needs to be stopped to issue in a next second predetermined number of operation cycles, so as to control the operation device to stop working in the cycle.
In some embodiments, after acquiring the information, the instruction parsing device may randomly select a period (the number is the same as the number of the first value in the power consumption control signal value) for stopping issuing the instruction.
In some embodiments, as shown in fig. 5, the second register 560 may also generate an instruction issue blocking signal 502 based on its stored power consumption control signal value 501, for example, if the power consumption control signal value 501 is "00001111", then the corresponding generated instruction issue blocking signal 502 is a corresponding window signal. After receiving the instruction issue blocking signal 502, the instruction analysis device may stop issuing instructions based on 4 operation cycles indicated by the window of the signal.
In some embodiments, the power consumption control method for an arithmetic device of an embodiment of the present disclosure may further include: after the power consumption control signal value is adjusted, responding to a third preset number of operation cycles, and then obtaining an average power consumption representation value of the operation device in the latest power consumption evaluation cycle to determine a power consumption evaluation result of the operation device in the latest power consumption evaluation cycle, wherein the third preset number is greater than or equal to the first preset number; and re-determining the power consumption control signal value based on a power consumption evaluation result of the operation device in the latest power consumption evaluation period.
Therefore, by setting the interval period (that is, the third preset number of operation periods), after the power consumption is adjusted once, the comparison of the power consumption data and the adjustment of the power consumption control signal value in the register are performed after the interval period, so that the frequency of the power consumption adjustment can be controlled based on the interval period, and the power consumption adjustment of the operation device can be made smoother.
In some embodiments, when a third preset number of operation cycles (i.e., interval cycles) are set, the average power consumption characterization value is not compared with the preset power consumption threshold value and the power consumption control signal value is not adjusted in the third preset number of operation cycles after the power consumption control signal value is adjusted once. In the interval period, the arithmetic device operates at the adjusted operating frequency.
In some embodiments, the third preset period may be greater than or equal to the first preset period, so that it can be avoided that when the next comparison is triggered, the obtained average power consumption characterization value is still the result of the last statistics, which affects the power consumption evaluation result and the power consumption adjustment effect of the comparison. It is understood that the third preset number can be set by a person skilled in the art according to actual requirements, and for example, can be an integer multiple of the first preset period, which is not limited herein.
In some embodiments, as shown in fig. 6, there is also provided a power consumption control apparatus 600 for a computing apparatus, which may include: a first obtaining unit 610 configured to obtain a first number of data request signals within a power consumption evaluation period, wherein the power consumption evaluation period includes a first preset number of consecutive operation periods, and the data request signals are used for requesting input data of the operation device; a second obtaining unit 620 configured to obtain an average power consumption characterizing value of the arithmetic device in a power consumption evaluation period based on the first number; a third obtaining unit 630, configured to obtain a power consumption evaluation result in a power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold; and an adjusting unit 640 configured to adjust an operating frequency of the arithmetic device based on the power consumption evaluation result.
The operations of the units 610 to 640 in the power consumption control apparatus 600 are similar to the operations of the steps S101 to S104 in the power consumption control method for an arithmetic device, and are not described herein again.
In some embodiments, the operation device may include a plurality of operation sub-modules, and the second obtaining unit may include: a first acquisition subunit configured to acquire, based on the first number, a second number of operation submodules in the operation device in an operating state in the power consumption evaluation period; and a second obtaining subunit configured to obtain, based on the second number, an average power consumption characterizing value of the arithmetic device in the power consumption evaluation period.
In some embodiments, the adjusting unit may include: an adjusting subunit configured to adjust a power consumption control signal value represented by a binary system based on a power consumption evaluation result, wherein the power consumption evaluation result indicates whether the power consumption of the arithmetic device exceeds a preset power consumption threshold, and the power consumption control signal value includes a second preset number of a plurality of numerical bits; and a control subunit configured to control, based on a plurality of numerical bits in the adjusted power consumption control signal value, an operating frequency of the operation device in a next second preset number of the plurality of operation cycles after the power consumption control signal value is adjusted, wherein the second preset number is less than or equal to the first preset number, the plurality of numerical bits include a first numerical bit having a first value, and the number of the first numerical bit is used to indicate a number of operation cycles in which the operation device stops operating in the next second preset number of the plurality of operation cycles.
In some embodiments, the plurality of numerical bits further includes a second numerical bit having a second value, and the third obtaining unit may include: the first determining subunit is configured to determine that the power consumption evaluation result is that the power consumption of the computing device is too high in response to that the average power consumption characterization value is greater than or equal to a preset power consumption threshold value; and wherein the adjusting subunit may be configured to: and adjusting a second numerical bit in the power consumption control signal value to the first numerical bit in response to determining that the power consumption evaluation result is that the power consumption of the arithmetic device is too high.
In some embodiments, the plurality of numerical bits further includes a second numerical bit having a second value, and the third obtaining unit may include: the second determining subunit is configured to determine that the power consumption evaluation result is that the power consumption of the computing device is normal in response to the average power consumption characterization value being smaller than the preset power consumption threshold value; and wherein the adjustment subunit may be configured to: and adjusting one first numerical bit in the power consumption control signal value to be a second numerical bit in response to the power consumption evaluation result being that the power consumption of the arithmetic device is normal and the power consumption control signal value comprises the first numerical bit.
In some embodiments, the adjustment subunit may be further configured to: and in response to determining that the power consumption evaluation result is that the power consumption of the arithmetic device is normal and each numerical bit in the power consumption control signal value is the second numerical bit, determining that each numerical bit in the power consumption control signal value is still the second numerical bit.
In some embodiments, the control subunit may include: a generation module configured to generate an instruction issue blocking signal based on a third number of second numerical bits in the adjusted power consumption control signal value; and the sending module is configured to send the instruction issuing blocking signal to an instruction analysis device used for sending the operation instruction to the operation device so as to prevent the instruction analysis device from stopping issuing the operation instruction in a third number of operation cycles in a next second preset number of operation cycles.
In some embodiments, the power consumption control device for a computing device of an embodiment of the present disclosure may further include: a fourth obtaining unit, configured to obtain an average power consumption characterization value of the operation device in a latest power consumption evaluation period in response to a third preset number of operation periods after the power consumption control signal value is adjusted, so as to determine a power consumption evaluation result of the operation device in the latest power consumption evaluation period, where the third preset number is greater than or equal to the first preset number; and a determination unit configured to re-determine the power consumption control signal value based on a power consumption evaluation result of the arithmetic device in a latest power consumption evaluation period.
In some embodiments, there is provided a chip comprising the above power consumption control apparatus for an arithmetic apparatus.
In some embodiments, an electronic device is provided, comprising the chip described above.
In some embodiments, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the power consumption control method for the arithmetic device.
In some embodiments, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the above-described power consumption control method for an arithmetic device.
In some embodiments, a computer program product is provided, comprising a computer program, wherein the computer program realizes the above-described power consumption control method for a computing device when executed by a processor.
According to an embodiment of the present disclosure, there is also provided an electronic device, a readable storage medium, and a computer program product.
Referring to fig. 7, a block diagram of a structure of an electronic device 700, which may be a server or a client of the present disclosure, which is an example of a hardware device that may be applied to aspects of the present disclosure, will now be described. Electronic device is intended to represent various forms of digital electronic computer devices, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 7, the electronic device 700 includes a computing unit 701, which may perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM)702 or a computer program loaded from a storage unit 708 into a Random Access Memory (RAM) 703. In the RAM703, various programs and data required for the operation of the electronic device 700 can also be stored. The computing unit 701, the ROM 702, and the RAM703 are connected to each other by a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.
A number of components in the electronic device 700 are connected to the I/O interface 705, including: an input unit 706, an output unit 707, a storage unit 708, and a communication unit 709. The input unit 706 may be any type of device capable of inputting information to the electronic device 700, and the input unit 706 may receive input numeric or character information and generate key signal inputs related to user settings and/or function controls of the electronic device, and may include, but is not limited to, a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and/or a remote controller. Output unit 707 may be any type of device capable of presenting information and may include, but is not limited to, a display, speakers, a video/audio output terminal, a vibrator, and/or a printer. Storage unit 708 may include, but is not limited to, magnetic or optical disks. The communication unit 709 allows the electronic device 700 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and/or chipsets, such as bluetooth (TM) devices, 802.11 devices, WiFi devices, WiMax devices, cellular communication devices, and/or the like.
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.
The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server with a combined blockchain.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be performed in parallel, sequentially or in different orders, and are not limited herein as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved.
Although embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it is to be understood that the above-described methods, systems and apparatus are merely exemplary embodiments or examples and that the scope of the present invention is not limited by these embodiments or examples, but only by the claims as issued and their equivalents. Various elements in the embodiments or examples may be omitted or may be replaced with equivalents thereof. Further, the steps may be performed in an order different from that described in the present disclosure. Further, various elements in the embodiments or examples may be combined in various ways. It is important that as technology evolves, many of the elements described herein may be replaced with equivalent elements that appear after the present disclosure.
Claims (21)
1. A power consumption control method for an arithmetic device, the method comprising:
acquiring a first number of data request signals in a power consumption evaluation period, wherein the power consumption evaluation period comprises a first preset number of continuous operation periods, and the data request signals are used for requesting input data of the operation device;
acquiring an average power consumption characterization value of the operation device in the power consumption evaluation period based on the first quantity;
acquiring a power consumption evaluation result in the power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value; and
and adjusting the working frequency of the arithmetic device based on the power consumption evaluation result.
2. The method of claim 1, wherein the computing device includes a plurality of computing sub-modules, and wherein obtaining an average power consumption characterization value for the computing device over the power consumption evaluation period based on the first number comprises:
acquiring a second number of operation sub-modules in the operation device in the working state in the power consumption evaluation period based on the first number; and
and acquiring an average power consumption characterization value of the operation device in the power consumption evaluation period based on the second quantity.
3. The method of claim 1, wherein the adjusting the operating frequency of the computing device based on the power consumption assessment result comprises:
adjusting a binary-expressed power consumption control signal value based on the power consumption evaluation result, wherein the power consumption evaluation result indicates whether the power consumption of the computing device exceeds the preset power consumption threshold value, and the power consumption control signal value comprises a second preset number of a plurality of numerical value bits; and
controlling the working frequency of the operation device in a plurality of operation cycles of a next second preset number after the power consumption control signal value is adjusted based on a plurality of numerical bits in the adjusted power consumption control signal value, wherein the second preset number is less than or equal to the first preset number, the plurality of numerical bits comprise a first numerical bit of which the numerical value is a first value, and the number of the first numerical bit is used for indicating the number of operation cycles of stopping the operation of the operation device in the plurality of operation cycles of the next second preset number.
4. The method of claim 3, wherein the plurality of numerical bits further includes a second numerical bit having a second value, and the obtaining the power consumption evaluation result in the power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value comprises:
in response to that the average power consumption characterization value is larger than or equal to the preset power consumption threshold value, determining that the power consumption evaluation result is that the power consumption of the operation device is too high; and wherein the one or more of the one or more,
determining a binary-represented power consumption control signal value based on the power consumption assessment result comprises:
adjusting a second numerical bit of the power consumption control signal value to a first numerical bit in response to determining that the power consumption evaluation result is that the computing device consumes too much power.
5. The method of claim 3, wherein the plurality of numerical bits further includes a second numerical bit having a second value, and the obtaining the power consumption evaluation result in the power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value comprises:
responding to the fact that the average power consumption characterization value is smaller than the preset power consumption threshold value, and determining that the power consumption evaluation result is that the power consumption of the operation device is normal; and wherein the (a) and (b) are,
determining a binary-represented power consumption control signal value based on the power consumption assessment result comprises:
adjusting one first numerical bit of the power consumption control signal values to a second numerical bit in response to determining that the power consumption evaluation result is that the computing device consumes normal power and the power consumption control signal values include the first numerical bit.
6. The method of claim 5, wherein determining a binary-represented power consumption control signal value based on the power consumption assessment result further comprises:
and in response to determining that the power consumption evaluation result is that the computing device consumes normal power and each numerical bit in the power consumption control signal value is a second numerical bit, determining that each numerical bit in the power consumption control signal value is still the second numerical bit.
7. The method of any of claims 3 to 6, wherein the controlling the operating frequency of the computing device in a next second preset number of computing cycles after adjusting the power consumption control signal value based on the number of numerical bits in the adjusted power consumption control signal value comprises:
generating an instruction issue blocking signal based on a third number of second numerical bits in the adjusted power consumption control signal value; and
and sending the instruction issuing prevention signal to an instruction analysis device used for sending the operation instruction to the operation device so as to prevent the instruction analysis device from stopping issuing the operation instruction in a third number of operation cycles in the next second preset number of operation cycles.
8. The method of any of claims 3 to 7, further comprising:
after the power consumption control signal value is adjusted, responding to a third preset number of operation cycles, and then obtaining an average power consumption representation value of the operation device in the latest power consumption evaluation cycle to determine a power consumption evaluation result of the operation device in the latest power consumption evaluation cycle, wherein the third preset number is greater than or equal to the first preset number; and
re-determining the power consumption control signal value based on a power consumption evaluation result of the arithmetic device in a latest power consumption evaluation period.
9. A power consumption control apparatus for an arithmetic apparatus, the power consumption control apparatus comprising:
a first acquisition unit configured to acquire a first number of data request signals within a power consumption evaluation period, wherein the power consumption evaluation period includes a first preset number of consecutive operation periods, and the data request signals are used for requesting input data of the operation device;
a second obtaining unit configured to obtain an average power consumption characterization value of the arithmetic device in the power consumption evaluation period based on the first number;
a third obtaining unit, configured to obtain a power consumption evaluation result in the power consumption evaluation period based on the average power consumption characterization value and a preset power consumption threshold value; and
an adjusting unit configured to adjust an operating frequency of the arithmetic device based on the power consumption evaluation result.
10. The power consumption control apparatus according to claim 9, wherein the arithmetic means includes a plurality of arithmetic sub-modules, the second acquisition unit includes:
a first obtaining subunit configured to obtain, based on the first number, a second number of operation sub-modules in the operation device that is in an operating state in the power consumption evaluation period; and
a second obtaining subunit configured to obtain, based on the second number, an average power consumption characterizing value of the arithmetic device in the power consumption evaluation period.
11. The power consumption control apparatus according to claim 9, wherein the adjusting unit includes:
an adjusting subunit configured to adjust a binary-represented power consumption control signal value based on the power consumption evaluation result, wherein the power consumption evaluation result indicates whether the power consumption of the computing device exceeds the preset power consumption threshold, and the power consumption control signal value includes a second preset number of a plurality of numerical bits; and
a control subunit configured to control an operating frequency of the arithmetic device in a next second preset number of multiple operation cycles after the power consumption control signal value is adjusted based on a plurality of numerical bits in the adjusted power consumption control signal value, where the second preset number is less than or equal to the first preset number, the plurality of numerical bits include a first numerical bit whose numerical value is a first value, and the number of the first numerical bit is used to indicate a number of operation cycles in which the arithmetic device stops operating in the next second preset number of multiple operation cycles.
12. The power consumption control apparatus according to claim 11, wherein the plurality of numerical bits further includes a second numerical bit whose numerical value is a second value, the third obtaining unit includes:
a first determining subunit, configured to determine that the power consumption evaluation result is that the power consumption of the computing device is too high in response to that the average power consumption characterization value is greater than or equal to the preset power consumption threshold; and wherein the one or more of the one or more,
the adjustment subunit is configured to:
adjusting a second numerical bit of the power consumption control signal value to a first numerical bit in response to determining that the power consumption evaluation result is that the computing device consumes too much power.
13. The power consumption control apparatus according to claim 11, wherein the plurality of numerical bits further includes a second numerical bit whose numerical value is a second value, the third obtaining unit includes:
a second determining subunit, configured to determine, in response to the average power consumption characterization value being smaller than the preset power consumption threshold value, that the power consumption evaluation result is that the power consumption of the computing device is normal; and wherein the one or more of the one or more,
the adjustment subunit is configured to:
adjusting one first numerical bit of the power consumption control signal values to a second numerical bit in response to determining that the power consumption evaluation result is that the computing device consumes normal power and the power consumption control signal values include the first numerical bit.
14. The power consumption control apparatus of claim 13, wherein the adjustment subunit is further configured to:
and in response to determining that the power consumption evaluation result is that the computing device consumes normal power and each numerical bit in the power consumption control signal value is a second numerical bit, determining that each numerical bit in the power consumption control signal value is still the second numerical bit.
15. The power consumption control apparatus according to any one of claims 11 to 14, wherein the control subunit includes:
a generation module configured to generate an instruction issue blocking signal based on a third number of second numerical bits in the adjusted power consumption control signal value; and
a sending module configured to send the instruction issue blocking signal to an instruction analysis device for sending an operation instruction to the operation device, so as to prevent the instruction analysis device from stopping issuing the operation instruction in a third number of operation cycles in the next second preset number of operation cycles.
16. The power consumption control apparatus according to any one of claims 11 to 15, further comprising:
a fourth obtaining unit, configured to obtain an average power consumption characterization value of the computing device in a latest power consumption evaluation period in response to a third preset number of computing periods after the power consumption control signal value is adjusted, so as to determine a power consumption evaluation result of the computing device in the latest power consumption evaluation period, where the third preset number is greater than or equal to the first preset number; and
a determination unit configured to re-determine the power consumption control signal value based on a power consumption evaluation result of the arithmetic device in a latest power consumption evaluation period.
17. A chip comprising the apparatus of any one of claims 9-16.
18. An electronic device comprising the chip of claim 17.
19. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.
20. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-8.
21. A computer program product comprising a computer program, wherein the computer program realizes the method of any one of claims 1-8 when executed by a processor.
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